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targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.c@1:f30bdcd2b33b, 2017-02-27 (annotated)
- Committer:
- jacobjohnson
- Date:
- Mon Feb 27 17:45:05 2017 +0000
- Revision:
- 1:f30bdcd2b33b
- Parent:
- 0:098463de4c5d
changed the inputscale from 1 to 7 in analogin_api.c. This will need to be changed later, and accessed from the main level, but for now this allows the adc to read a value from 0 to 3.7V, instead of just up to 1V.;
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| group-onsemi | 0:098463de4c5d | 1 | /** |
| group-onsemi | 0:098463de4c5d | 2 | ****************************************************************************** |
| group-onsemi | 0:098463de4c5d | 3 | * @file stm32f4xx_hal_rtc.c |
| group-onsemi | 0:098463de4c5d | 4 | * @author MCD Application Team |
| group-onsemi | 0:098463de4c5d | 5 | * @version V1.5.0 |
| group-onsemi | 0:098463de4c5d | 6 | * @date 06-May-2016 |
| group-onsemi | 0:098463de4c5d | 7 | * @brief RTC HAL module driver. |
| group-onsemi | 0:098463de4c5d | 8 | * This file provides firmware functions to manage the following |
| group-onsemi | 0:098463de4c5d | 9 | * functionalities of the Real Time Clock (RTC) peripheral: |
| group-onsemi | 0:098463de4c5d | 10 | * + Initialization and de-initialization functions |
| group-onsemi | 0:098463de4c5d | 11 | * + RTC Time and Date functions |
| group-onsemi | 0:098463de4c5d | 12 | * + RTC Alarm functions |
| group-onsemi | 0:098463de4c5d | 13 | * + Peripheral Control functions |
| group-onsemi | 0:098463de4c5d | 14 | * + Peripheral State functions |
| group-onsemi | 0:098463de4c5d | 15 | * |
| group-onsemi | 0:098463de4c5d | 16 | @verbatim |
| group-onsemi | 0:098463de4c5d | 17 | ============================================================================== |
| group-onsemi | 0:098463de4c5d | 18 | ##### Backup Domain Operating Condition ##### |
| group-onsemi | 0:098463de4c5d | 19 | ============================================================================== |
| group-onsemi | 0:098463de4c5d | 20 | [..] The real-time clock (RTC), the RTC backup registers, and the backup |
| group-onsemi | 0:098463de4c5d | 21 | SRAM (BKP SRAM) can be powered from the VBAT voltage when the main |
| group-onsemi | 0:098463de4c5d | 22 | VDD supply is powered off. |
| group-onsemi | 0:098463de4c5d | 23 | To retain the content of the RTC backup registers, backup SRAM, and supply |
| group-onsemi | 0:098463de4c5d | 24 | the RTC when VDD is turned off, VBAT pin can be connected to an optional |
| group-onsemi | 0:098463de4c5d | 25 | standby voltage supplied by a battery or by another source. |
| group-onsemi | 0:098463de4c5d | 26 | |
| group-onsemi | 0:098463de4c5d | 27 | [..] To allow the RTC operating even when the main digital supply (VDD) is turned |
| group-onsemi | 0:098463de4c5d | 28 | off, the VBAT pin powers the following blocks: |
| group-onsemi | 0:098463de4c5d | 29 | (#) The RTC |
| group-onsemi | 0:098463de4c5d | 30 | (#) The LSE oscillator |
| group-onsemi | 0:098463de4c5d | 31 | (#) The backup SRAM when the low power backup regulator is enabled |
| group-onsemi | 0:098463de4c5d | 32 | (#) PC13 to PC15 I/Os, plus PI8 I/O (when available) |
| group-onsemi | 0:098463de4c5d | 33 | |
| group-onsemi | 0:098463de4c5d | 34 | [..] When the backup domain is supplied by VDD (analog switch connected to VDD), |
| group-onsemi | 0:098463de4c5d | 35 | the following pins are available: |
| group-onsemi | 0:098463de4c5d | 36 | (#) PC14 and PC15 can be used as either GPIO or LSE pins |
| group-onsemi | 0:098463de4c5d | 37 | (#) PC13 can be used as a GPIO or as the RTC_AF1 pin |
| group-onsemi | 0:098463de4c5d | 38 | (#) PI8 can be used as a GPIO or as the RTC_AF2 pin |
| group-onsemi | 0:098463de4c5d | 39 | |
| group-onsemi | 0:098463de4c5d | 40 | [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT |
| group-onsemi | 0:098463de4c5d | 41 | because VDD is not present), the following pins are available: |
| group-onsemi | 0:098463de4c5d | 42 | (#) PC14 and PC15 can be used as LSE pins only |
| group-onsemi | 0:098463de4c5d | 43 | (#) PC13 can be used as the RTC_AF1 pin |
| group-onsemi | 0:098463de4c5d | 44 | (#) PI8 can be used as the RTC_AF2 pin |
| group-onsemi | 0:098463de4c5d | 45 | |
| group-onsemi | 0:098463de4c5d | 46 | ##### Backup Domain Reset ##### |
| group-onsemi | 0:098463de4c5d | 47 | ================================================================== |
| group-onsemi | 0:098463de4c5d | 48 | [..] The backup domain reset sets all RTC registers and the RCC_BDCR register |
| group-onsemi | 0:098463de4c5d | 49 | to their reset values. The BKPSRAM is not affected by this reset. The only |
| group-onsemi | 0:098463de4c5d | 50 | way to reset the BKPSRAM is through the Flash interface by requesting |
| group-onsemi | 0:098463de4c5d | 51 | a protection level change from 1 to 0. |
| group-onsemi | 0:098463de4c5d | 52 | [..] A backup domain reset is generated when one of the following events occurs: |
| group-onsemi | 0:098463de4c5d | 53 | (#) Software reset, triggered by setting the BDRST bit in the |
| group-onsemi | 0:098463de4c5d | 54 | RCC Backup domain control register (RCC_BDCR). |
| group-onsemi | 0:098463de4c5d | 55 | (#) VDD or VBAT power on, if both supplies have previously been powered off. |
| group-onsemi | 0:098463de4c5d | 56 | |
| group-onsemi | 0:098463de4c5d | 57 | ##### Backup Domain Access ##### |
| group-onsemi | 0:098463de4c5d | 58 | ================================================================== |
| group-onsemi | 0:098463de4c5d | 59 | [..] After reset, the backup domain (RTC registers, RTC backup data |
| group-onsemi | 0:098463de4c5d | 60 | registers and backup SRAM) is protected against possible unwanted write |
| group-onsemi | 0:098463de4c5d | 61 | accesses. |
| group-onsemi | 0:098463de4c5d | 62 | [..] To enable access to the RTC Domain and RTC registers, proceed as follows: |
| group-onsemi | 0:098463de4c5d | 63 | (+) Enable the Power Controller (PWR) APB1 interface clock using the |
| group-onsemi | 0:098463de4c5d | 64 | __HAL_RCC_PWR_CLK_ENABLE() function. |
| group-onsemi | 0:098463de4c5d | 65 | (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. |
| group-onsemi | 0:098463de4c5d | 66 | (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. |
| group-onsemi | 0:098463de4c5d | 67 | (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. |
| group-onsemi | 0:098463de4c5d | 68 | |
| group-onsemi | 0:098463de4c5d | 69 | |
| group-onsemi | 0:098463de4c5d | 70 | ##### How to use this driver ##### |
| group-onsemi | 0:098463de4c5d | 71 | ================================================================== |
| group-onsemi | 0:098463de4c5d | 72 | [..] |
| group-onsemi | 0:098463de4c5d | 73 | (+) Enable the RTC domain access (see description in the section above). |
| group-onsemi | 0:098463de4c5d | 74 | (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour |
| group-onsemi | 0:098463de4c5d | 75 | format using the HAL_RTC_Init() function. |
| group-onsemi | 0:098463de4c5d | 76 | |
| group-onsemi | 0:098463de4c5d | 77 | *** Time and Date configuration *** |
| group-onsemi | 0:098463de4c5d | 78 | =================================== |
| group-onsemi | 0:098463de4c5d | 79 | [..] |
| group-onsemi | 0:098463de4c5d | 80 | (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() |
| group-onsemi | 0:098463de4c5d | 81 | and HAL_RTC_SetDate() functions. |
| group-onsemi | 0:098463de4c5d | 82 | (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. |
| group-onsemi | 0:098463de4c5d | 83 | |
| group-onsemi | 0:098463de4c5d | 84 | *** Alarm configuration *** |
| group-onsemi | 0:098463de4c5d | 85 | =========================== |
| group-onsemi | 0:098463de4c5d | 86 | [..] |
| group-onsemi | 0:098463de4c5d | 87 | (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. |
| group-onsemi | 0:098463de4c5d | 88 | You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function. |
| group-onsemi | 0:098463de4c5d | 89 | (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. |
| group-onsemi | 0:098463de4c5d | 90 | |
| group-onsemi | 0:098463de4c5d | 91 | ##### RTC and low power modes ##### |
| group-onsemi | 0:098463de4c5d | 92 | ================================================================== |
| group-onsemi | 0:098463de4c5d | 93 | [..] The MCU can be woken up from a low power mode by an RTC alternate |
| group-onsemi | 0:098463de4c5d | 94 | function. |
| group-onsemi | 0:098463de4c5d | 95 | [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), |
| group-onsemi | 0:098463de4c5d | 96 | RTC wake-up, RTC tamper event detection and RTC time stamp event detection. |
| group-onsemi | 0:098463de4c5d | 97 | These RTC alternate functions can wake up the system from the Stop and |
| group-onsemi | 0:098463de4c5d | 98 | Standby low power modes. |
| group-onsemi | 0:098463de4c5d | 99 | [..] The system can also wake up from low power modes without depending |
| group-onsemi | 0:098463de4c5d | 100 | on an external interrupt (Auto-wake-up mode), by using the RTC alarm |
| group-onsemi | 0:098463de4c5d | 101 | or the RTC wake-up events. |
| group-onsemi | 0:098463de4c5d | 102 | [..] The RTC provides a programmable time base for waking up from the |
| group-onsemi | 0:098463de4c5d | 103 | Stop or Standby mode at regular intervals. |
| group-onsemi | 0:098463de4c5d | 104 | Wake-up from STOP and STANDBY modes is possible only when the RTC clock source |
| group-onsemi | 0:098463de4c5d | 105 | is LSE or LSI. |
| group-onsemi | 0:098463de4c5d | 106 | |
| group-onsemi | 0:098463de4c5d | 107 | @endverbatim |
| group-onsemi | 0:098463de4c5d | 108 | ****************************************************************************** |
| group-onsemi | 0:098463de4c5d | 109 | * @attention |
| group-onsemi | 0:098463de4c5d | 110 | * |
| group-onsemi | 0:098463de4c5d | 111 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| group-onsemi | 0:098463de4c5d | 112 | * |
| group-onsemi | 0:098463de4c5d | 113 | * Redistribution and use in source and binary forms, with or without modification, |
| group-onsemi | 0:098463de4c5d | 114 | * are permitted provided that the following conditions are met: |
| group-onsemi | 0:098463de4c5d | 115 | * 1. Redistributions of source code must retain the above copyright notice, |
| group-onsemi | 0:098463de4c5d | 116 | * this list of conditions and the following disclaimer. |
| group-onsemi | 0:098463de4c5d | 117 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| group-onsemi | 0:098463de4c5d | 118 | * this list of conditions and the following disclaimer in the documentation |
| group-onsemi | 0:098463de4c5d | 119 | * and/or other materials provided with the distribution. |
| group-onsemi | 0:098463de4c5d | 120 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| group-onsemi | 0:098463de4c5d | 121 | * may be used to endorse or promote products derived from this software |
| group-onsemi | 0:098463de4c5d | 122 | * without specific prior written permission. |
| group-onsemi | 0:098463de4c5d | 123 | * |
| group-onsemi | 0:098463de4c5d | 124 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| group-onsemi | 0:098463de4c5d | 125 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| group-onsemi | 0:098463de4c5d | 126 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| group-onsemi | 0:098463de4c5d | 127 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| group-onsemi | 0:098463de4c5d | 128 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| group-onsemi | 0:098463de4c5d | 129 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| group-onsemi | 0:098463de4c5d | 130 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| group-onsemi | 0:098463de4c5d | 131 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| group-onsemi | 0:098463de4c5d | 132 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| group-onsemi | 0:098463de4c5d | 133 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| group-onsemi | 0:098463de4c5d | 134 | * |
| group-onsemi | 0:098463de4c5d | 135 | ****************************************************************************** |
| group-onsemi | 0:098463de4c5d | 136 | */ |
| group-onsemi | 0:098463de4c5d | 137 | |
| group-onsemi | 0:098463de4c5d | 138 | /* Includes ------------------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 139 | #include "stm32f4xx_hal.h" |
| group-onsemi | 0:098463de4c5d | 140 | |
| group-onsemi | 0:098463de4c5d | 141 | /** @addtogroup STM32F4xx_HAL_Driver |
| group-onsemi | 0:098463de4c5d | 142 | * @{ |
| group-onsemi | 0:098463de4c5d | 143 | */ |
| group-onsemi | 0:098463de4c5d | 144 | |
| group-onsemi | 0:098463de4c5d | 145 | /** @defgroup RTC RTC |
| group-onsemi | 0:098463de4c5d | 146 | * @brief RTC HAL module driver |
| group-onsemi | 0:098463de4c5d | 147 | * @{ |
| group-onsemi | 0:098463de4c5d | 148 | */ |
| group-onsemi | 0:098463de4c5d | 149 | |
| group-onsemi | 0:098463de4c5d | 150 | #ifdef HAL_RTC_MODULE_ENABLED |
| group-onsemi | 0:098463de4c5d | 151 | |
| group-onsemi | 0:098463de4c5d | 152 | /* Private typedef -----------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 153 | /* Private define ------------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 154 | /* Private macro -------------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 155 | /* Private variables ---------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 156 | /* Private function prototypes -----------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 157 | /* Private functions ---------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 158 | |
| group-onsemi | 0:098463de4c5d | 159 | /** @defgroup RTC_Exported_Functions RTC Exported Functions |
| group-onsemi | 0:098463de4c5d | 160 | * @{ |
| group-onsemi | 0:098463de4c5d | 161 | */ |
| group-onsemi | 0:098463de4c5d | 162 | |
| group-onsemi | 0:098463de4c5d | 163 | /** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions |
| group-onsemi | 0:098463de4c5d | 164 | * @brief Initialization and Configuration functions |
| group-onsemi | 0:098463de4c5d | 165 | * |
| group-onsemi | 0:098463de4c5d | 166 | @verbatim |
| group-onsemi | 0:098463de4c5d | 167 | =============================================================================== |
| group-onsemi | 0:098463de4c5d | 168 | ##### Initialization and de-initialization functions ##### |
| group-onsemi | 0:098463de4c5d | 169 | =============================================================================== |
| group-onsemi | 0:098463de4c5d | 170 | [..] This section provides functions allowing to initialize and configure the |
| group-onsemi | 0:098463de4c5d | 171 | RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable |
| group-onsemi | 0:098463de4c5d | 172 | RTC registers Write protection, enter and exit the RTC initialization mode, |
| group-onsemi | 0:098463de4c5d | 173 | RTC registers synchronization check and reference clock detection enable. |
| group-onsemi | 0:098463de4c5d | 174 | (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. |
| group-onsemi | 0:098463de4c5d | 175 | It is split into 2 programmable prescalers to minimize power consumption. |
| group-onsemi | 0:098463de4c5d | 176 | (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler. |
| group-onsemi | 0:098463de4c5d | 177 | (++) When both prescalers are used, it is recommended to configure the |
| group-onsemi | 0:098463de4c5d | 178 | asynchronous prescaler to a high value to minimize power consumption. |
| group-onsemi | 0:098463de4c5d | 179 | (#) All RTC registers are Write protected. Writing to the RTC registers |
| group-onsemi | 0:098463de4c5d | 180 | is enabled by writing a key into the Write Protection register, RTC_WPR. |
| group-onsemi | 0:098463de4c5d | 181 | (#) To configure the RTC Calendar, user application should enter |
| group-onsemi | 0:098463de4c5d | 182 | initialization mode. In this mode, the calendar counter is stopped |
| group-onsemi | 0:098463de4c5d | 183 | and its value can be updated. When the initialization sequence is |
| group-onsemi | 0:098463de4c5d | 184 | complete, the calendar restarts counting after 4 RTCCLK cycles. |
| group-onsemi | 0:098463de4c5d | 185 | (#) To read the calendar through the shadow registers after Calendar |
| group-onsemi | 0:098463de4c5d | 186 | initialization, calendar update or after wake-up from low power modes |
| group-onsemi | 0:098463de4c5d | 187 | the software must first clear the RSF flag. The software must then |
| group-onsemi | 0:098463de4c5d | 188 | wait until it is set again before reading the calendar, which means |
| group-onsemi | 0:098463de4c5d | 189 | that the calendar registers have been correctly copied into the |
| group-onsemi | 0:098463de4c5d | 190 | RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function |
| group-onsemi | 0:098463de4c5d | 191 | implements the above software sequence (RSF clear and RSF check). |
| group-onsemi | 0:098463de4c5d | 192 | |
| group-onsemi | 0:098463de4c5d | 193 | @endverbatim |
| group-onsemi | 0:098463de4c5d | 194 | * @{ |
| group-onsemi | 0:098463de4c5d | 195 | */ |
| group-onsemi | 0:098463de4c5d | 196 | |
| group-onsemi | 0:098463de4c5d | 197 | /** |
| group-onsemi | 0:098463de4c5d | 198 | * @brief Initializes the RTC peripheral |
| group-onsemi | 0:098463de4c5d | 199 | * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains |
| group-onsemi | 0:098463de4c5d | 200 | * the configuration information for RTC. |
| group-onsemi | 0:098463de4c5d | 201 | * @retval HAL status |
| group-onsemi | 0:098463de4c5d | 202 | */ |
| group-onsemi | 0:098463de4c5d | 203 | HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) |
| group-onsemi | 0:098463de4c5d | 204 | { |
| group-onsemi | 0:098463de4c5d | 205 | /* Check the RTC peripheral state */ |
| group-onsemi | 0:098463de4c5d | 206 | if(hrtc == NULL) |
| group-onsemi | 0:098463de4c5d | 207 | { |
| group-onsemi | 0:098463de4c5d | 208 | return HAL_ERROR; |
| group-onsemi | 0:098463de4c5d | 209 | } |
| group-onsemi | 0:098463de4c5d | 210 | |
| group-onsemi | 0:098463de4c5d | 211 | /* Check the parameters */ |
| group-onsemi | 0:098463de4c5d | 212 | assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); |
| group-onsemi | 0:098463de4c5d | 213 | assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); |
| group-onsemi | 0:098463de4c5d | 214 | assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); |
| group-onsemi | 0:098463de4c5d | 215 | assert_param (IS_RTC_OUTPUT(hrtc->Init.OutPut)); |
| group-onsemi | 0:098463de4c5d | 216 | assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); |
| group-onsemi | 0:098463de4c5d | 217 | assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); |
| group-onsemi | 0:098463de4c5d | 218 | |
| group-onsemi | 0:098463de4c5d | 219 | if(hrtc->State == HAL_RTC_STATE_RESET) |
| group-onsemi | 0:098463de4c5d | 220 | { |
| group-onsemi | 0:098463de4c5d | 221 | /* Allocate lock resource and initialize it */ |
| group-onsemi | 0:098463de4c5d | 222 | hrtc->Lock = HAL_UNLOCKED; |
| group-onsemi | 0:098463de4c5d | 223 | /* Initialize RTC MSP */ |
| group-onsemi | 0:098463de4c5d | 224 | HAL_RTC_MspInit(hrtc); |
| group-onsemi | 0:098463de4c5d | 225 | } |
| group-onsemi | 0:098463de4c5d | 226 | |
| group-onsemi | 0:098463de4c5d | 227 | /* Set RTC state */ |
| group-onsemi | 0:098463de4c5d | 228 | hrtc->State = HAL_RTC_STATE_BUSY; |
| group-onsemi | 0:098463de4c5d | 229 | |
| group-onsemi | 0:098463de4c5d | 230 | /* Disable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 231 | __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 232 | |
| group-onsemi | 0:098463de4c5d | 233 | /* Set Initialization mode */ |
| group-onsemi | 0:098463de4c5d | 234 | if(RTC_EnterInitMode(hrtc) != HAL_OK) |
| group-onsemi | 0:098463de4c5d | 235 | { |
| group-onsemi | 0:098463de4c5d | 236 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 237 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 238 | |
| group-onsemi | 0:098463de4c5d | 239 | /* Set RTC state */ |
| group-onsemi | 0:098463de4c5d | 240 | hrtc->State = HAL_RTC_STATE_ERROR; |
| group-onsemi | 0:098463de4c5d | 241 | |
| group-onsemi | 0:098463de4c5d | 242 | return HAL_ERROR; |
| group-onsemi | 0:098463de4c5d | 243 | } |
| group-onsemi | 0:098463de4c5d | 244 | else |
| group-onsemi | 0:098463de4c5d | 245 | { |
| group-onsemi | 0:098463de4c5d | 246 | /* Clear RTC_CR FMT, OSEL and POL Bits */ |
| group-onsemi | 0:098463de4c5d | 247 | hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); |
| group-onsemi | 0:098463de4c5d | 248 | /* Set RTC_CR register */ |
| group-onsemi | 0:098463de4c5d | 249 | hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); |
| group-onsemi | 0:098463de4c5d | 250 | |
| group-onsemi | 0:098463de4c5d | 251 | /* Configure the RTC PRER */ |
| group-onsemi | 0:098463de4c5d | 252 | hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); |
| group-onsemi | 0:098463de4c5d | 253 | hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U); |
| group-onsemi | 0:098463de4c5d | 254 | |
| group-onsemi | 0:098463de4c5d | 255 | /* Exit Initialization mode */ |
| group-onsemi | 0:098463de4c5d | 256 | hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; |
| group-onsemi | 0:098463de4c5d | 257 | |
| group-onsemi | 0:098463de4c5d | 258 | hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE; |
| group-onsemi | 0:098463de4c5d | 259 | hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); |
| group-onsemi | 0:098463de4c5d | 260 | |
| group-onsemi | 0:098463de4c5d | 261 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 262 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 263 | |
| group-onsemi | 0:098463de4c5d | 264 | /* Set RTC state */ |
| group-onsemi | 0:098463de4c5d | 265 | hrtc->State = HAL_RTC_STATE_READY; |
| group-onsemi | 0:098463de4c5d | 266 | |
| group-onsemi | 0:098463de4c5d | 267 | return HAL_OK; |
| group-onsemi | 0:098463de4c5d | 268 | } |
| group-onsemi | 0:098463de4c5d | 269 | } |
| group-onsemi | 0:098463de4c5d | 270 | |
| group-onsemi | 0:098463de4c5d | 271 | /** |
| group-onsemi | 0:098463de4c5d | 272 | * @brief DeInitializes the RTC peripheral |
| group-onsemi | 0:098463de4c5d | 273 | * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains |
| group-onsemi | 0:098463de4c5d | 274 | * the configuration information for RTC. |
| group-onsemi | 0:098463de4c5d | 275 | * @note This function doesn't reset the RTC Backup Data registers. |
| group-onsemi | 0:098463de4c5d | 276 | * @retval HAL status |
| group-onsemi | 0:098463de4c5d | 277 | */ |
| group-onsemi | 0:098463de4c5d | 278 | HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) |
| group-onsemi | 0:098463de4c5d | 279 | { |
| group-onsemi | 0:098463de4c5d | 280 | uint32_t tickstart = 0U; |
| group-onsemi | 0:098463de4c5d | 281 | |
| group-onsemi | 0:098463de4c5d | 282 | /* Set RTC state */ |
| group-onsemi | 0:098463de4c5d | 283 | hrtc->State = HAL_RTC_STATE_BUSY; |
| group-onsemi | 0:098463de4c5d | 284 | |
| group-onsemi | 0:098463de4c5d | 285 | /* Disable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 286 | __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 287 | |
| group-onsemi | 0:098463de4c5d | 288 | /* Set Initialization mode */ |
| group-onsemi | 0:098463de4c5d | 289 | if(RTC_EnterInitMode(hrtc) != HAL_OK) |
| group-onsemi | 0:098463de4c5d | 290 | { |
| group-onsemi | 0:098463de4c5d | 291 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 292 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 293 | |
| group-onsemi | 0:098463de4c5d | 294 | /* Set RTC state */ |
| group-onsemi | 0:098463de4c5d | 295 | hrtc->State = HAL_RTC_STATE_ERROR; |
| group-onsemi | 0:098463de4c5d | 296 | |
| group-onsemi | 0:098463de4c5d | 297 | return HAL_ERROR; |
| group-onsemi | 0:098463de4c5d | 298 | } |
| group-onsemi | 0:098463de4c5d | 299 | else |
| group-onsemi | 0:098463de4c5d | 300 | { |
| group-onsemi | 0:098463de4c5d | 301 | /* Reset TR, DR and CR registers */ |
| group-onsemi | 0:098463de4c5d | 302 | hrtc->Instance->TR = (uint32_t)0x00000000U; |
| group-onsemi | 0:098463de4c5d | 303 | hrtc->Instance->DR = (uint32_t)0x00002101U; |
| group-onsemi | 0:098463de4c5d | 304 | /* Reset All CR bits except CR[2:0] */ |
| group-onsemi | 0:098463de4c5d | 305 | hrtc->Instance->CR &= (uint32_t)0x00000007U; |
| group-onsemi | 0:098463de4c5d | 306 | |
| group-onsemi | 0:098463de4c5d | 307 | /* Get tick */ |
| group-onsemi | 0:098463de4c5d | 308 | tickstart = HAL_GetTick(); |
| group-onsemi | 0:098463de4c5d | 309 | |
| group-onsemi | 0:098463de4c5d | 310 | /* Wait till WUTWF flag is set and if Time out is reached exit */ |
| group-onsemi | 0:098463de4c5d | 311 | while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET) |
| group-onsemi | 0:098463de4c5d | 312 | { |
| group-onsemi | 0:098463de4c5d | 313 | if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) |
| group-onsemi | 0:098463de4c5d | 314 | { |
| group-onsemi | 0:098463de4c5d | 315 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 316 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 317 | |
| group-onsemi | 0:098463de4c5d | 318 | /* Set RTC state */ |
| group-onsemi | 0:098463de4c5d | 319 | hrtc->State = HAL_RTC_STATE_TIMEOUT; |
| group-onsemi | 0:098463de4c5d | 320 | |
| group-onsemi | 0:098463de4c5d | 321 | return HAL_TIMEOUT; |
| group-onsemi | 0:098463de4c5d | 322 | } |
| group-onsemi | 0:098463de4c5d | 323 | } |
| group-onsemi | 0:098463de4c5d | 324 | |
| group-onsemi | 0:098463de4c5d | 325 | /* Reset all RTC CR register bits */ |
| group-onsemi | 0:098463de4c5d | 326 | hrtc->Instance->CR &= (uint32_t)0x00000000U; |
| group-onsemi | 0:098463de4c5d | 327 | hrtc->Instance->WUTR = (uint32_t)0x0000FFFFU; |
| group-onsemi | 0:098463de4c5d | 328 | hrtc->Instance->PRER = (uint32_t)0x007F00FFU; |
| group-onsemi | 0:098463de4c5d | 329 | hrtc->Instance->CALIBR = (uint32_t)0x00000000U; |
| group-onsemi | 0:098463de4c5d | 330 | hrtc->Instance->ALRMAR = (uint32_t)0x00000000U; |
| group-onsemi | 0:098463de4c5d | 331 | hrtc->Instance->ALRMBR = (uint32_t)0x00000000U; |
| group-onsemi | 0:098463de4c5d | 332 | hrtc->Instance->SHIFTR = (uint32_t)0x00000000U; |
| group-onsemi | 0:098463de4c5d | 333 | hrtc->Instance->CALR = (uint32_t)0x00000000U; |
| group-onsemi | 0:098463de4c5d | 334 | hrtc->Instance->ALRMASSR = (uint32_t)0x00000000U; |
| group-onsemi | 0:098463de4c5d | 335 | hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000U; |
| group-onsemi | 0:098463de4c5d | 336 | |
| group-onsemi | 0:098463de4c5d | 337 | /* Reset ISR register and exit initialization mode */ |
| group-onsemi | 0:098463de4c5d | 338 | hrtc->Instance->ISR = (uint32_t)0x00000000U; |
| group-onsemi | 0:098463de4c5d | 339 | |
| group-onsemi | 0:098463de4c5d | 340 | /* Reset Tamper and alternate functions configuration register */ |
| group-onsemi | 0:098463de4c5d | 341 | hrtc->Instance->TAFCR = 0x00000000U; |
| group-onsemi | 0:098463de4c5d | 342 | |
| group-onsemi | 0:098463de4c5d | 343 | /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ |
| group-onsemi | 0:098463de4c5d | 344 | if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) |
| group-onsemi | 0:098463de4c5d | 345 | { |
| group-onsemi | 0:098463de4c5d | 346 | if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) |
| group-onsemi | 0:098463de4c5d | 347 | { |
| group-onsemi | 0:098463de4c5d | 348 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 349 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 350 | |
| group-onsemi | 0:098463de4c5d | 351 | hrtc->State = HAL_RTC_STATE_ERROR; |
| group-onsemi | 0:098463de4c5d | 352 | |
| group-onsemi | 0:098463de4c5d | 353 | return HAL_ERROR; |
| group-onsemi | 0:098463de4c5d | 354 | } |
| group-onsemi | 0:098463de4c5d | 355 | } |
| group-onsemi | 0:098463de4c5d | 356 | } |
| group-onsemi | 0:098463de4c5d | 357 | |
| group-onsemi | 0:098463de4c5d | 358 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 359 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 360 | |
| group-onsemi | 0:098463de4c5d | 361 | /* De-Initialize RTC MSP */ |
| group-onsemi | 0:098463de4c5d | 362 | HAL_RTC_MspDeInit(hrtc); |
| group-onsemi | 0:098463de4c5d | 363 | |
| group-onsemi | 0:098463de4c5d | 364 | hrtc->State = HAL_RTC_STATE_RESET; |
| group-onsemi | 0:098463de4c5d | 365 | |
| group-onsemi | 0:098463de4c5d | 366 | /* Release Lock */ |
| group-onsemi | 0:098463de4c5d | 367 | __HAL_UNLOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 368 | |
| group-onsemi | 0:098463de4c5d | 369 | return HAL_OK; |
| group-onsemi | 0:098463de4c5d | 370 | } |
| group-onsemi | 0:098463de4c5d | 371 | |
| group-onsemi | 0:098463de4c5d | 372 | /** |
| group-onsemi | 0:098463de4c5d | 373 | * @brief Initializes the RTC MSP. |
| group-onsemi | 0:098463de4c5d | 374 | * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains |
| group-onsemi | 0:098463de4c5d | 375 | * the configuration information for RTC. |
| group-onsemi | 0:098463de4c5d | 376 | * @retval None |
| group-onsemi | 0:098463de4c5d | 377 | */ |
| group-onsemi | 0:098463de4c5d | 378 | __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) |
| group-onsemi | 0:098463de4c5d | 379 | { |
| group-onsemi | 0:098463de4c5d | 380 | /* Prevent unused argument(s) compilation warning */ |
| group-onsemi | 0:098463de4c5d | 381 | UNUSED(hrtc); |
| group-onsemi | 0:098463de4c5d | 382 | /* NOTE : This function Should not be modified, when the callback is needed, |
| group-onsemi | 0:098463de4c5d | 383 | the HAL_RTC_MspInit could be implemented in the user file |
| group-onsemi | 0:098463de4c5d | 384 | */ |
| group-onsemi | 0:098463de4c5d | 385 | } |
| group-onsemi | 0:098463de4c5d | 386 | |
| group-onsemi | 0:098463de4c5d | 387 | /** |
| group-onsemi | 0:098463de4c5d | 388 | * @brief DeInitializes the RTC MSP. |
| group-onsemi | 0:098463de4c5d | 389 | * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains |
| group-onsemi | 0:098463de4c5d | 390 | * the configuration information for RTC. |
| group-onsemi | 0:098463de4c5d | 391 | * @retval None |
| group-onsemi | 0:098463de4c5d | 392 | */ |
| group-onsemi | 0:098463de4c5d | 393 | __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) |
| group-onsemi | 0:098463de4c5d | 394 | { |
| group-onsemi | 0:098463de4c5d | 395 | /* Prevent unused argument(s) compilation warning */ |
| group-onsemi | 0:098463de4c5d | 396 | UNUSED(hrtc); |
| group-onsemi | 0:098463de4c5d | 397 | /* NOTE : This function Should not be modified, when the callback is needed, |
| group-onsemi | 0:098463de4c5d | 398 | the HAL_RTC_MspDeInit could be implemented in the user file |
| group-onsemi | 0:098463de4c5d | 399 | */ |
| group-onsemi | 0:098463de4c5d | 400 | } |
| group-onsemi | 0:098463de4c5d | 401 | |
| group-onsemi | 0:098463de4c5d | 402 | /** |
| group-onsemi | 0:098463de4c5d | 403 | * @} |
| group-onsemi | 0:098463de4c5d | 404 | */ |
| group-onsemi | 0:098463de4c5d | 405 | |
| group-onsemi | 0:098463de4c5d | 406 | /** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions |
| group-onsemi | 0:098463de4c5d | 407 | * @brief RTC Time and Date functions |
| group-onsemi | 0:098463de4c5d | 408 | * |
| group-onsemi | 0:098463de4c5d | 409 | @verbatim |
| group-onsemi | 0:098463de4c5d | 410 | =============================================================================== |
| group-onsemi | 0:098463de4c5d | 411 | ##### RTC Time and Date functions ##### |
| group-onsemi | 0:098463de4c5d | 412 | =============================================================================== |
| group-onsemi | 0:098463de4c5d | 413 | |
| group-onsemi | 0:098463de4c5d | 414 | [..] This section provides functions allowing to configure Time and Date features |
| group-onsemi | 0:098463de4c5d | 415 | |
| group-onsemi | 0:098463de4c5d | 416 | @endverbatim |
| group-onsemi | 0:098463de4c5d | 417 | * @{ |
| group-onsemi | 0:098463de4c5d | 418 | */ |
| group-onsemi | 0:098463de4c5d | 419 | |
| group-onsemi | 0:098463de4c5d | 420 | /** |
| group-onsemi | 0:098463de4c5d | 421 | * @brief Sets RTC current time. |
| group-onsemi | 0:098463de4c5d | 422 | * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains |
| group-onsemi | 0:098463de4c5d | 423 | * the configuration information for RTC. |
| group-onsemi | 0:098463de4c5d | 424 | * @param sTime: Pointer to Time structure |
| group-onsemi | 0:098463de4c5d | 425 | * @param Format: Specifies the format of the entered parameters. |
| group-onsemi | 0:098463de4c5d | 426 | * This parameter can be one of the following values: |
| group-onsemi | 0:098463de4c5d | 427 | * @arg RTC_FORMAT_BIN: Binary data format |
| group-onsemi | 0:098463de4c5d | 428 | * @arg RTC_FORMAT_BCD: BCD data format |
| group-onsemi | 0:098463de4c5d | 429 | * @retval HAL status |
| group-onsemi | 0:098463de4c5d | 430 | */ |
| group-onsemi | 0:098463de4c5d | 431 | HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) |
| group-onsemi | 0:098463de4c5d | 432 | { |
| group-onsemi | 0:098463de4c5d | 433 | uint32_t tmpreg = 0U; |
| group-onsemi | 0:098463de4c5d | 434 | |
| group-onsemi | 0:098463de4c5d | 435 | /* Check the parameters */ |
| group-onsemi | 0:098463de4c5d | 436 | assert_param(IS_RTC_FORMAT(Format)); |
| group-onsemi | 0:098463de4c5d | 437 | assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); |
| group-onsemi | 0:098463de4c5d | 438 | assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); |
| group-onsemi | 0:098463de4c5d | 439 | |
| group-onsemi | 0:098463de4c5d | 440 | /* Process Locked */ |
| group-onsemi | 0:098463de4c5d | 441 | __HAL_LOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 442 | |
| group-onsemi | 0:098463de4c5d | 443 | hrtc->State = HAL_RTC_STATE_BUSY; |
| group-onsemi | 0:098463de4c5d | 444 | |
| group-onsemi | 0:098463de4c5d | 445 | if(Format == RTC_FORMAT_BIN) |
| group-onsemi | 0:098463de4c5d | 446 | { |
| group-onsemi | 0:098463de4c5d | 447 | if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) |
| group-onsemi | 0:098463de4c5d | 448 | { |
| group-onsemi | 0:098463de4c5d | 449 | assert_param(IS_RTC_HOUR12(sTime->Hours)); |
| group-onsemi | 0:098463de4c5d | 450 | assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); |
| group-onsemi | 0:098463de4c5d | 451 | } |
| group-onsemi | 0:098463de4c5d | 452 | else |
| group-onsemi | 0:098463de4c5d | 453 | { |
| group-onsemi | 0:098463de4c5d | 454 | sTime->TimeFormat = 0x00U; |
| group-onsemi | 0:098463de4c5d | 455 | assert_param(IS_RTC_HOUR24(sTime->Hours)); |
| group-onsemi | 0:098463de4c5d | 456 | } |
| group-onsemi | 0:098463de4c5d | 457 | assert_param(IS_RTC_MINUTES(sTime->Minutes)); |
| group-onsemi | 0:098463de4c5d | 458 | assert_param(IS_RTC_SECONDS(sTime->Seconds)); |
| group-onsemi | 0:098463de4c5d | 459 | |
| group-onsemi | 0:098463de4c5d | 460 | tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \ |
| group-onsemi | 0:098463de4c5d | 461 | ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \ |
| group-onsemi | 0:098463de4c5d | 462 | ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ |
| group-onsemi | 0:098463de4c5d | 463 | (((uint32_t)sTime->TimeFormat) << 16U)); |
| group-onsemi | 0:098463de4c5d | 464 | } |
| group-onsemi | 0:098463de4c5d | 465 | else |
| group-onsemi | 0:098463de4c5d | 466 | { |
| group-onsemi | 0:098463de4c5d | 467 | if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) |
| group-onsemi | 0:098463de4c5d | 468 | { |
| group-onsemi | 0:098463de4c5d | 469 | tmpreg = RTC_Bcd2ToByte(sTime->Hours); |
| group-onsemi | 0:098463de4c5d | 470 | assert_param(IS_RTC_HOUR12(tmpreg)); |
| group-onsemi | 0:098463de4c5d | 471 | assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); |
| group-onsemi | 0:098463de4c5d | 472 | } |
| group-onsemi | 0:098463de4c5d | 473 | else |
| group-onsemi | 0:098463de4c5d | 474 | { |
| group-onsemi | 0:098463de4c5d | 475 | sTime->TimeFormat = 0x00U; |
| group-onsemi | 0:098463de4c5d | 476 | assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); |
| group-onsemi | 0:098463de4c5d | 477 | } |
| group-onsemi | 0:098463de4c5d | 478 | assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); |
| group-onsemi | 0:098463de4c5d | 479 | assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); |
| group-onsemi | 0:098463de4c5d | 480 | tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \ |
| group-onsemi | 0:098463de4c5d | 481 | ((uint32_t)(sTime->Minutes) << 8U) | \ |
| group-onsemi | 0:098463de4c5d | 482 | ((uint32_t)sTime->Seconds) | \ |
| group-onsemi | 0:098463de4c5d | 483 | ((uint32_t)(sTime->TimeFormat) << 16U)); |
| group-onsemi | 0:098463de4c5d | 484 | } |
| group-onsemi | 0:098463de4c5d | 485 | |
| group-onsemi | 0:098463de4c5d | 486 | /* Disable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 487 | __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 488 | |
| group-onsemi | 0:098463de4c5d | 489 | /* Set Initialization mode */ |
| group-onsemi | 0:098463de4c5d | 490 | if(RTC_EnterInitMode(hrtc) != HAL_OK) |
| group-onsemi | 0:098463de4c5d | 491 | { |
| group-onsemi | 0:098463de4c5d | 492 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 493 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 494 | |
| group-onsemi | 0:098463de4c5d | 495 | /* Set RTC state */ |
| group-onsemi | 0:098463de4c5d | 496 | hrtc->State = HAL_RTC_STATE_ERROR; |
| group-onsemi | 0:098463de4c5d | 497 | |
| group-onsemi | 0:098463de4c5d | 498 | /* Process Unlocked */ |
| group-onsemi | 0:098463de4c5d | 499 | __HAL_UNLOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 500 | |
| group-onsemi | 0:098463de4c5d | 501 | return HAL_ERROR; |
| group-onsemi | 0:098463de4c5d | 502 | } |
| group-onsemi | 0:098463de4c5d | 503 | else |
| group-onsemi | 0:098463de4c5d | 504 | { |
| group-onsemi | 0:098463de4c5d | 505 | /* Set the RTC_TR register */ |
| group-onsemi | 0:098463de4c5d | 506 | hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); |
| group-onsemi | 0:098463de4c5d | 507 | |
| group-onsemi | 0:098463de4c5d | 508 | /* Clear the bits to be configured */ |
| group-onsemi | 0:098463de4c5d | 509 | hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK; |
| group-onsemi | 0:098463de4c5d | 510 | |
| group-onsemi | 0:098463de4c5d | 511 | /* Configure the RTC_CR register */ |
| group-onsemi | 0:098463de4c5d | 512 | hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); |
| group-onsemi | 0:098463de4c5d | 513 | |
| group-onsemi | 0:098463de4c5d | 514 | /* Exit Initialization mode */ |
| group-onsemi | 0:098463de4c5d | 515 | hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; |
| group-onsemi | 0:098463de4c5d | 516 | |
| group-onsemi | 0:098463de4c5d | 517 | /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ |
| group-onsemi | 0:098463de4c5d | 518 | if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) |
| group-onsemi | 0:098463de4c5d | 519 | { |
| group-onsemi | 0:098463de4c5d | 520 | if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) |
| group-onsemi | 0:098463de4c5d | 521 | { |
| group-onsemi | 0:098463de4c5d | 522 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 523 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 524 | |
| group-onsemi | 0:098463de4c5d | 525 | hrtc->State = HAL_RTC_STATE_ERROR; |
| group-onsemi | 0:098463de4c5d | 526 | |
| group-onsemi | 0:098463de4c5d | 527 | /* Process Unlocked */ |
| group-onsemi | 0:098463de4c5d | 528 | __HAL_UNLOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 529 | |
| group-onsemi | 0:098463de4c5d | 530 | return HAL_ERROR; |
| group-onsemi | 0:098463de4c5d | 531 | } |
| group-onsemi | 0:098463de4c5d | 532 | } |
| group-onsemi | 0:098463de4c5d | 533 | |
| group-onsemi | 0:098463de4c5d | 534 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 535 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 536 | |
| group-onsemi | 0:098463de4c5d | 537 | hrtc->State = HAL_RTC_STATE_READY; |
| group-onsemi | 0:098463de4c5d | 538 | |
| group-onsemi | 0:098463de4c5d | 539 | __HAL_UNLOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 540 | |
| group-onsemi | 0:098463de4c5d | 541 | return HAL_OK; |
| group-onsemi | 0:098463de4c5d | 542 | } |
| group-onsemi | 0:098463de4c5d | 543 | } |
| group-onsemi | 0:098463de4c5d | 544 | |
| group-onsemi | 0:098463de4c5d | 545 | /** |
| group-onsemi | 0:098463de4c5d | 546 | * @brief Gets RTC current time. |
| group-onsemi | 0:098463de4c5d | 547 | * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains |
| group-onsemi | 0:098463de4c5d | 548 | * the configuration information for RTC. |
| group-onsemi | 0:098463de4c5d | 549 | * @param sTime: Pointer to Time structure |
| group-onsemi | 0:098463de4c5d | 550 | * @param Format: Specifies the format of the entered parameters. |
| group-onsemi | 0:098463de4c5d | 551 | * This parameter can be one of the following values: |
| group-onsemi | 0:098463de4c5d | 552 | * @arg RTC_FORMAT_BIN: Binary data format |
| group-onsemi | 0:098463de4c5d | 553 | * @arg RTC_FORMAT_BCD: BCD data format |
| group-onsemi | 0:098463de4c5d | 554 | * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds |
| group-onsemi | 0:098463de4c5d | 555 | * value in second fraction ratio with time unit following generic formula: |
| group-onsemi | 0:098463de4c5d | 556 | * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit |
| group-onsemi | 0:098463de4c5d | 557 | * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS |
| group-onsemi | 0:098463de4c5d | 558 | * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values |
| group-onsemi | 0:098463de4c5d | 559 | * in the higher-order calendar shadow registers to ensure consistency between the time and date values. |
| group-onsemi | 0:098463de4c5d | 560 | * Reading RTC current time locks the values in calendar shadow registers until current date is read. |
| group-onsemi | 0:098463de4c5d | 561 | * @retval HAL status |
| group-onsemi | 0:098463de4c5d | 562 | */ |
| group-onsemi | 0:098463de4c5d | 563 | HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) |
| group-onsemi | 0:098463de4c5d | 564 | { |
| group-onsemi | 0:098463de4c5d | 565 | uint32_t tmpreg = 0U; |
| group-onsemi | 0:098463de4c5d | 566 | |
| group-onsemi | 0:098463de4c5d | 567 | /* Check the parameters */ |
| group-onsemi | 0:098463de4c5d | 568 | assert_param(IS_RTC_FORMAT(Format)); |
| group-onsemi | 0:098463de4c5d | 569 | |
| group-onsemi | 0:098463de4c5d | 570 | /* Get subseconds structure field from the corresponding register */ |
| group-onsemi | 0:098463de4c5d | 571 | sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR); |
| group-onsemi | 0:098463de4c5d | 572 | |
| group-onsemi | 0:098463de4c5d | 573 | /* Get SecondFraction structure field from the corresponding register field*/ |
| group-onsemi | 0:098463de4c5d | 574 | sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S); |
| group-onsemi | 0:098463de4c5d | 575 | |
| group-onsemi | 0:098463de4c5d | 576 | /* Get the TR register */ |
| group-onsemi | 0:098463de4c5d | 577 | tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); |
| group-onsemi | 0:098463de4c5d | 578 | |
| group-onsemi | 0:098463de4c5d | 579 | /* Fill the structure fields with the read parameters */ |
| group-onsemi | 0:098463de4c5d | 580 | sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U); |
| group-onsemi | 0:098463de4c5d | 581 | sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8U); |
| group-onsemi | 0:098463de4c5d | 582 | sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); |
| group-onsemi | 0:098463de4c5d | 583 | sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U); |
| group-onsemi | 0:098463de4c5d | 584 | |
| group-onsemi | 0:098463de4c5d | 585 | /* Check the input parameters format */ |
| group-onsemi | 0:098463de4c5d | 586 | if(Format == RTC_FORMAT_BIN) |
| group-onsemi | 0:098463de4c5d | 587 | { |
| group-onsemi | 0:098463de4c5d | 588 | /* Convert the time structure parameters to Binary format */ |
| group-onsemi | 0:098463de4c5d | 589 | sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); |
| group-onsemi | 0:098463de4c5d | 590 | sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); |
| group-onsemi | 0:098463de4c5d | 591 | sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); |
| group-onsemi | 0:098463de4c5d | 592 | } |
| group-onsemi | 0:098463de4c5d | 593 | |
| group-onsemi | 0:098463de4c5d | 594 | return HAL_OK; |
| group-onsemi | 0:098463de4c5d | 595 | } |
| group-onsemi | 0:098463de4c5d | 596 | |
| group-onsemi | 0:098463de4c5d | 597 | /** |
| group-onsemi | 0:098463de4c5d | 598 | * @brief Sets RTC current date. |
| group-onsemi | 0:098463de4c5d | 599 | * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains |
| group-onsemi | 0:098463de4c5d | 600 | * the configuration information for RTC. |
| group-onsemi | 0:098463de4c5d | 601 | * @param sDate: Pointer to date structure |
| group-onsemi | 0:098463de4c5d | 602 | * @param Format: specifies the format of the entered parameters. |
| group-onsemi | 0:098463de4c5d | 603 | * This parameter can be one of the following values: |
| group-onsemi | 0:098463de4c5d | 604 | * @arg RTC_FORMAT_BIN: Binary data format |
| group-onsemi | 0:098463de4c5d | 605 | * @arg RTC_FORMAT_BCD: BCD data format |
| group-onsemi | 0:098463de4c5d | 606 | * @retval HAL status |
| group-onsemi | 0:098463de4c5d | 607 | */ |
| group-onsemi | 0:098463de4c5d | 608 | HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) |
| group-onsemi | 0:098463de4c5d | 609 | { |
| group-onsemi | 0:098463de4c5d | 610 | uint32_t datetmpreg = 0U; |
| group-onsemi | 0:098463de4c5d | 611 | |
| group-onsemi | 0:098463de4c5d | 612 | /* Check the parameters */ |
| group-onsemi | 0:098463de4c5d | 613 | assert_param(IS_RTC_FORMAT(Format)); |
| group-onsemi | 0:098463de4c5d | 614 | |
| group-onsemi | 0:098463de4c5d | 615 | /* Process Locked */ |
| group-onsemi | 0:098463de4c5d | 616 | __HAL_LOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 617 | |
| group-onsemi | 0:098463de4c5d | 618 | hrtc->State = HAL_RTC_STATE_BUSY; |
| group-onsemi | 0:098463de4c5d | 619 | |
| group-onsemi | 0:098463de4c5d | 620 | if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) |
| group-onsemi | 0:098463de4c5d | 621 | { |
| group-onsemi | 0:098463de4c5d | 622 | sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); |
| group-onsemi | 0:098463de4c5d | 623 | } |
| group-onsemi | 0:098463de4c5d | 624 | |
| group-onsemi | 0:098463de4c5d | 625 | assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); |
| group-onsemi | 0:098463de4c5d | 626 | |
| group-onsemi | 0:098463de4c5d | 627 | if(Format == RTC_FORMAT_BIN) |
| group-onsemi | 0:098463de4c5d | 628 | { |
| group-onsemi | 0:098463de4c5d | 629 | assert_param(IS_RTC_YEAR(sDate->Year)); |
| group-onsemi | 0:098463de4c5d | 630 | assert_param(IS_RTC_MONTH(sDate->Month)); |
| group-onsemi | 0:098463de4c5d | 631 | assert_param(IS_RTC_DATE(sDate->Date)); |
| group-onsemi | 0:098463de4c5d | 632 | |
| group-onsemi | 0:098463de4c5d | 633 | datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \ |
| group-onsemi | 0:098463de4c5d | 634 | ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \ |
| group-onsemi | 0:098463de4c5d | 635 | ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ |
| group-onsemi | 0:098463de4c5d | 636 | ((uint32_t)sDate->WeekDay << 13U)); |
| group-onsemi | 0:098463de4c5d | 637 | } |
| group-onsemi | 0:098463de4c5d | 638 | else |
| group-onsemi | 0:098463de4c5d | 639 | { |
| group-onsemi | 0:098463de4c5d | 640 | assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); |
| group-onsemi | 0:098463de4c5d | 641 | datetmpreg = RTC_Bcd2ToByte(sDate->Month); |
| group-onsemi | 0:098463de4c5d | 642 | assert_param(IS_RTC_MONTH(datetmpreg)); |
| group-onsemi | 0:098463de4c5d | 643 | datetmpreg = RTC_Bcd2ToByte(sDate->Date); |
| group-onsemi | 0:098463de4c5d | 644 | assert_param(IS_RTC_DATE(datetmpreg)); |
| group-onsemi | 0:098463de4c5d | 645 | |
| group-onsemi | 0:098463de4c5d | 646 | datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \ |
| group-onsemi | 0:098463de4c5d | 647 | (((uint32_t)sDate->Month) << 8U) | \ |
| group-onsemi | 0:098463de4c5d | 648 | ((uint32_t)sDate->Date) | \ |
| group-onsemi | 0:098463de4c5d | 649 | (((uint32_t)sDate->WeekDay) << 13U)); |
| group-onsemi | 0:098463de4c5d | 650 | } |
| group-onsemi | 0:098463de4c5d | 651 | |
| group-onsemi | 0:098463de4c5d | 652 | /* Disable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 653 | __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 654 | |
| group-onsemi | 0:098463de4c5d | 655 | /* Set Initialization mode */ |
| group-onsemi | 0:098463de4c5d | 656 | if(RTC_EnterInitMode(hrtc) != HAL_OK) |
| group-onsemi | 0:098463de4c5d | 657 | { |
| group-onsemi | 0:098463de4c5d | 658 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 659 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 660 | |
| group-onsemi | 0:098463de4c5d | 661 | /* Set RTC state*/ |
| group-onsemi | 0:098463de4c5d | 662 | hrtc->State = HAL_RTC_STATE_ERROR; |
| group-onsemi | 0:098463de4c5d | 663 | |
| group-onsemi | 0:098463de4c5d | 664 | /* Process Unlocked */ |
| group-onsemi | 0:098463de4c5d | 665 | __HAL_UNLOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 666 | |
| group-onsemi | 0:098463de4c5d | 667 | return HAL_ERROR; |
| group-onsemi | 0:098463de4c5d | 668 | } |
| group-onsemi | 0:098463de4c5d | 669 | else |
| group-onsemi | 0:098463de4c5d | 670 | { |
| group-onsemi | 0:098463de4c5d | 671 | /* Set the RTC_DR register */ |
| group-onsemi | 0:098463de4c5d | 672 | hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); |
| group-onsemi | 0:098463de4c5d | 673 | |
| group-onsemi | 0:098463de4c5d | 674 | /* Exit Initialization mode */ |
| group-onsemi | 0:098463de4c5d | 675 | hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; |
| group-onsemi | 0:098463de4c5d | 676 | |
| group-onsemi | 0:098463de4c5d | 677 | /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ |
| group-onsemi | 0:098463de4c5d | 678 | if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) |
| group-onsemi | 0:098463de4c5d | 679 | { |
| group-onsemi | 0:098463de4c5d | 680 | if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) |
| group-onsemi | 0:098463de4c5d | 681 | { |
| group-onsemi | 0:098463de4c5d | 682 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 683 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 684 | |
| group-onsemi | 0:098463de4c5d | 685 | hrtc->State = HAL_RTC_STATE_ERROR; |
| group-onsemi | 0:098463de4c5d | 686 | |
| group-onsemi | 0:098463de4c5d | 687 | /* Process Unlocked */ |
| group-onsemi | 0:098463de4c5d | 688 | __HAL_UNLOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 689 | |
| group-onsemi | 0:098463de4c5d | 690 | return HAL_ERROR; |
| group-onsemi | 0:098463de4c5d | 691 | } |
| group-onsemi | 0:098463de4c5d | 692 | } |
| group-onsemi | 0:098463de4c5d | 693 | |
| group-onsemi | 0:098463de4c5d | 694 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 695 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 696 | |
| group-onsemi | 0:098463de4c5d | 697 | hrtc->State = HAL_RTC_STATE_READY ; |
| group-onsemi | 0:098463de4c5d | 698 | |
| group-onsemi | 0:098463de4c5d | 699 | /* Process Unlocked */ |
| group-onsemi | 0:098463de4c5d | 700 | __HAL_UNLOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 701 | |
| group-onsemi | 0:098463de4c5d | 702 | return HAL_OK; |
| group-onsemi | 0:098463de4c5d | 703 | } |
| group-onsemi | 0:098463de4c5d | 704 | } |
| group-onsemi | 0:098463de4c5d | 705 | |
| group-onsemi | 0:098463de4c5d | 706 | /** |
| group-onsemi | 0:098463de4c5d | 707 | * @brief Gets RTC current date. |
| group-onsemi | 0:098463de4c5d | 708 | * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains |
| group-onsemi | 0:098463de4c5d | 709 | * the configuration information for RTC. |
| group-onsemi | 0:098463de4c5d | 710 | * @param sDate: Pointer to Date structure |
| group-onsemi | 0:098463de4c5d | 711 | * @param Format: Specifies the format of the entered parameters. |
| group-onsemi | 0:098463de4c5d | 712 | * This parameter can be one of the following values: |
| group-onsemi | 0:098463de4c5d | 713 | * @arg RTC_FORMAT_BIN: Binary data format |
| group-onsemi | 0:098463de4c5d | 714 | * @arg RTC_FORMAT_BCD: BCD data format |
| group-onsemi | 0:098463de4c5d | 715 | * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values |
| group-onsemi | 0:098463de4c5d | 716 | * in the higher-order calendar shadow registers to ensure consistency between the time and date values. |
| group-onsemi | 0:098463de4c5d | 717 | * Reading RTC current time locks the values in calendar shadow registers until Current date is read. |
| group-onsemi | 0:098463de4c5d | 718 | * @retval HAL status |
| group-onsemi | 0:098463de4c5d | 719 | */ |
| group-onsemi | 0:098463de4c5d | 720 | HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) |
| group-onsemi | 0:098463de4c5d | 721 | { |
| group-onsemi | 0:098463de4c5d | 722 | uint32_t datetmpreg = 0U; |
| group-onsemi | 0:098463de4c5d | 723 | |
| group-onsemi | 0:098463de4c5d | 724 | /* Check the parameters */ |
| group-onsemi | 0:098463de4c5d | 725 | assert_param(IS_RTC_FORMAT(Format)); |
| group-onsemi | 0:098463de4c5d | 726 | |
| group-onsemi | 0:098463de4c5d | 727 | /* Get the DR register */ |
| group-onsemi | 0:098463de4c5d | 728 | datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); |
| group-onsemi | 0:098463de4c5d | 729 | |
| group-onsemi | 0:098463de4c5d | 730 | /* Fill the structure fields with the read parameters */ |
| group-onsemi | 0:098463de4c5d | 731 | sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U); |
| group-onsemi | 0:098463de4c5d | 732 | sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U); |
| group-onsemi | 0:098463de4c5d | 733 | sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); |
| group-onsemi | 0:098463de4c5d | 734 | sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U); |
| group-onsemi | 0:098463de4c5d | 735 | |
| group-onsemi | 0:098463de4c5d | 736 | /* Check the input parameters format */ |
| group-onsemi | 0:098463de4c5d | 737 | if(Format == RTC_FORMAT_BIN) |
| group-onsemi | 0:098463de4c5d | 738 | { |
| group-onsemi | 0:098463de4c5d | 739 | /* Convert the date structure parameters to Binary format */ |
| group-onsemi | 0:098463de4c5d | 740 | sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); |
| group-onsemi | 0:098463de4c5d | 741 | sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); |
| group-onsemi | 0:098463de4c5d | 742 | sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); |
| group-onsemi | 0:098463de4c5d | 743 | } |
| group-onsemi | 0:098463de4c5d | 744 | return HAL_OK; |
| group-onsemi | 0:098463de4c5d | 745 | } |
| group-onsemi | 0:098463de4c5d | 746 | |
| group-onsemi | 0:098463de4c5d | 747 | /** |
| group-onsemi | 0:098463de4c5d | 748 | * @} |
| group-onsemi | 0:098463de4c5d | 749 | */ |
| group-onsemi | 0:098463de4c5d | 750 | |
| group-onsemi | 0:098463de4c5d | 751 | /** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions |
| group-onsemi | 0:098463de4c5d | 752 | * @brief RTC Alarm functions |
| group-onsemi | 0:098463de4c5d | 753 | * |
| group-onsemi | 0:098463de4c5d | 754 | @verbatim |
| group-onsemi | 0:098463de4c5d | 755 | =============================================================================== |
| group-onsemi | 0:098463de4c5d | 756 | ##### RTC Alarm functions ##### |
| group-onsemi | 0:098463de4c5d | 757 | =============================================================================== |
| group-onsemi | 0:098463de4c5d | 758 | |
| group-onsemi | 0:098463de4c5d | 759 | [..] This section provides functions allowing to configure Alarm feature |
| group-onsemi | 0:098463de4c5d | 760 | |
| group-onsemi | 0:098463de4c5d | 761 | @endverbatim |
| group-onsemi | 0:098463de4c5d | 762 | * @{ |
| group-onsemi | 0:098463de4c5d | 763 | */ |
| group-onsemi | 0:098463de4c5d | 764 | /** |
| group-onsemi | 0:098463de4c5d | 765 | * @brief Sets the specified RTC Alarm. |
| group-onsemi | 0:098463de4c5d | 766 | * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains |
| group-onsemi | 0:098463de4c5d | 767 | * the configuration information for RTC. |
| group-onsemi | 0:098463de4c5d | 768 | * @param sAlarm: Pointer to Alarm structure |
| group-onsemi | 0:098463de4c5d | 769 | * @param Format: Specifies the format of the entered parameters. |
| group-onsemi | 0:098463de4c5d | 770 | * This parameter can be one of the following values: |
| group-onsemi | 0:098463de4c5d | 771 | * @arg RTC_FORMAT_BIN: Binary data format |
| group-onsemi | 0:098463de4c5d | 772 | * @arg RTC_FORMAT_BCD: BCD data format |
| group-onsemi | 0:098463de4c5d | 773 | * @retval HAL status |
| group-onsemi | 0:098463de4c5d | 774 | */ |
| group-onsemi | 0:098463de4c5d | 775 | HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) |
| group-onsemi | 0:098463de4c5d | 776 | { |
| group-onsemi | 0:098463de4c5d | 777 | uint32_t tickstart = 0U; |
| group-onsemi | 0:098463de4c5d | 778 | uint32_t tmpreg = 0U, subsecondtmpreg = 0U; |
| group-onsemi | 0:098463de4c5d | 779 | |
| group-onsemi | 0:098463de4c5d | 780 | /* Check the parameters */ |
| group-onsemi | 0:098463de4c5d | 781 | assert_param(IS_RTC_FORMAT(Format)); |
| group-onsemi | 0:098463de4c5d | 782 | assert_param(IS_RTC_ALARM(sAlarm->Alarm)); |
| group-onsemi | 0:098463de4c5d | 783 | assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); |
| group-onsemi | 0:098463de4c5d | 784 | assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); |
| group-onsemi | 0:098463de4c5d | 785 | assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); |
| group-onsemi | 0:098463de4c5d | 786 | assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); |
| group-onsemi | 0:098463de4c5d | 787 | |
| group-onsemi | 0:098463de4c5d | 788 | /* Process Locked */ |
| group-onsemi | 0:098463de4c5d | 789 | __HAL_LOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 790 | |
| group-onsemi | 0:098463de4c5d | 791 | hrtc->State = HAL_RTC_STATE_BUSY; |
| group-onsemi | 0:098463de4c5d | 792 | |
| group-onsemi | 0:098463de4c5d | 793 | if(Format == RTC_FORMAT_BIN) |
| group-onsemi | 0:098463de4c5d | 794 | { |
| group-onsemi | 0:098463de4c5d | 795 | if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) |
| group-onsemi | 0:098463de4c5d | 796 | { |
| group-onsemi | 0:098463de4c5d | 797 | assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); |
| group-onsemi | 0:098463de4c5d | 798 | assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); |
| group-onsemi | 0:098463de4c5d | 799 | } |
| group-onsemi | 0:098463de4c5d | 800 | else |
| group-onsemi | 0:098463de4c5d | 801 | { |
| group-onsemi | 0:098463de4c5d | 802 | sAlarm->AlarmTime.TimeFormat = 0x00U; |
| group-onsemi | 0:098463de4c5d | 803 | assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); |
| group-onsemi | 0:098463de4c5d | 804 | } |
| group-onsemi | 0:098463de4c5d | 805 | assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); |
| group-onsemi | 0:098463de4c5d | 806 | assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); |
| group-onsemi | 0:098463de4c5d | 807 | |
| group-onsemi | 0:098463de4c5d | 808 | if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) |
| group-onsemi | 0:098463de4c5d | 809 | { |
| group-onsemi | 0:098463de4c5d | 810 | assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); |
| group-onsemi | 0:098463de4c5d | 811 | } |
| group-onsemi | 0:098463de4c5d | 812 | else |
| group-onsemi | 0:098463de4c5d | 813 | { |
| group-onsemi | 0:098463de4c5d | 814 | assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); |
| group-onsemi | 0:098463de4c5d | 815 | } |
| group-onsemi | 0:098463de4c5d | 816 | |
| group-onsemi | 0:098463de4c5d | 817 | tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ |
| group-onsemi | 0:098463de4c5d | 818 | ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ |
| group-onsemi | 0:098463de4c5d | 819 | ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ |
| group-onsemi | 0:098463de4c5d | 820 | ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ |
| group-onsemi | 0:098463de4c5d | 821 | ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ |
| group-onsemi | 0:098463de4c5d | 822 | ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ |
| group-onsemi | 0:098463de4c5d | 823 | ((uint32_t)sAlarm->AlarmMask)); |
| group-onsemi | 0:098463de4c5d | 824 | } |
| group-onsemi | 0:098463de4c5d | 825 | else |
| group-onsemi | 0:098463de4c5d | 826 | { |
| group-onsemi | 0:098463de4c5d | 827 | if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) |
| group-onsemi | 0:098463de4c5d | 828 | { |
| group-onsemi | 0:098463de4c5d | 829 | tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); |
| group-onsemi | 0:098463de4c5d | 830 | assert_param(IS_RTC_HOUR12(tmpreg)); |
| group-onsemi | 0:098463de4c5d | 831 | assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); |
| group-onsemi | 0:098463de4c5d | 832 | } |
| group-onsemi | 0:098463de4c5d | 833 | else |
| group-onsemi | 0:098463de4c5d | 834 | { |
| group-onsemi | 0:098463de4c5d | 835 | sAlarm->AlarmTime.TimeFormat = 0x00U; |
| group-onsemi | 0:098463de4c5d | 836 | assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); |
| group-onsemi | 0:098463de4c5d | 837 | } |
| group-onsemi | 0:098463de4c5d | 838 | |
| group-onsemi | 0:098463de4c5d | 839 | assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); |
| group-onsemi | 0:098463de4c5d | 840 | assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); |
| group-onsemi | 0:098463de4c5d | 841 | |
| group-onsemi | 0:098463de4c5d | 842 | if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) |
| group-onsemi | 0:098463de4c5d | 843 | { |
| group-onsemi | 0:098463de4c5d | 844 | tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); |
| group-onsemi | 0:098463de4c5d | 845 | assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); |
| group-onsemi | 0:098463de4c5d | 846 | } |
| group-onsemi | 0:098463de4c5d | 847 | else |
| group-onsemi | 0:098463de4c5d | 848 | { |
| group-onsemi | 0:098463de4c5d | 849 | tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); |
| group-onsemi | 0:098463de4c5d | 850 | assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); |
| group-onsemi | 0:098463de4c5d | 851 | } |
| group-onsemi | 0:098463de4c5d | 852 | |
| group-onsemi | 0:098463de4c5d | 853 | tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ |
| group-onsemi | 0:098463de4c5d | 854 | ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ |
| group-onsemi | 0:098463de4c5d | 855 | ((uint32_t) sAlarm->AlarmTime.Seconds) | \ |
| group-onsemi | 0:098463de4c5d | 856 | ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ |
| group-onsemi | 0:098463de4c5d | 857 | ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ |
| group-onsemi | 0:098463de4c5d | 858 | ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ |
| group-onsemi | 0:098463de4c5d | 859 | ((uint32_t)sAlarm->AlarmMask)); |
| group-onsemi | 0:098463de4c5d | 860 | } |
| group-onsemi | 0:098463de4c5d | 861 | |
| group-onsemi | 0:098463de4c5d | 862 | /* Configure the Alarm A or Alarm B Sub Second registers */ |
| group-onsemi | 0:098463de4c5d | 863 | subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); |
| group-onsemi | 0:098463de4c5d | 864 | |
| group-onsemi | 0:098463de4c5d | 865 | /* Disable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 866 | __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 867 | |
| group-onsemi | 0:098463de4c5d | 868 | /* Configure the Alarm register */ |
| group-onsemi | 0:098463de4c5d | 869 | if(sAlarm->Alarm == RTC_ALARM_A) |
| group-onsemi | 0:098463de4c5d | 870 | { |
| group-onsemi | 0:098463de4c5d | 871 | /* Disable the Alarm A interrupt */ |
| group-onsemi | 0:098463de4c5d | 872 | __HAL_RTC_ALARMA_DISABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 873 | |
| group-onsemi | 0:098463de4c5d | 874 | /* In case of interrupt mode is used, the interrupt source must disabled */ |
| group-onsemi | 0:098463de4c5d | 875 | __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); |
| group-onsemi | 0:098463de4c5d | 876 | |
| group-onsemi | 0:098463de4c5d | 877 | /* Get tick */ |
| group-onsemi | 0:098463de4c5d | 878 | tickstart = HAL_GetTick(); |
| group-onsemi | 0:098463de4c5d | 879 | |
| group-onsemi | 0:098463de4c5d | 880 | /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ |
| group-onsemi | 0:098463de4c5d | 881 | while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) |
| group-onsemi | 0:098463de4c5d | 882 | { |
| group-onsemi | 0:098463de4c5d | 883 | if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) |
| group-onsemi | 0:098463de4c5d | 884 | { |
| group-onsemi | 0:098463de4c5d | 885 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 886 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 887 | |
| group-onsemi | 0:098463de4c5d | 888 | hrtc->State = HAL_RTC_STATE_TIMEOUT; |
| group-onsemi | 0:098463de4c5d | 889 | |
| group-onsemi | 0:098463de4c5d | 890 | /* Process Unlocked */ |
| group-onsemi | 0:098463de4c5d | 891 | __HAL_UNLOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 892 | |
| group-onsemi | 0:098463de4c5d | 893 | return HAL_TIMEOUT; |
| group-onsemi | 0:098463de4c5d | 894 | } |
| group-onsemi | 0:098463de4c5d | 895 | } |
| group-onsemi | 0:098463de4c5d | 896 | |
| group-onsemi | 0:098463de4c5d | 897 | hrtc->Instance->ALRMAR = (uint32_t)tmpreg; |
| group-onsemi | 0:098463de4c5d | 898 | /* Configure the Alarm A Sub Second register */ |
| group-onsemi | 0:098463de4c5d | 899 | hrtc->Instance->ALRMASSR = subsecondtmpreg; |
| group-onsemi | 0:098463de4c5d | 900 | /* Configure the Alarm state: Enable Alarm */ |
| group-onsemi | 0:098463de4c5d | 901 | __HAL_RTC_ALARMA_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 902 | } |
| group-onsemi | 0:098463de4c5d | 903 | else |
| group-onsemi | 0:098463de4c5d | 904 | { |
| group-onsemi | 0:098463de4c5d | 905 | /* Disable the Alarm B interrupt */ |
| group-onsemi | 0:098463de4c5d | 906 | __HAL_RTC_ALARMB_DISABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 907 | |
| group-onsemi | 0:098463de4c5d | 908 | /* In case of interrupt mode is used, the interrupt source must disabled */ |
| group-onsemi | 0:098463de4c5d | 909 | __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); |
| group-onsemi | 0:098463de4c5d | 910 | |
| group-onsemi | 0:098463de4c5d | 911 | /* Get tick */ |
| group-onsemi | 0:098463de4c5d | 912 | tickstart = HAL_GetTick(); |
| group-onsemi | 0:098463de4c5d | 913 | |
| group-onsemi | 0:098463de4c5d | 914 | /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ |
| group-onsemi | 0:098463de4c5d | 915 | while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) |
| group-onsemi | 0:098463de4c5d | 916 | { |
| group-onsemi | 0:098463de4c5d | 917 | if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) |
| group-onsemi | 0:098463de4c5d | 918 | { |
| group-onsemi | 0:098463de4c5d | 919 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 920 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 921 | |
| group-onsemi | 0:098463de4c5d | 922 | hrtc->State = HAL_RTC_STATE_TIMEOUT; |
| group-onsemi | 0:098463de4c5d | 923 | |
| group-onsemi | 0:098463de4c5d | 924 | /* Process Unlocked */ |
| group-onsemi | 0:098463de4c5d | 925 | __HAL_UNLOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 926 | |
| group-onsemi | 0:098463de4c5d | 927 | return HAL_TIMEOUT; |
| group-onsemi | 0:098463de4c5d | 928 | } |
| group-onsemi | 0:098463de4c5d | 929 | } |
| group-onsemi | 0:098463de4c5d | 930 | |
| group-onsemi | 0:098463de4c5d | 931 | hrtc->Instance->ALRMBR = (uint32_t)tmpreg; |
| group-onsemi | 0:098463de4c5d | 932 | /* Configure the Alarm B Sub Second register */ |
| group-onsemi | 0:098463de4c5d | 933 | hrtc->Instance->ALRMBSSR = subsecondtmpreg; |
| group-onsemi | 0:098463de4c5d | 934 | /* Configure the Alarm state: Enable Alarm */ |
| group-onsemi | 0:098463de4c5d | 935 | __HAL_RTC_ALARMB_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 936 | } |
| group-onsemi | 0:098463de4c5d | 937 | |
| group-onsemi | 0:098463de4c5d | 938 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 939 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 940 | |
| group-onsemi | 0:098463de4c5d | 941 | /* Change RTC state */ |
| group-onsemi | 0:098463de4c5d | 942 | hrtc->State = HAL_RTC_STATE_READY; |
| group-onsemi | 0:098463de4c5d | 943 | |
| group-onsemi | 0:098463de4c5d | 944 | /* Process Unlocked */ |
| group-onsemi | 0:098463de4c5d | 945 | __HAL_UNLOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 946 | |
| group-onsemi | 0:098463de4c5d | 947 | return HAL_OK; |
| group-onsemi | 0:098463de4c5d | 948 | } |
| group-onsemi | 0:098463de4c5d | 949 | |
| group-onsemi | 0:098463de4c5d | 950 | /** |
| group-onsemi | 0:098463de4c5d | 951 | * @brief Sets the specified RTC Alarm with Interrupt |
| group-onsemi | 0:098463de4c5d | 952 | * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains |
| group-onsemi | 0:098463de4c5d | 953 | * the configuration information for RTC. |
| group-onsemi | 0:098463de4c5d | 954 | * @param sAlarm: Pointer to Alarm structure |
| group-onsemi | 0:098463de4c5d | 955 | * @param Format: Specifies the format of the entered parameters. |
| group-onsemi | 0:098463de4c5d | 956 | * This parameter can be one of the following values: |
| group-onsemi | 0:098463de4c5d | 957 | * @arg RTC_FORMAT_BIN: Binary data format |
| group-onsemi | 0:098463de4c5d | 958 | * @arg RTC_FORMAT_BCD: BCD data format |
| group-onsemi | 0:098463de4c5d | 959 | * @retval HAL status |
| group-onsemi | 0:098463de4c5d | 960 | */ |
| group-onsemi | 0:098463de4c5d | 961 | HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) |
| group-onsemi | 0:098463de4c5d | 962 | { |
| group-onsemi | 0:098463de4c5d | 963 | uint32_t tmpreg = 0U, subsecondtmpreg = 0U; |
| group-onsemi | 0:098463de4c5d | 964 | __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U) ; |
| group-onsemi | 0:098463de4c5d | 965 | |
| group-onsemi | 0:098463de4c5d | 966 | /* Check the parameters */ |
| group-onsemi | 0:098463de4c5d | 967 | assert_param(IS_RTC_FORMAT(Format)); |
| group-onsemi | 0:098463de4c5d | 968 | assert_param(IS_RTC_ALARM(sAlarm->Alarm)); |
| group-onsemi | 0:098463de4c5d | 969 | assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); |
| group-onsemi | 0:098463de4c5d | 970 | assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); |
| group-onsemi | 0:098463de4c5d | 971 | assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); |
| group-onsemi | 0:098463de4c5d | 972 | assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); |
| group-onsemi | 0:098463de4c5d | 973 | |
| group-onsemi | 0:098463de4c5d | 974 | /* Process Locked */ |
| group-onsemi | 0:098463de4c5d | 975 | __HAL_LOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 976 | |
| group-onsemi | 0:098463de4c5d | 977 | hrtc->State = HAL_RTC_STATE_BUSY; |
| group-onsemi | 0:098463de4c5d | 978 | |
| group-onsemi | 0:098463de4c5d | 979 | if(Format == RTC_FORMAT_BIN) |
| group-onsemi | 0:098463de4c5d | 980 | { |
| group-onsemi | 0:098463de4c5d | 981 | if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) |
| group-onsemi | 0:098463de4c5d | 982 | { |
| group-onsemi | 0:098463de4c5d | 983 | assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); |
| group-onsemi | 0:098463de4c5d | 984 | assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); |
| group-onsemi | 0:098463de4c5d | 985 | } |
| group-onsemi | 0:098463de4c5d | 986 | else |
| group-onsemi | 0:098463de4c5d | 987 | { |
| group-onsemi | 0:098463de4c5d | 988 | sAlarm->AlarmTime.TimeFormat = 0x00U; |
| group-onsemi | 0:098463de4c5d | 989 | assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); |
| group-onsemi | 0:098463de4c5d | 990 | } |
| group-onsemi | 0:098463de4c5d | 991 | assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); |
| group-onsemi | 0:098463de4c5d | 992 | assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); |
| group-onsemi | 0:098463de4c5d | 993 | |
| group-onsemi | 0:098463de4c5d | 994 | if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) |
| group-onsemi | 0:098463de4c5d | 995 | { |
| group-onsemi | 0:098463de4c5d | 996 | assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); |
| group-onsemi | 0:098463de4c5d | 997 | } |
| group-onsemi | 0:098463de4c5d | 998 | else |
| group-onsemi | 0:098463de4c5d | 999 | { |
| group-onsemi | 0:098463de4c5d | 1000 | assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); |
| group-onsemi | 0:098463de4c5d | 1001 | } |
| group-onsemi | 0:098463de4c5d | 1002 | tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ |
| group-onsemi | 0:098463de4c5d | 1003 | ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ |
| group-onsemi | 0:098463de4c5d | 1004 | ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ |
| group-onsemi | 0:098463de4c5d | 1005 | ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ |
| group-onsemi | 0:098463de4c5d | 1006 | ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ |
| group-onsemi | 0:098463de4c5d | 1007 | ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ |
| group-onsemi | 0:098463de4c5d | 1008 | ((uint32_t)sAlarm->AlarmMask)); |
| group-onsemi | 0:098463de4c5d | 1009 | } |
| group-onsemi | 0:098463de4c5d | 1010 | else |
| group-onsemi | 0:098463de4c5d | 1011 | { |
| group-onsemi | 0:098463de4c5d | 1012 | if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) |
| group-onsemi | 0:098463de4c5d | 1013 | { |
| group-onsemi | 0:098463de4c5d | 1014 | tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); |
| group-onsemi | 0:098463de4c5d | 1015 | assert_param(IS_RTC_HOUR12(tmpreg)); |
| group-onsemi | 0:098463de4c5d | 1016 | assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); |
| group-onsemi | 0:098463de4c5d | 1017 | } |
| group-onsemi | 0:098463de4c5d | 1018 | else |
| group-onsemi | 0:098463de4c5d | 1019 | { |
| group-onsemi | 0:098463de4c5d | 1020 | sAlarm->AlarmTime.TimeFormat = 0x00U; |
| group-onsemi | 0:098463de4c5d | 1021 | assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); |
| group-onsemi | 0:098463de4c5d | 1022 | } |
| group-onsemi | 0:098463de4c5d | 1023 | |
| group-onsemi | 0:098463de4c5d | 1024 | assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); |
| group-onsemi | 0:098463de4c5d | 1025 | assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); |
| group-onsemi | 0:098463de4c5d | 1026 | |
| group-onsemi | 0:098463de4c5d | 1027 | if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) |
| group-onsemi | 0:098463de4c5d | 1028 | { |
| group-onsemi | 0:098463de4c5d | 1029 | tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); |
| group-onsemi | 0:098463de4c5d | 1030 | assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); |
| group-onsemi | 0:098463de4c5d | 1031 | } |
| group-onsemi | 0:098463de4c5d | 1032 | else |
| group-onsemi | 0:098463de4c5d | 1033 | { |
| group-onsemi | 0:098463de4c5d | 1034 | tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); |
| group-onsemi | 0:098463de4c5d | 1035 | assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); |
| group-onsemi | 0:098463de4c5d | 1036 | } |
| group-onsemi | 0:098463de4c5d | 1037 | tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ |
| group-onsemi | 0:098463de4c5d | 1038 | ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ |
| group-onsemi | 0:098463de4c5d | 1039 | ((uint32_t) sAlarm->AlarmTime.Seconds) | \ |
| group-onsemi | 0:098463de4c5d | 1040 | ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ |
| group-onsemi | 0:098463de4c5d | 1041 | ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ |
| group-onsemi | 0:098463de4c5d | 1042 | ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ |
| group-onsemi | 0:098463de4c5d | 1043 | ((uint32_t)sAlarm->AlarmMask)); |
| group-onsemi | 0:098463de4c5d | 1044 | } |
| group-onsemi | 0:098463de4c5d | 1045 | /* Configure the Alarm A or Alarm B Sub Second registers */ |
| group-onsemi | 0:098463de4c5d | 1046 | subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); |
| group-onsemi | 0:098463de4c5d | 1047 | |
| group-onsemi | 0:098463de4c5d | 1048 | /* Disable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 1049 | __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 1050 | |
| group-onsemi | 0:098463de4c5d | 1051 | /* Configure the Alarm register */ |
| group-onsemi | 0:098463de4c5d | 1052 | if(sAlarm->Alarm == RTC_ALARM_A) |
| group-onsemi | 0:098463de4c5d | 1053 | { |
| group-onsemi | 0:098463de4c5d | 1054 | /* Disable the Alarm A interrupt */ |
| group-onsemi | 0:098463de4c5d | 1055 | __HAL_RTC_ALARMA_DISABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 1056 | |
| group-onsemi | 0:098463de4c5d | 1057 | /* Clear flag alarm A */ |
| group-onsemi | 0:098463de4c5d | 1058 | __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); |
| group-onsemi | 0:098463de4c5d | 1059 | |
| group-onsemi | 0:098463de4c5d | 1060 | /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ |
| group-onsemi | 0:098463de4c5d | 1061 | do |
| group-onsemi | 0:098463de4c5d | 1062 | { |
| group-onsemi | 0:098463de4c5d | 1063 | if (count-- == 0) |
| group-onsemi | 0:098463de4c5d | 1064 | { |
| group-onsemi | 0:098463de4c5d | 1065 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 1066 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 1067 | |
| group-onsemi | 0:098463de4c5d | 1068 | hrtc->State = HAL_RTC_STATE_TIMEOUT; |
| group-onsemi | 0:098463de4c5d | 1069 | |
| group-onsemi | 0:098463de4c5d | 1070 | /* Process Unlocked */ |
| group-onsemi | 0:098463de4c5d | 1071 | __HAL_UNLOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 1072 | |
| group-onsemi | 0:098463de4c5d | 1073 | return HAL_TIMEOUT; |
| group-onsemi | 0:098463de4c5d | 1074 | } |
| group-onsemi | 0:098463de4c5d | 1075 | } |
| group-onsemi | 0:098463de4c5d | 1076 | while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET); |
| group-onsemi | 0:098463de4c5d | 1077 | |
| group-onsemi | 0:098463de4c5d | 1078 | hrtc->Instance->ALRMAR = (uint32_t)tmpreg; |
| group-onsemi | 0:098463de4c5d | 1079 | /* Configure the Alarm A Sub Second register */ |
| group-onsemi | 0:098463de4c5d | 1080 | hrtc->Instance->ALRMASSR = subsecondtmpreg; |
| group-onsemi | 0:098463de4c5d | 1081 | /* Configure the Alarm state: Enable Alarm */ |
| group-onsemi | 0:098463de4c5d | 1082 | __HAL_RTC_ALARMA_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 1083 | /* Configure the Alarm interrupt */ |
| group-onsemi | 0:098463de4c5d | 1084 | __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA); |
| group-onsemi | 0:098463de4c5d | 1085 | } |
| group-onsemi | 0:098463de4c5d | 1086 | else |
| group-onsemi | 0:098463de4c5d | 1087 | { |
| group-onsemi | 0:098463de4c5d | 1088 | /* Disable the Alarm B interrupt */ |
| group-onsemi | 0:098463de4c5d | 1089 | __HAL_RTC_ALARMB_DISABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 1090 | |
| group-onsemi | 0:098463de4c5d | 1091 | /* Clear flag alarm B */ |
| group-onsemi | 0:098463de4c5d | 1092 | __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); |
| group-onsemi | 0:098463de4c5d | 1093 | |
| group-onsemi | 0:098463de4c5d | 1094 | /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ |
| group-onsemi | 0:098463de4c5d | 1095 | do |
| group-onsemi | 0:098463de4c5d | 1096 | { |
| group-onsemi | 0:098463de4c5d | 1097 | if (count-- == 0) |
| group-onsemi | 0:098463de4c5d | 1098 | { |
| group-onsemi | 0:098463de4c5d | 1099 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 1100 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 1101 | |
| group-onsemi | 0:098463de4c5d | 1102 | hrtc->State = HAL_RTC_STATE_TIMEOUT; |
| group-onsemi | 0:098463de4c5d | 1103 | |
| group-onsemi | 0:098463de4c5d | 1104 | /* Process Unlocked */ |
| group-onsemi | 0:098463de4c5d | 1105 | __HAL_UNLOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 1106 | |
| group-onsemi | 0:098463de4c5d | 1107 | return HAL_TIMEOUT; |
| group-onsemi | 0:098463de4c5d | 1108 | } |
| group-onsemi | 0:098463de4c5d | 1109 | } |
| group-onsemi | 0:098463de4c5d | 1110 | while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET); |
| group-onsemi | 0:098463de4c5d | 1111 | |
| group-onsemi | 0:098463de4c5d | 1112 | hrtc->Instance->ALRMBR = (uint32_t)tmpreg; |
| group-onsemi | 0:098463de4c5d | 1113 | /* Configure the Alarm B Sub Second register */ |
| group-onsemi | 0:098463de4c5d | 1114 | hrtc->Instance->ALRMBSSR = subsecondtmpreg; |
| group-onsemi | 0:098463de4c5d | 1115 | /* Configure the Alarm state: Enable Alarm */ |
| group-onsemi | 0:098463de4c5d | 1116 | __HAL_RTC_ALARMB_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 1117 | /* Configure the Alarm interrupt */ |
| group-onsemi | 0:098463de4c5d | 1118 | __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB); |
| group-onsemi | 0:098463de4c5d | 1119 | } |
| group-onsemi | 0:098463de4c5d | 1120 | |
| group-onsemi | 0:098463de4c5d | 1121 | /* RTC Alarm Interrupt Configuration: EXTI configuration */ |
| group-onsemi | 0:098463de4c5d | 1122 | __HAL_RTC_ALARM_EXTI_ENABLE_IT(); |
| group-onsemi | 0:098463de4c5d | 1123 | |
| group-onsemi | 0:098463de4c5d | 1124 | EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT; |
| group-onsemi | 0:098463de4c5d | 1125 | |
| group-onsemi | 0:098463de4c5d | 1126 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 1127 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 1128 | |
| group-onsemi | 0:098463de4c5d | 1129 | hrtc->State = HAL_RTC_STATE_READY; |
| group-onsemi | 0:098463de4c5d | 1130 | |
| group-onsemi | 0:098463de4c5d | 1131 | /* Process Unlocked */ |
| group-onsemi | 0:098463de4c5d | 1132 | __HAL_UNLOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 1133 | |
| group-onsemi | 0:098463de4c5d | 1134 | return HAL_OK; |
| group-onsemi | 0:098463de4c5d | 1135 | } |
| group-onsemi | 0:098463de4c5d | 1136 | |
| group-onsemi | 0:098463de4c5d | 1137 | /** |
| group-onsemi | 0:098463de4c5d | 1138 | * @brief Deactivate the specified RTC Alarm |
| group-onsemi | 0:098463de4c5d | 1139 | * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains |
| group-onsemi | 0:098463de4c5d | 1140 | * the configuration information for RTC. |
| group-onsemi | 0:098463de4c5d | 1141 | * @param Alarm: Specifies the Alarm. |
| group-onsemi | 0:098463de4c5d | 1142 | * This parameter can be one of the following values: |
| group-onsemi | 0:098463de4c5d | 1143 | * @arg RTC_ALARM_A: AlarmA |
| group-onsemi | 0:098463de4c5d | 1144 | * @arg RTC_ALARM_B: AlarmB |
| group-onsemi | 0:098463de4c5d | 1145 | * @retval HAL status |
| group-onsemi | 0:098463de4c5d | 1146 | */ |
| group-onsemi | 0:098463de4c5d | 1147 | HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) |
| group-onsemi | 0:098463de4c5d | 1148 | { |
| group-onsemi | 0:098463de4c5d | 1149 | uint32_t tickstart = 0U; |
| group-onsemi | 0:098463de4c5d | 1150 | |
| group-onsemi | 0:098463de4c5d | 1151 | /* Check the parameters */ |
| group-onsemi | 0:098463de4c5d | 1152 | assert_param(IS_RTC_ALARM(Alarm)); |
| group-onsemi | 0:098463de4c5d | 1153 | |
| group-onsemi | 0:098463de4c5d | 1154 | /* Process Locked */ |
| group-onsemi | 0:098463de4c5d | 1155 | __HAL_LOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 1156 | |
| group-onsemi | 0:098463de4c5d | 1157 | hrtc->State = HAL_RTC_STATE_BUSY; |
| group-onsemi | 0:098463de4c5d | 1158 | |
| group-onsemi | 0:098463de4c5d | 1159 | /* Disable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 1160 | __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 1161 | |
| group-onsemi | 0:098463de4c5d | 1162 | if(Alarm == RTC_ALARM_A) |
| group-onsemi | 0:098463de4c5d | 1163 | { |
| group-onsemi | 0:098463de4c5d | 1164 | /* AlarmA */ |
| group-onsemi | 0:098463de4c5d | 1165 | __HAL_RTC_ALARMA_DISABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 1166 | |
| group-onsemi | 0:098463de4c5d | 1167 | /* In case of interrupt mode is used, the interrupt source must disabled */ |
| group-onsemi | 0:098463de4c5d | 1168 | __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); |
| group-onsemi | 0:098463de4c5d | 1169 | |
| group-onsemi | 0:098463de4c5d | 1170 | /* Get tick */ |
| group-onsemi | 0:098463de4c5d | 1171 | tickstart = HAL_GetTick(); |
| group-onsemi | 0:098463de4c5d | 1172 | |
| group-onsemi | 0:098463de4c5d | 1173 | /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ |
| group-onsemi | 0:098463de4c5d | 1174 | while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) |
| group-onsemi | 0:098463de4c5d | 1175 | { |
| group-onsemi | 0:098463de4c5d | 1176 | if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) |
| group-onsemi | 0:098463de4c5d | 1177 | { |
| group-onsemi | 0:098463de4c5d | 1178 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 1179 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 1180 | |
| group-onsemi | 0:098463de4c5d | 1181 | hrtc->State = HAL_RTC_STATE_TIMEOUT; |
| group-onsemi | 0:098463de4c5d | 1182 | |
| group-onsemi | 0:098463de4c5d | 1183 | /* Process Unlocked */ |
| group-onsemi | 0:098463de4c5d | 1184 | __HAL_UNLOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 1185 | |
| group-onsemi | 0:098463de4c5d | 1186 | return HAL_TIMEOUT; |
| group-onsemi | 0:098463de4c5d | 1187 | } |
| group-onsemi | 0:098463de4c5d | 1188 | } |
| group-onsemi | 0:098463de4c5d | 1189 | } |
| group-onsemi | 0:098463de4c5d | 1190 | else |
| group-onsemi | 0:098463de4c5d | 1191 | { |
| group-onsemi | 0:098463de4c5d | 1192 | /* AlarmB */ |
| group-onsemi | 0:098463de4c5d | 1193 | __HAL_RTC_ALARMB_DISABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 1194 | |
| group-onsemi | 0:098463de4c5d | 1195 | /* In case of interrupt mode is used, the interrupt source must disabled */ |
| group-onsemi | 0:098463de4c5d | 1196 | __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB); |
| group-onsemi | 0:098463de4c5d | 1197 | |
| group-onsemi | 0:098463de4c5d | 1198 | /* Get tick */ |
| group-onsemi | 0:098463de4c5d | 1199 | tickstart = HAL_GetTick(); |
| group-onsemi | 0:098463de4c5d | 1200 | |
| group-onsemi | 0:098463de4c5d | 1201 | /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ |
| group-onsemi | 0:098463de4c5d | 1202 | while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) |
| group-onsemi | 0:098463de4c5d | 1203 | { |
| group-onsemi | 0:098463de4c5d | 1204 | if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) |
| group-onsemi | 0:098463de4c5d | 1205 | { |
| group-onsemi | 0:098463de4c5d | 1206 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 1207 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 1208 | |
| group-onsemi | 0:098463de4c5d | 1209 | hrtc->State = HAL_RTC_STATE_TIMEOUT; |
| group-onsemi | 0:098463de4c5d | 1210 | |
| group-onsemi | 0:098463de4c5d | 1211 | /* Process Unlocked */ |
| group-onsemi | 0:098463de4c5d | 1212 | __HAL_UNLOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 1213 | |
| group-onsemi | 0:098463de4c5d | 1214 | return HAL_TIMEOUT; |
| group-onsemi | 0:098463de4c5d | 1215 | } |
| group-onsemi | 0:098463de4c5d | 1216 | } |
| group-onsemi | 0:098463de4c5d | 1217 | } |
| group-onsemi | 0:098463de4c5d | 1218 | /* Enable the write protection for RTC registers */ |
| group-onsemi | 0:098463de4c5d | 1219 | __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); |
| group-onsemi | 0:098463de4c5d | 1220 | |
| group-onsemi | 0:098463de4c5d | 1221 | hrtc->State = HAL_RTC_STATE_READY; |
| group-onsemi | 0:098463de4c5d | 1222 | |
| group-onsemi | 0:098463de4c5d | 1223 | /* Process Unlocked */ |
| group-onsemi | 0:098463de4c5d | 1224 | __HAL_UNLOCK(hrtc); |
| group-onsemi | 0:098463de4c5d | 1225 | |
| group-onsemi | 0:098463de4c5d | 1226 | return HAL_OK; |
| group-onsemi | 0:098463de4c5d | 1227 | } |
| group-onsemi | 0:098463de4c5d | 1228 | |
| group-onsemi | 0:098463de4c5d | 1229 | /** |
| group-onsemi | 0:098463de4c5d | 1230 | * @brief Gets the RTC Alarm value and masks. |
| group-onsemi | 0:098463de4c5d | 1231 | * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains |
| group-onsemi | 0:098463de4c5d | 1232 | * the configuration information for RTC. |
| group-onsemi | 0:098463de4c5d | 1233 | * @param sAlarm: Pointer to Date structure |
| group-onsemi | 0:098463de4c5d | 1234 | * @param Alarm: Specifies the Alarm. |
| group-onsemi | 0:098463de4c5d | 1235 | * This parameter can be one of the following values: |
| group-onsemi | 0:098463de4c5d | 1236 | * @arg RTC_ALARM_A: AlarmA |
| group-onsemi | 0:098463de4c5d | 1237 | * @arg RTC_ALARM_B: AlarmB |
| group-onsemi | 0:098463de4c5d | 1238 | * @param Format: Specifies the format of the entered parameters. |
| group-onsemi | 0:098463de4c5d | 1239 | * This parameter can be one of the following values: |
| group-onsemi | 0:098463de4c5d | 1240 | * @arg RTC_FORMAT_BIN: Binary data format |
| group-onsemi | 0:098463de4c5d | 1241 | * @arg RTC_FORMAT_BCD: BCD data format |
| group-onsemi | 0:098463de4c5d | 1242 | * @retval HAL status |
| group-onsemi | 0:098463de4c5d | 1243 | */ |
| group-onsemi | 0:098463de4c5d | 1244 | HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) |
| group-onsemi | 0:098463de4c5d | 1245 | { |
| group-onsemi | 0:098463de4c5d | 1246 | uint32_t tmpreg = 0U, subsecondtmpreg = 0U; |
| group-onsemi | 0:098463de4c5d | 1247 | |
| group-onsemi | 0:098463de4c5d | 1248 | /* Check the parameters */ |
| group-onsemi | 0:098463de4c5d | 1249 | assert_param(IS_RTC_FORMAT(Format)); |
| group-onsemi | 0:098463de4c5d | 1250 | assert_param(IS_RTC_ALARM(Alarm)); |
| group-onsemi | 0:098463de4c5d | 1251 | |
| group-onsemi | 0:098463de4c5d | 1252 | if(Alarm == RTC_ALARM_A) |
| group-onsemi | 0:098463de4c5d | 1253 | { |
| group-onsemi | 0:098463de4c5d | 1254 | /* AlarmA */ |
| group-onsemi | 0:098463de4c5d | 1255 | sAlarm->Alarm = RTC_ALARM_A; |
| group-onsemi | 0:098463de4c5d | 1256 | |
| group-onsemi | 0:098463de4c5d | 1257 | tmpreg = (uint32_t)(hrtc->Instance->ALRMAR); |
| group-onsemi | 0:098463de4c5d | 1258 | subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS); |
| group-onsemi | 0:098463de4c5d | 1259 | } |
| group-onsemi | 0:098463de4c5d | 1260 | else |
| group-onsemi | 0:098463de4c5d | 1261 | { |
| group-onsemi | 0:098463de4c5d | 1262 | sAlarm->Alarm = RTC_ALARM_B; |
| group-onsemi | 0:098463de4c5d | 1263 | |
| group-onsemi | 0:098463de4c5d | 1264 | tmpreg = (uint32_t)(hrtc->Instance->ALRMBR); |
| group-onsemi | 0:098463de4c5d | 1265 | subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS); |
| group-onsemi | 0:098463de4c5d | 1266 | } |
| group-onsemi | 0:098463de4c5d | 1267 | |
| group-onsemi | 0:098463de4c5d | 1268 | /* Fill the structure with the read parameters */ |
| group-onsemi | 0:098463de4c5d | 1269 | sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U); |
| group-onsemi | 0:098463de4c5d | 1270 | sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U); |
| group-onsemi | 0:098463de4c5d | 1271 | sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); |
| group-onsemi | 0:098463de4c5d | 1272 | sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U); |
| group-onsemi | 0:098463de4c5d | 1273 | sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; |
| group-onsemi | 0:098463de4c5d | 1274 | sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U); |
| group-onsemi | 0:098463de4c5d | 1275 | sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); |
| group-onsemi | 0:098463de4c5d | 1276 | sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); |
| group-onsemi | 0:098463de4c5d | 1277 | |
| group-onsemi | 0:098463de4c5d | 1278 | if(Format == RTC_FORMAT_BIN) |
| group-onsemi | 0:098463de4c5d | 1279 | { |
| group-onsemi | 0:098463de4c5d | 1280 | sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); |
| group-onsemi | 0:098463de4c5d | 1281 | sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); |
| group-onsemi | 0:098463de4c5d | 1282 | sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); |
| group-onsemi | 0:098463de4c5d | 1283 | sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); |
| group-onsemi | 0:098463de4c5d | 1284 | } |
| group-onsemi | 0:098463de4c5d | 1285 | |
| group-onsemi | 0:098463de4c5d | 1286 | return HAL_OK; |
| group-onsemi | 0:098463de4c5d | 1287 | } |
| group-onsemi | 0:098463de4c5d | 1288 | |
| group-onsemi | 0:098463de4c5d | 1289 | /** |
| group-onsemi | 0:098463de4c5d | 1290 | * @brief This function handles Alarm interrupt request. |
| group-onsemi | 0:098463de4c5d | 1291 | * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains |
| group-onsemi | 0:098463de4c5d | 1292 | * the configuration information for RTC. |
| group-onsemi | 0:098463de4c5d | 1293 | * @retval None |
| group-onsemi | 0:098463de4c5d | 1294 | */ |
| group-onsemi | 0:098463de4c5d | 1295 | void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) |
| group-onsemi | 0:098463de4c5d | 1296 | { |
| group-onsemi | 0:098463de4c5d | 1297 | if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA)) |
| group-onsemi | 0:098463de4c5d | 1298 | { |
| group-onsemi | 0:098463de4c5d | 1299 | /* Get the status of the Interrupt */ |
| group-onsemi | 0:098463de4c5d | 1300 | if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET) |
| group-onsemi | 0:098463de4c5d | 1301 | { |
| group-onsemi | 0:098463de4c5d | 1302 | /* AlarmA callback */ |
| group-onsemi | 0:098463de4c5d | 1303 | HAL_RTC_AlarmAEventCallback(hrtc); |
| group-onsemi | 0:098463de4c5d | 1304 | |
| group-onsemi | 0:098463de4c5d | 1305 | /* Clear the Alarm interrupt pending bit */ |
| group-onsemi | 0:098463de4c5d | 1306 | __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF); |
| group-onsemi | 0:098463de4c5d | 1307 | } |
| group-onsemi | 0:098463de4c5d | 1308 | } |
| group-onsemi | 0:098463de4c5d | 1309 | |
| group-onsemi | 0:098463de4c5d | 1310 | if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB)) |
| group-onsemi | 0:098463de4c5d | 1311 | { |
| group-onsemi | 0:098463de4c5d | 1312 | /* Get the status of the Interrupt */ |
| group-onsemi | 0:098463de4c5d | 1313 | if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET) |
| group-onsemi | 0:098463de4c5d | 1314 | { |
| group-onsemi | 0:098463de4c5d | 1315 | /* AlarmB callback */ |
| group-onsemi | 0:098463de4c5d | 1316 | HAL_RTCEx_AlarmBEventCallback(hrtc); |
| group-onsemi | 0:098463de4c5d | 1317 | |
| group-onsemi | 0:098463de4c5d | 1318 | /* Clear the Alarm interrupt pending bit */ |
| group-onsemi | 0:098463de4c5d | 1319 | __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF); |
| group-onsemi | 0:098463de4c5d | 1320 | } |
| group-onsemi | 0:098463de4c5d | 1321 | } |
| group-onsemi | 0:098463de4c5d | 1322 | |
| group-onsemi | 0:098463de4c5d | 1323 | /* Clear the EXTI's line Flag for RTC Alarm */ |
| group-onsemi | 0:098463de4c5d | 1324 | __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); |
| group-onsemi | 0:098463de4c5d | 1325 | |
| group-onsemi | 0:098463de4c5d | 1326 | /* Change RTC state */ |
| group-onsemi | 0:098463de4c5d | 1327 | hrtc->State = HAL_RTC_STATE_READY; |
| group-onsemi | 0:098463de4c5d | 1328 | } |
| group-onsemi | 0:098463de4c5d | 1329 | |
| group-onsemi | 0:098463de4c5d | 1330 | /** |
| group-onsemi | 0:098463de4c5d | 1331 | * @brief Alarm A callback. |
| group-onsemi | 0:098463de4c5d | 1332 | * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains |
| group-onsemi | 0:098463de4c5d | 1333 | * the configuration information for RTC. |
| group-onsemi | 0:098463de4c5d | 1334 | * @retval None |
| group-onsemi | 0:098463de4c5d | 1335 | */ |
| group-onsemi | 0:098463de4c5d | 1336 | __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) |
| group-onsemi | 0:098463de4c5d | 1337 | { |
| group-onsemi | 0:098463de4c5d | 1338 | /* Prevent unused argument(s) compilation warning */ |
| group-onsemi | 0:098463de4c5d | 1339 | UNUSED(hrtc); |
| group-onsemi | 0:098463de4c5d | 1340 | /* NOTE : This function Should not be modified, when the callback is needed, |
| group-onsemi | 0:098463de4c5d | 1341 | the HAL_RTC_AlarmAEventCallback could be implemented in the user file |
| group-onsemi | 0:098463de4c5d | 1342 | */ |
| group-onsemi | 0:098463de4c5d | 1343 | } |
| group-onsemi | 0:098463de4c5d | 1344 | |
| group-onsemi | 0:098463de4c5d | 1345 | /** |
| group-onsemi | 0:098463de4c5d | 1346 | * @brief This function handles AlarmA Polling request. |
| group-onsemi | 0:098463de4c5d | 1347 | * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains |
| group-onsemi | 0:098463de4c5d | 1348 | * the configuration information for RTC. |
| group-onsemi | 0:098463de4c5d | 1349 | * @param Timeout: Timeout duration |
| group-onsemi | 0:098463de4c5d | 1350 | * @retval HAL status |
| group-onsemi | 0:098463de4c5d | 1351 | */ |
| group-onsemi | 0:098463de4c5d | 1352 | HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) |
| group-onsemi | 0:098463de4c5d | 1353 | { |
| group-onsemi | 0:098463de4c5d | 1354 | uint32_t tickstart = 0U; |
| group-onsemi | 0:098463de4c5d | 1355 | |
| group-onsemi | 0:098463de4c5d | 1356 | /* Get tick */ |
| group-onsemi | 0:098463de4c5d | 1357 | tickstart = HAL_GetTick(); |
| group-onsemi | 0:098463de4c5d | 1358 | |
| group-onsemi | 0:098463de4c5d | 1359 | while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) |
| group-onsemi | 0:098463de4c5d | 1360 | { |
| group-onsemi | 0:098463de4c5d | 1361 | if(Timeout != HAL_MAX_DELAY) |
| group-onsemi | 0:098463de4c5d | 1362 | { |
| group-onsemi | 0:098463de4c5d | 1363 | if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) |
| group-onsemi | 0:098463de4c5d | 1364 | { |
| group-onsemi | 0:098463de4c5d | 1365 | hrtc->State = HAL_RTC_STATE_TIMEOUT; |
| group-onsemi | 0:098463de4c5d | 1366 | return HAL_TIMEOUT; |
| group-onsemi | 0:098463de4c5d | 1367 | } |
| group-onsemi | 0:098463de4c5d | 1368 | } |
| group-onsemi | 0:098463de4c5d | 1369 | } |
| group-onsemi | 0:098463de4c5d | 1370 | |
| group-onsemi | 0:098463de4c5d | 1371 | /* Clear the Alarm interrupt pending bit */ |
| group-onsemi | 0:098463de4c5d | 1372 | __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); |
| group-onsemi | 0:098463de4c5d | 1373 | |
| group-onsemi | 0:098463de4c5d | 1374 | /* Change RTC state */ |
| group-onsemi | 0:098463de4c5d | 1375 | hrtc->State = HAL_RTC_STATE_READY; |
| group-onsemi | 0:098463de4c5d | 1376 | |
| group-onsemi | 0:098463de4c5d | 1377 | return HAL_OK; |
| group-onsemi | 0:098463de4c5d | 1378 | } |
| group-onsemi | 0:098463de4c5d | 1379 | |
| group-onsemi | 0:098463de4c5d | 1380 | /** |
| group-onsemi | 0:098463de4c5d | 1381 | * @} |
| group-onsemi | 0:098463de4c5d | 1382 | */ |
| group-onsemi | 0:098463de4c5d | 1383 | |
| group-onsemi | 0:098463de4c5d | 1384 | /** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions |
| group-onsemi | 0:098463de4c5d | 1385 | * @brief Peripheral Control functions |
| group-onsemi | 0:098463de4c5d | 1386 | * |
| group-onsemi | 0:098463de4c5d | 1387 | @verbatim |
| group-onsemi | 0:098463de4c5d | 1388 | =============================================================================== |
| group-onsemi | 0:098463de4c5d | 1389 | ##### Peripheral Control functions ##### |
| group-onsemi | 0:098463de4c5d | 1390 | =============================================================================== |
| group-onsemi | 0:098463de4c5d | 1391 | [..] |
| group-onsemi | 0:098463de4c5d | 1392 | This subsection provides functions allowing to |
| group-onsemi | 0:098463de4c5d | 1393 | (+) Wait for RTC Time and Date Synchronization |
| group-onsemi | 0:098463de4c5d | 1394 | |
| group-onsemi | 0:098463de4c5d | 1395 | @endverbatim |
| group-onsemi | 0:098463de4c5d | 1396 | * @{ |
| group-onsemi | 0:098463de4c5d | 1397 | */ |
| group-onsemi | 0:098463de4c5d | 1398 | |
| group-onsemi | 0:098463de4c5d | 1399 | /** |
| group-onsemi | 0:098463de4c5d | 1400 | * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are |
| group-onsemi | 0:098463de4c5d | 1401 | * synchronized with RTC APB clock. |
| group-onsemi | 0:098463de4c5d | 1402 | * @note The RTC Resynchronization mode is write protected, use the |
| group-onsemi | 0:098463de4c5d | 1403 | * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. |
| group-onsemi | 0:098463de4c5d | 1404 | * @note To read the calendar through the shadow registers after Calendar |
| group-onsemi | 0:098463de4c5d | 1405 | * initialization, calendar update or after wake-up from low power modes |
| group-onsemi | 0:098463de4c5d | 1406 | * the software must first clear the RSF flag. |
| group-onsemi | 0:098463de4c5d | 1407 | * The software must then wait until it is set again before reading |
| group-onsemi | 0:098463de4c5d | 1408 | * the calendar, which means that the calendar registers have been |
| group-onsemi | 0:098463de4c5d | 1409 | * correctly copied into the RTC_TR and RTC_DR shadow registers. |
| group-onsemi | 0:098463de4c5d | 1410 | * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains |
| group-onsemi | 0:098463de4c5d | 1411 | * the configuration information for RTC. |
| group-onsemi | 0:098463de4c5d | 1412 | * @retval HAL status |
| group-onsemi | 0:098463de4c5d | 1413 | */ |
| group-onsemi | 0:098463de4c5d | 1414 | HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) |
| group-onsemi | 0:098463de4c5d | 1415 | { |
| group-onsemi | 0:098463de4c5d | 1416 | uint32_t tickstart = 0U; |
| group-onsemi | 0:098463de4c5d | 1417 | |
| group-onsemi | 0:098463de4c5d | 1418 | /* Clear RSF flag */ |
| group-onsemi | 0:098463de4c5d | 1419 | hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; |
| group-onsemi | 0:098463de4c5d | 1420 | |
| group-onsemi | 0:098463de4c5d | 1421 | /* Get tick */ |
| group-onsemi | 0:098463de4c5d | 1422 | tickstart = HAL_GetTick(); |
| group-onsemi | 0:098463de4c5d | 1423 | |
| group-onsemi | 0:098463de4c5d | 1424 | /* Wait the registers to be synchronised */ |
| group-onsemi | 0:098463de4c5d | 1425 | while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) |
| group-onsemi | 0:098463de4c5d | 1426 | { |
| group-onsemi | 0:098463de4c5d | 1427 | if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) |
| group-onsemi | 0:098463de4c5d | 1428 | { |
| group-onsemi | 0:098463de4c5d | 1429 | return HAL_TIMEOUT; |
| group-onsemi | 0:098463de4c5d | 1430 | } |
| group-onsemi | 0:098463de4c5d | 1431 | } |
| group-onsemi | 0:098463de4c5d | 1432 | |
| group-onsemi | 0:098463de4c5d | 1433 | return HAL_OK; |
| group-onsemi | 0:098463de4c5d | 1434 | } |
| group-onsemi | 0:098463de4c5d | 1435 | |
| group-onsemi | 0:098463de4c5d | 1436 | /** |
| group-onsemi | 0:098463de4c5d | 1437 | * @} |
| group-onsemi | 0:098463de4c5d | 1438 | */ |
| group-onsemi | 0:098463de4c5d | 1439 | |
| group-onsemi | 0:098463de4c5d | 1440 | /** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions |
| group-onsemi | 0:098463de4c5d | 1441 | * @brief Peripheral State functions |
| group-onsemi | 0:098463de4c5d | 1442 | * |
| group-onsemi | 0:098463de4c5d | 1443 | @verbatim |
| group-onsemi | 0:098463de4c5d | 1444 | =============================================================================== |
| group-onsemi | 0:098463de4c5d | 1445 | ##### Peripheral State functions ##### |
| group-onsemi | 0:098463de4c5d | 1446 | =============================================================================== |
| group-onsemi | 0:098463de4c5d | 1447 | [..] |
| group-onsemi | 0:098463de4c5d | 1448 | This subsection provides functions allowing to |
| group-onsemi | 0:098463de4c5d | 1449 | (+) Get RTC state |
| group-onsemi | 0:098463de4c5d | 1450 | |
| group-onsemi | 0:098463de4c5d | 1451 | @endverbatim |
| group-onsemi | 0:098463de4c5d | 1452 | * @{ |
| group-onsemi | 0:098463de4c5d | 1453 | */ |
| group-onsemi | 0:098463de4c5d | 1454 | /** |
| group-onsemi | 0:098463de4c5d | 1455 | * @brief Returns the RTC state. |
| group-onsemi | 0:098463de4c5d | 1456 | * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains |
| group-onsemi | 0:098463de4c5d | 1457 | * the configuration information for RTC. |
| group-onsemi | 0:098463de4c5d | 1458 | * @retval HAL state |
| group-onsemi | 0:098463de4c5d | 1459 | */ |
| group-onsemi | 0:098463de4c5d | 1460 | HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) |
| group-onsemi | 0:098463de4c5d | 1461 | { |
| group-onsemi | 0:098463de4c5d | 1462 | return hrtc->State; |
| group-onsemi | 0:098463de4c5d | 1463 | } |
| group-onsemi | 0:098463de4c5d | 1464 | |
| group-onsemi | 0:098463de4c5d | 1465 | /** |
| group-onsemi | 0:098463de4c5d | 1466 | * @} |
| group-onsemi | 0:098463de4c5d | 1467 | */ |
| group-onsemi | 0:098463de4c5d | 1468 | |
| group-onsemi | 0:098463de4c5d | 1469 | /** |
| group-onsemi | 0:098463de4c5d | 1470 | * @brief Enters the RTC Initialization mode. |
| group-onsemi | 0:098463de4c5d | 1471 | * @note The RTC Initialization mode is write protected, use the |
| group-onsemi | 0:098463de4c5d | 1472 | * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. |
| group-onsemi | 0:098463de4c5d | 1473 | * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains |
| group-onsemi | 0:098463de4c5d | 1474 | * the configuration information for RTC. |
| group-onsemi | 0:098463de4c5d | 1475 | * @retval HAL status |
| group-onsemi | 0:098463de4c5d | 1476 | */ |
| group-onsemi | 0:098463de4c5d | 1477 | HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) |
| group-onsemi | 0:098463de4c5d | 1478 | { |
| group-onsemi | 0:098463de4c5d | 1479 | uint32_t tickstart = 0U; |
| group-onsemi | 0:098463de4c5d | 1480 | |
| group-onsemi | 0:098463de4c5d | 1481 | /* Check if the Initialization mode is set */ |
| group-onsemi | 0:098463de4c5d | 1482 | if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) |
| group-onsemi | 0:098463de4c5d | 1483 | { |
| group-onsemi | 0:098463de4c5d | 1484 | /* Set the Initialization mode */ |
| group-onsemi | 0:098463de4c5d | 1485 | hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; |
| group-onsemi | 0:098463de4c5d | 1486 | |
| group-onsemi | 0:098463de4c5d | 1487 | /* Get tick */ |
| group-onsemi | 0:098463de4c5d | 1488 | tickstart = HAL_GetTick(); |
| group-onsemi | 0:098463de4c5d | 1489 | |
| group-onsemi | 0:098463de4c5d | 1490 | /* Wait till RTC is in INIT state and if Time out is reached exit */ |
| group-onsemi | 0:098463de4c5d | 1491 | while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) |
| group-onsemi | 0:098463de4c5d | 1492 | { |
| group-onsemi | 0:098463de4c5d | 1493 | if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) |
| group-onsemi | 0:098463de4c5d | 1494 | { |
| group-onsemi | 0:098463de4c5d | 1495 | return HAL_TIMEOUT; |
| group-onsemi | 0:098463de4c5d | 1496 | } |
| group-onsemi | 0:098463de4c5d | 1497 | } |
| group-onsemi | 0:098463de4c5d | 1498 | } |
| group-onsemi | 0:098463de4c5d | 1499 | |
| group-onsemi | 0:098463de4c5d | 1500 | return HAL_OK; |
| group-onsemi | 0:098463de4c5d | 1501 | } |
| group-onsemi | 0:098463de4c5d | 1502 | |
| group-onsemi | 0:098463de4c5d | 1503 | |
| group-onsemi | 0:098463de4c5d | 1504 | /** |
| group-onsemi | 0:098463de4c5d | 1505 | * @brief Converts a 2 digit decimal to BCD format. |
| group-onsemi | 0:098463de4c5d | 1506 | * @param Value: Byte to be converted |
| group-onsemi | 0:098463de4c5d | 1507 | * @retval Converted byte |
| group-onsemi | 0:098463de4c5d | 1508 | */ |
| group-onsemi | 0:098463de4c5d | 1509 | uint8_t RTC_ByteToBcd2(uint8_t Value) |
| group-onsemi | 0:098463de4c5d | 1510 | { |
| group-onsemi | 0:098463de4c5d | 1511 | uint32_t bcdhigh = 0U; |
| group-onsemi | 0:098463de4c5d | 1512 | |
| group-onsemi | 0:098463de4c5d | 1513 | while(Value >= 10U) |
| group-onsemi | 0:098463de4c5d | 1514 | { |
| group-onsemi | 0:098463de4c5d | 1515 | bcdhigh++; |
| group-onsemi | 0:098463de4c5d | 1516 | Value -= 10U; |
| group-onsemi | 0:098463de4c5d | 1517 | } |
| group-onsemi | 0:098463de4c5d | 1518 | |
| group-onsemi | 0:098463de4c5d | 1519 | return ((uint8_t)(bcdhigh << 4U) | Value); |
| group-onsemi | 0:098463de4c5d | 1520 | } |
| group-onsemi | 0:098463de4c5d | 1521 | |
| group-onsemi | 0:098463de4c5d | 1522 | /** |
| group-onsemi | 0:098463de4c5d | 1523 | * @brief Converts from 2 digit BCD to Binary. |
| group-onsemi | 0:098463de4c5d | 1524 | * @param Value: BCD value to be converted |
| group-onsemi | 0:098463de4c5d | 1525 | * @retval Converted word |
| group-onsemi | 0:098463de4c5d | 1526 | */ |
| group-onsemi | 0:098463de4c5d | 1527 | uint8_t RTC_Bcd2ToByte(uint8_t Value) |
| group-onsemi | 0:098463de4c5d | 1528 | { |
| group-onsemi | 0:098463de4c5d | 1529 | uint32_t tmp = 0U; |
| group-onsemi | 0:098463de4c5d | 1530 | tmp = ((uint8_t)(Value & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U; |
| group-onsemi | 0:098463de4c5d | 1531 | return (tmp + (Value & (uint8_t)0x0FU)); |
| group-onsemi | 0:098463de4c5d | 1532 | } |
| group-onsemi | 0:098463de4c5d | 1533 | |
| group-onsemi | 0:098463de4c5d | 1534 | /** |
| group-onsemi | 0:098463de4c5d | 1535 | * @} |
| group-onsemi | 0:098463de4c5d | 1536 | */ |
| group-onsemi | 0:098463de4c5d | 1537 | |
| group-onsemi | 0:098463de4c5d | 1538 | #endif /* HAL_RTC_MODULE_ENABLED */ |
| group-onsemi | 0:098463de4c5d | 1539 | /** |
| group-onsemi | 0:098463de4c5d | 1540 | * @} |
| group-onsemi | 0:098463de4c5d | 1541 | */ |
| group-onsemi | 0:098463de4c5d | 1542 | |
| group-onsemi | 0:098463de4c5d | 1543 | /** |
| group-onsemi | 0:098463de4c5d | 1544 | * @} |
| group-onsemi | 0:098463de4c5d | 1545 | */ |
| group-onsemi | 0:098463de4c5d | 1546 | |
| group-onsemi | 0:098463de4c5d | 1547 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |