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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_spi.h@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /**
group-onsemi 0:098463de4c5d 2 ******************************************************************************
group-onsemi 0:098463de4c5d 3 * @file stm32f3xx_hal_spi.h
group-onsemi 0:098463de4c5d 4 * @author MCD Application Team
group-onsemi 0:098463de4c5d 5 * @version V1.3.0
group-onsemi 0:098463de4c5d 6 * @date 01-July-2016
group-onsemi 0:098463de4c5d 7 * @brief Header file of SPI HAL module.
group-onsemi 0:098463de4c5d 8 ******************************************************************************
group-onsemi 0:098463de4c5d 9 * @attention
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
group-onsemi 0:098463de4c5d 12 *
group-onsemi 0:098463de4c5d 13 * Redistribution and use in source and binary forms, with or without modification,
group-onsemi 0:098463de4c5d 14 * are permitted provided that the following conditions are met:
group-onsemi 0:098463de4c5d 15 * 1. Redistributions of source code must retain the above copyright notice,
group-onsemi 0:098463de4c5d 16 * this list of conditions and the following disclaimer.
group-onsemi 0:098463de4c5d 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
group-onsemi 0:098463de4c5d 18 * this list of conditions and the following disclaimer in the documentation
group-onsemi 0:098463de4c5d 19 * and/or other materials provided with the distribution.
group-onsemi 0:098463de4c5d 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
group-onsemi 0:098463de4c5d 21 * may be used to endorse or promote products derived from this software
group-onsemi 0:098463de4c5d 22 * without specific prior written permission.
group-onsemi 0:098463de4c5d 23 *
group-onsemi 0:098463de4c5d 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
group-onsemi 0:098463de4c5d 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
group-onsemi 0:098463de4c5d 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
group-onsemi 0:098463de4c5d 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
group-onsemi 0:098463de4c5d 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
group-onsemi 0:098463de4c5d 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
group-onsemi 0:098463de4c5d 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
group-onsemi 0:098463de4c5d 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
group-onsemi 0:098463de4c5d 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
group-onsemi 0:098463de4c5d 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
group-onsemi 0:098463de4c5d 34 *
group-onsemi 0:098463de4c5d 35 ******************************************************************************
group-onsemi 0:098463de4c5d 36 */
group-onsemi 0:098463de4c5d 37
group-onsemi 0:098463de4c5d 38 /* Define to prevent recursive inclusion -------------------------------------*/
group-onsemi 0:098463de4c5d 39 #ifndef __STM32F3xx_HAL_SPI_H
group-onsemi 0:098463de4c5d 40 #define __STM32F3xx_HAL_SPI_H
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 43 extern "C" {
group-onsemi 0:098463de4c5d 44 #endif
group-onsemi 0:098463de4c5d 45
group-onsemi 0:098463de4c5d 46 /* Includes ------------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 47 #include "stm32f3xx_hal_def.h"
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49 /** @addtogroup STM32F3xx_HAL_Driver
group-onsemi 0:098463de4c5d 50 * @{
group-onsemi 0:098463de4c5d 51 */
group-onsemi 0:098463de4c5d 52
group-onsemi 0:098463de4c5d 53 /** @addtogroup SPI
group-onsemi 0:098463de4c5d 54 * @{
group-onsemi 0:098463de4c5d 55 */
group-onsemi 0:098463de4c5d 56
group-onsemi 0:098463de4c5d 57 /* Exported types ------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 58 /** @defgroup SPI_Exported_Types SPI Exported Types
group-onsemi 0:098463de4c5d 59 * @{
group-onsemi 0:098463de4c5d 60 */
group-onsemi 0:098463de4c5d 61
group-onsemi 0:098463de4c5d 62 /**
group-onsemi 0:098463de4c5d 63 * @brief SPI Configuration Structure definition
group-onsemi 0:098463de4c5d 64 */
group-onsemi 0:098463de4c5d 65 typedef struct
group-onsemi 0:098463de4c5d 66 {
group-onsemi 0:098463de4c5d 67 uint32_t Mode; /*!< Specifies the SPI operating mode.
group-onsemi 0:098463de4c5d 68 This parameter can be a value of @ref SPI_Mode */
group-onsemi 0:098463de4c5d 69
group-onsemi 0:098463de4c5d 70 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
group-onsemi 0:098463de4c5d 71 This parameter can be a value of @ref SPI_Direction */
group-onsemi 0:098463de4c5d 72
group-onsemi 0:098463de4c5d 73 uint32_t DataSize; /*!< Specifies the SPI data size.
group-onsemi 0:098463de4c5d 74 This parameter can be a value of @ref SPI_Data_Size */
group-onsemi 0:098463de4c5d 75
group-onsemi 0:098463de4c5d 76 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
group-onsemi 0:098463de4c5d 77 This parameter can be a value of @ref SPI_Clock_Polarity */
group-onsemi 0:098463de4c5d 78
group-onsemi 0:098463de4c5d 79 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
group-onsemi 0:098463de4c5d 80 This parameter can be a value of @ref SPI_Clock_Phase */
group-onsemi 0:098463de4c5d 81
group-onsemi 0:098463de4c5d 82 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
group-onsemi 0:098463de4c5d 83 hardware (NSS pin) or by software using the SSI bit.
group-onsemi 0:098463de4c5d 84 This parameter can be a value of @ref SPI_Slave_Select_management */
group-onsemi 0:098463de4c5d 85
group-onsemi 0:098463de4c5d 86 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
group-onsemi 0:098463de4c5d 87 used to configure the transmit and receive SCK clock.
group-onsemi 0:098463de4c5d 88 This parameter can be a value of @ref SPI_BaudRate_Prescaler
group-onsemi 0:098463de4c5d 89 @note The communication clock is derived from the master
group-onsemi 0:098463de4c5d 90 clock. The slave clock does not need to be set. */
group-onsemi 0:098463de4c5d 91
group-onsemi 0:098463de4c5d 92 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
group-onsemi 0:098463de4c5d 93 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
group-onsemi 0:098463de4c5d 94
group-onsemi 0:098463de4c5d 95 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not .
group-onsemi 0:098463de4c5d 96 This parameter can be a value of @ref SPI_TI_mode */
group-onsemi 0:098463de4c5d 97
group-onsemi 0:098463de4c5d 98 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
group-onsemi 0:098463de4c5d 99 This parameter can be a value of @ref SPI_CRC_Calculation */
group-onsemi 0:098463de4c5d 100
group-onsemi 0:098463de4c5d 101 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
group-onsemi 0:098463de4c5d 102 This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
group-onsemi 0:098463de4c5d 103
group-onsemi 0:098463de4c5d 104 uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
group-onsemi 0:098463de4c5d 105 CRC Length is only used with Data8 and Data16, not other data size
group-onsemi 0:098463de4c5d 106 This parameter can be a value of @ref SPI_CRC_length */
group-onsemi 0:098463de4c5d 107
group-onsemi 0:098463de4c5d 108 uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
group-onsemi 0:098463de4c5d 109 This parameter can be a value of @ref SPI_NSSP_Mode
group-onsemi 0:098463de4c5d 110 This mode is activated by the NSSP bit in the SPIx_CR2 register and
group-onsemi 0:098463de4c5d 111 it takes effect only if the SPI interface is configured as Motorola SPI
group-onsemi 0:098463de4c5d 112 master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
group-onsemi 0:098463de4c5d 113 CPOL setting is ignored).. */
group-onsemi 0:098463de4c5d 114 } SPI_InitTypeDef;
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 /**
group-onsemi 0:098463de4c5d 117 * @brief HAL State structures definition
group-onsemi 0:098463de4c5d 118 */
group-onsemi 0:098463de4c5d 119 typedef enum
group-onsemi 0:098463de4c5d 120 {
group-onsemi 0:098463de4c5d 121 HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */
group-onsemi 0:098463de4c5d 122 HAL_SPI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
group-onsemi 0:098463de4c5d 123 HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
group-onsemi 0:098463de4c5d 124 HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
group-onsemi 0:098463de4c5d 125 HAL_SPI_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
group-onsemi 0:098463de4c5d 126 HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */
group-onsemi 0:098463de4c5d 127 HAL_SPI_STATE_ERROR = 0x06 /*!< SPI error state */
group-onsemi 0:098463de4c5d 128 }HAL_SPI_StateTypeDef;
group-onsemi 0:098463de4c5d 129
group-onsemi 0:098463de4c5d 130 /**
group-onsemi 0:098463de4c5d 131 * @brief SPI handle Structure definition
group-onsemi 0:098463de4c5d 132 */
group-onsemi 0:098463de4c5d 133 typedef struct __SPI_HandleTypeDef
group-onsemi 0:098463de4c5d 134 {
group-onsemi 0:098463de4c5d 135 SPI_TypeDef *Instance; /*!< SPI registers base address */
group-onsemi 0:098463de4c5d 136
group-onsemi 0:098463de4c5d 137 SPI_InitTypeDef Init; /*!< SPI communication parameters */
group-onsemi 0:098463de4c5d 138
group-onsemi 0:098463de4c5d 139 uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
group-onsemi 0:098463de4c5d 140
group-onsemi 0:098463de4c5d 141 uint16_t TxXferSize; /*!< SPI Tx Transfer size */
group-onsemi 0:098463de4c5d 142
group-onsemi 0:098463de4c5d 143 __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
group-onsemi 0:098463de4c5d 144
group-onsemi 0:098463de4c5d 145 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
group-onsemi 0:098463de4c5d 146
group-onsemi 0:098463de4c5d 147 uint16_t RxXferSize; /*!< SPI Rx Transfer size */
group-onsemi 0:098463de4c5d 148
group-onsemi 0:098463de4c5d 149 __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
group-onsemi 0:098463de4c5d 150
group-onsemi 0:098463de4c5d 151 uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
group-onsemi 0:098463de4c5d 152
group-onsemi 0:098463de4c5d 153 void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx IRQ handler */
group-onsemi 0:098463de4c5d 154
group-onsemi 0:098463de4c5d 155 void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx IRQ handler */
group-onsemi 0:098463de4c5d 156
group-onsemi 0:098463de4c5d 157 DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
group-onsemi 0:098463de4c5d 158
group-onsemi 0:098463de4c5d 159 DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
group-onsemi 0:098463de4c5d 160
group-onsemi 0:098463de4c5d 161 HAL_LockTypeDef Lock; /*!< Locking object */
group-onsemi 0:098463de4c5d 162
group-onsemi 0:098463de4c5d 163 __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
group-onsemi 0:098463de4c5d 164
group-onsemi 0:098463de4c5d 165 __IO uint32_t ErrorCode; /*!< SPI Error code */
group-onsemi 0:098463de4c5d 166
group-onsemi 0:098463de4c5d 167 }SPI_HandleTypeDef;
group-onsemi 0:098463de4c5d 168
group-onsemi 0:098463de4c5d 169 /**
group-onsemi 0:098463de4c5d 170 * @}
group-onsemi 0:098463de4c5d 171 */
group-onsemi 0:098463de4c5d 172
group-onsemi 0:098463de4c5d 173 /* Exported constants --------------------------------------------------------*/
group-onsemi 0:098463de4c5d 174
group-onsemi 0:098463de4c5d 175 /** @defgroup SPI_Exported_Constants SPI Exported Constants
group-onsemi 0:098463de4c5d 176 * @{
group-onsemi 0:098463de4c5d 177 */
group-onsemi 0:098463de4c5d 178
group-onsemi 0:098463de4c5d 179 /** @defgroup SPI_Error_Code SPI Error Code
group-onsemi 0:098463de4c5d 180 * @{
group-onsemi 0:098463de4c5d 181 */
group-onsemi 0:098463de4c5d 182 #define HAL_SPI_ERROR_NONE (uint32_t)0x00000000 /*!< No error */
group-onsemi 0:098463de4c5d 183 #define HAL_SPI_ERROR_MODF (uint32_t)0x00000001 /*!< MODF error */
group-onsemi 0:098463de4c5d 184 #define HAL_SPI_ERROR_CRC (uint32_t)0x00000002 /*!< CRC error */
group-onsemi 0:098463de4c5d 185 #define HAL_SPI_ERROR_OVR (uint32_t)0x00000004 /*!< OVR error */
group-onsemi 0:098463de4c5d 186 #define HAL_SPI_ERROR_FRE (uint32_t)0x00000008 /*!< FRE error */
group-onsemi 0:098463de4c5d 187 #define HAL_SPI_ERROR_DMA (uint32_t)0x00000010 /*!< DMA transfer error */
group-onsemi 0:098463de4c5d 188 #define HAL_SPI_ERROR_FLAG (uint32_t)0x00000020 /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
group-onsemi 0:098463de4c5d 189 #define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040 /*!< Unknown error */
group-onsemi 0:098463de4c5d 190 /**
group-onsemi 0:098463de4c5d 191 * @}
group-onsemi 0:098463de4c5d 192 */
group-onsemi 0:098463de4c5d 193
group-onsemi 0:098463de4c5d 194
group-onsemi 0:098463de4c5d 195 /** @defgroup SPI_Mode SPI Mode
group-onsemi 0:098463de4c5d 196 * @{
group-onsemi 0:098463de4c5d 197 */
group-onsemi 0:098463de4c5d 198 #define SPI_MODE_SLAVE ((uint32_t)0x00000000)
group-onsemi 0:098463de4c5d 199 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
group-onsemi 0:098463de4c5d 200 /**
group-onsemi 0:098463de4c5d 201 * @}
group-onsemi 0:098463de4c5d 202 */
group-onsemi 0:098463de4c5d 203
group-onsemi 0:098463de4c5d 204 /** @defgroup SPI_Direction SPI Direction Mode
group-onsemi 0:098463de4c5d 205 * @{
group-onsemi 0:098463de4c5d 206 */
group-onsemi 0:098463de4c5d 207 #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
group-onsemi 0:098463de4c5d 208 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
group-onsemi 0:098463de4c5d 209 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
group-onsemi 0:098463de4c5d 210 /**
group-onsemi 0:098463de4c5d 211 * @}
group-onsemi 0:098463de4c5d 212 */
group-onsemi 0:098463de4c5d 213
group-onsemi 0:098463de4c5d 214 /** @defgroup SPI_Data_Size SPI Data Size
group-onsemi 0:098463de4c5d 215 * @{
group-onsemi 0:098463de4c5d 216 */
group-onsemi 0:098463de4c5d 217 #define SPI_DATASIZE_4BIT ((uint32_t)0x0300)
group-onsemi 0:098463de4c5d 218 #define SPI_DATASIZE_5BIT ((uint32_t)0x0400)
group-onsemi 0:098463de4c5d 219 #define SPI_DATASIZE_6BIT ((uint32_t)0x0500)
group-onsemi 0:098463de4c5d 220 #define SPI_DATASIZE_7BIT ((uint32_t)0x0600)
group-onsemi 0:098463de4c5d 221 #define SPI_DATASIZE_8BIT ((uint32_t)0x0700)
group-onsemi 0:098463de4c5d 222 #define SPI_DATASIZE_9BIT ((uint32_t)0x0800)
group-onsemi 0:098463de4c5d 223 #define SPI_DATASIZE_10BIT ((uint32_t)0x0900)
group-onsemi 0:098463de4c5d 224 #define SPI_DATASIZE_11BIT ((uint32_t)0x0A00)
group-onsemi 0:098463de4c5d 225 #define SPI_DATASIZE_12BIT ((uint32_t)0x0B00)
group-onsemi 0:098463de4c5d 226 #define SPI_DATASIZE_13BIT ((uint32_t)0x0C00)
group-onsemi 0:098463de4c5d 227 #define SPI_DATASIZE_14BIT ((uint32_t)0x0D00)
group-onsemi 0:098463de4c5d 228 #define SPI_DATASIZE_15BIT ((uint32_t)0x0E00)
group-onsemi 0:098463de4c5d 229 #define SPI_DATASIZE_16BIT ((uint32_t)0x0F00)
group-onsemi 0:098463de4c5d 230 /**
group-onsemi 0:098463de4c5d 231 * @}
group-onsemi 0:098463de4c5d 232 */
group-onsemi 0:098463de4c5d 233
group-onsemi 0:098463de4c5d 234 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
group-onsemi 0:098463de4c5d 235 * @{
group-onsemi 0:098463de4c5d 236 */
group-onsemi 0:098463de4c5d 237 #define SPI_POLARITY_LOW ((uint32_t)0x00000000)
group-onsemi 0:098463de4c5d 238 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
group-onsemi 0:098463de4c5d 239 /**
group-onsemi 0:098463de4c5d 240 * @}
group-onsemi 0:098463de4c5d 241 */
group-onsemi 0:098463de4c5d 242
group-onsemi 0:098463de4c5d 243 /** @defgroup SPI_Clock_Phase SPI Clock Phase
group-onsemi 0:098463de4c5d 244 * @{
group-onsemi 0:098463de4c5d 245 */
group-onsemi 0:098463de4c5d 246 #define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
group-onsemi 0:098463de4c5d 247 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
group-onsemi 0:098463de4c5d 248 /**
group-onsemi 0:098463de4c5d 249 * @}
group-onsemi 0:098463de4c5d 250 */
group-onsemi 0:098463de4c5d 251
group-onsemi 0:098463de4c5d 252 /** @defgroup SPI_Slave_Select_management SPI Slave Select management
group-onsemi 0:098463de4c5d 253 * @{
group-onsemi 0:098463de4c5d 254 */
group-onsemi 0:098463de4c5d 255 #define SPI_NSS_SOFT SPI_CR1_SSM
group-onsemi 0:098463de4c5d 256 #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
group-onsemi 0:098463de4c5d 257 #define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
group-onsemi 0:098463de4c5d 258 /**
group-onsemi 0:098463de4c5d 259 * @}
group-onsemi 0:098463de4c5d 260 */
group-onsemi 0:098463de4c5d 261
group-onsemi 0:098463de4c5d 262 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
group-onsemi 0:098463de4c5d 263 * @{
group-onsemi 0:098463de4c5d 264 */
group-onsemi 0:098463de4c5d 265 #define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
group-onsemi 0:098463de4c5d 266 #define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000)
group-onsemi 0:098463de4c5d 267 /**
group-onsemi 0:098463de4c5d 268 * @}
group-onsemi 0:098463de4c5d 269 */
group-onsemi 0:098463de4c5d 270
group-onsemi 0:098463de4c5d 271 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
group-onsemi 0:098463de4c5d 272 * @{
group-onsemi 0:098463de4c5d 273 */
group-onsemi 0:098463de4c5d 274 #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
group-onsemi 0:098463de4c5d 275 #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
group-onsemi 0:098463de4c5d 276 #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
group-onsemi 0:098463de4c5d 277 #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
group-onsemi 0:098463de4c5d 278 #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
group-onsemi 0:098463de4c5d 279 #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
group-onsemi 0:098463de4c5d 280 #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
group-onsemi 0:098463de4c5d 281 #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
group-onsemi 0:098463de4c5d 282 /**
group-onsemi 0:098463de4c5d 283 * @}
group-onsemi 0:098463de4c5d 284 */
group-onsemi 0:098463de4c5d 285
group-onsemi 0:098463de4c5d 286 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
group-onsemi 0:098463de4c5d 287 * @{
group-onsemi 0:098463de4c5d 288 */
group-onsemi 0:098463de4c5d 289 #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
group-onsemi 0:098463de4c5d 290 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
group-onsemi 0:098463de4c5d 291 /**
group-onsemi 0:098463de4c5d 292 * @}
group-onsemi 0:098463de4c5d 293 */
group-onsemi 0:098463de4c5d 294
group-onsemi 0:098463de4c5d 295 /** @defgroup SPI_TI_mode SPI TI mode
group-onsemi 0:098463de4c5d 296 * @{
group-onsemi 0:098463de4c5d 297 */
group-onsemi 0:098463de4c5d 298 #define SPI_TIMODE_DISABLE ((uint32_t)0x00000000)
group-onsemi 0:098463de4c5d 299 #define SPI_TIMODE_ENABLE SPI_CR2_FRF
group-onsemi 0:098463de4c5d 300 /**
group-onsemi 0:098463de4c5d 301 * @}
group-onsemi 0:098463de4c5d 302 */
group-onsemi 0:098463de4c5d 303
group-onsemi 0:098463de4c5d 304 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
group-onsemi 0:098463de4c5d 305 * @{
group-onsemi 0:098463de4c5d 306 */
group-onsemi 0:098463de4c5d 307 #define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
group-onsemi 0:098463de4c5d 308 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
group-onsemi 0:098463de4c5d 309 /**
group-onsemi 0:098463de4c5d 310 * @}
group-onsemi 0:098463de4c5d 311 */
group-onsemi 0:098463de4c5d 312
group-onsemi 0:098463de4c5d 313 /** @defgroup SPI_CRC_length SPI CRC Length
group-onsemi 0:098463de4c5d 314 * @{
group-onsemi 0:098463de4c5d 315 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 316 * SPI_CRC_LENGTH_DATASIZE: aligned with the data size
group-onsemi 0:098463de4c5d 317 * SPI_CRC_LENGTH_8BIT : CRC 8bit
group-onsemi 0:098463de4c5d 318 * SPI_CRC_LENGTH_16BIT : CRC 16bit
group-onsemi 0:098463de4c5d 319 */
group-onsemi 0:098463de4c5d 320 #define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000)
group-onsemi 0:098463de4c5d 321 #define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001)
group-onsemi 0:098463de4c5d 322 #define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002)
group-onsemi 0:098463de4c5d 323 /**
group-onsemi 0:098463de4c5d 324 * @}
group-onsemi 0:098463de4c5d 325 */
group-onsemi 0:098463de4c5d 326
group-onsemi 0:098463de4c5d 327 /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
group-onsemi 0:098463de4c5d 328 * @{
group-onsemi 0:098463de4c5d 329 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 330 * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
group-onsemi 0:098463de4c5d 331 * RXNE event is generated if the FIFO
group-onsemi 0:098463de4c5d 332 * level is greater or equal to 1/2(16-bits).
group-onsemi 0:098463de4c5d 333 * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
group-onsemi 0:098463de4c5d 334 * level is greater or equal to 1/4(8 bits). */
group-onsemi 0:098463de4c5d 335 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
group-onsemi 0:098463de4c5d 336 #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
group-onsemi 0:098463de4c5d 337 #define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000)
group-onsemi 0:098463de4c5d 338
group-onsemi 0:098463de4c5d 339 /**
group-onsemi 0:098463de4c5d 340 * @}
group-onsemi 0:098463de4c5d 341 */
group-onsemi 0:098463de4c5d 342
group-onsemi 0:098463de4c5d 343 /** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
group-onsemi 0:098463de4c5d 344 * @brief SPI Interrupt definition
group-onsemi 0:098463de4c5d 345 * Elements values convention: 0xXXXXXXXX
group-onsemi 0:098463de4c5d 346 * - XXXXXXXX : Interrupt control mask
group-onsemi 0:098463de4c5d 347 * @{
group-onsemi 0:098463de4c5d 348 */
group-onsemi 0:098463de4c5d 349 #define SPI_IT_TXE SPI_CR2_TXEIE
group-onsemi 0:098463de4c5d 350 #define SPI_IT_RXNE SPI_CR2_RXNEIE
group-onsemi 0:098463de4c5d 351 #define SPI_IT_ERR SPI_CR2_ERRIE
group-onsemi 0:098463de4c5d 352 /**
group-onsemi 0:098463de4c5d 353 * @}
group-onsemi 0:098463de4c5d 354 */
group-onsemi 0:098463de4c5d 355
group-onsemi 0:098463de4c5d 356
group-onsemi 0:098463de4c5d 357 /** @defgroup SPI_Flag_definition SPI Flag definition
group-onsemi 0:098463de4c5d 358 * @brief Flag definition
group-onsemi 0:098463de4c5d 359 * Elements values convention: 0xXXXXYYYY
group-onsemi 0:098463de4c5d 360 * - XXXX : Flag register Index
group-onsemi 0:098463de4c5d 361 * - YYYY : Flag mask
group-onsemi 0:098463de4c5d 362 * @{
group-onsemi 0:098463de4c5d 363 */
group-onsemi 0:098463de4c5d 364 #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
group-onsemi 0:098463de4c5d 365 #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
group-onsemi 0:098463de4c5d 366 #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
group-onsemi 0:098463de4c5d 367 #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
group-onsemi 0:098463de4c5d 368 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
group-onsemi 0:098463de4c5d 369 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
group-onsemi 0:098463de4c5d 370 #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
group-onsemi 0:098463de4c5d 371 #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
group-onsemi 0:098463de4c5d 372 #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
group-onsemi 0:098463de4c5d 373 /**
group-onsemi 0:098463de4c5d 374 * @}
group-onsemi 0:098463de4c5d 375 */
group-onsemi 0:098463de4c5d 376
group-onsemi 0:098463de4c5d 377 /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
group-onsemi 0:098463de4c5d 378 * @{
group-onsemi 0:098463de4c5d 379 */
group-onsemi 0:098463de4c5d 380 #define SPI_FTLVL_EMPTY ((uint32_t)0x0000)
group-onsemi 0:098463de4c5d 381 #define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800)
group-onsemi 0:098463de4c5d 382 #define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000)
group-onsemi 0:098463de4c5d 383 #define SPI_FTLVL_FULL ((uint32_t)0x1800)
group-onsemi 0:098463de4c5d 384
group-onsemi 0:098463de4c5d 385 /**
group-onsemi 0:098463de4c5d 386 * @}
group-onsemi 0:098463de4c5d 387 */
group-onsemi 0:098463de4c5d 388
group-onsemi 0:098463de4c5d 389 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
group-onsemi 0:098463de4c5d 390 * @{
group-onsemi 0:098463de4c5d 391 */
group-onsemi 0:098463de4c5d 392 #define SPI_FRLVL_EMPTY ((uint32_t)0x0000)
group-onsemi 0:098463de4c5d 393 #define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200)
group-onsemi 0:098463de4c5d 394 #define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400)
group-onsemi 0:098463de4c5d 395 #define SPI_FRLVL_FULL ((uint32_t)0x0600)
group-onsemi 0:098463de4c5d 396 /**
group-onsemi 0:098463de4c5d 397 * @}
group-onsemi 0:098463de4c5d 398 */
group-onsemi 0:098463de4c5d 399
group-onsemi 0:098463de4c5d 400 /**
group-onsemi 0:098463de4c5d 401 * @}
group-onsemi 0:098463de4c5d 402 */
group-onsemi 0:098463de4c5d 403
group-onsemi 0:098463de4c5d 404 /* Exported macros ------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 405 /** @defgroup SPI_Exported_Macros SPI Exported Macros
group-onsemi 0:098463de4c5d 406 * @{
group-onsemi 0:098463de4c5d 407 */
group-onsemi 0:098463de4c5d 408
group-onsemi 0:098463de4c5d 409 /** @brief Reset SPI handle state.
group-onsemi 0:098463de4c5d 410 * @param __HANDLE__: SPI handle.
group-onsemi 0:098463de4c5d 411 * @retval None
group-onsemi 0:098463de4c5d 412 */
group-onsemi 0:098463de4c5d 413 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
group-onsemi 0:098463de4c5d 414
group-onsemi 0:098463de4c5d 415 /** @brief Enable or disable the specified SPI interrupts.
group-onsemi 0:098463de4c5d 416 * @param __HANDLE__: specifies the SPI Handle.
group-onsemi 0:098463de4c5d 417 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
group-onsemi 0:098463de4c5d 418 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
group-onsemi 0:098463de4c5d 419 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 420 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
group-onsemi 0:098463de4c5d 421 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
group-onsemi 0:098463de4c5d 422 * @arg SPI_IT_ERR: Error interrupt enable
group-onsemi 0:098463de4c5d 423 * @retval None
group-onsemi 0:098463de4c5d 424 */
group-onsemi 0:098463de4c5d 425 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
group-onsemi 0:098463de4c5d 426 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
group-onsemi 0:098463de4c5d 427
group-onsemi 0:098463de4c5d 428 /** @brief Check whether the specified SPI interrupt source is enabled or not.
group-onsemi 0:098463de4c5d 429 * @param __HANDLE__: specifies the SPI Handle.
group-onsemi 0:098463de4c5d 430 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
group-onsemi 0:098463de4c5d 431 * @param __INTERRUPT__: specifies the SPI interrupt source to check.
group-onsemi 0:098463de4c5d 432 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 433 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
group-onsemi 0:098463de4c5d 434 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
group-onsemi 0:098463de4c5d 435 * @arg SPI_IT_ERR: Error interrupt enable
group-onsemi 0:098463de4c5d 436 * @retval The new state of __IT__ (TRUE or FALSE).
group-onsemi 0:098463de4c5d 437 */
group-onsemi 0:098463de4c5d 438 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
group-onsemi 0:098463de4c5d 439
group-onsemi 0:098463de4c5d 440 /** @brief Check whether the specified SPI flag is set or not.
group-onsemi 0:098463de4c5d 441 * @param __HANDLE__: specifies the SPI Handle.
group-onsemi 0:098463de4c5d 442 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
group-onsemi 0:098463de4c5d 443 * @param __FLAG__: specifies the flag to check.
group-onsemi 0:098463de4c5d 444 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 445 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
group-onsemi 0:098463de4c5d 446 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
group-onsemi 0:098463de4c5d 447 * @arg SPI_FLAG_CRCERR: CRC error flag
group-onsemi 0:098463de4c5d 448 * @arg SPI_FLAG_MODF: Mode fault flag
group-onsemi 0:098463de4c5d 449 * @arg SPI_FLAG_OVR: Overrun flag
group-onsemi 0:098463de4c5d 450 * @arg SPI_FLAG_BSY: Busy flag
group-onsemi 0:098463de4c5d 451 * @arg SPI_FLAG_FRE: Frame format error flag
group-onsemi 0:098463de4c5d 452 * @arg SPI_FLAG_FTLVL: SPI fifo transmission level
group-onsemi 0:098463de4c5d 453 * @arg SPI_FLAG_FRLVL: SPI fifo reception level
group-onsemi 0:098463de4c5d 454 * @retval The new state of __FLAG__ (TRUE or FALSE).
group-onsemi 0:098463de4c5d 455 */
group-onsemi 0:098463de4c5d 456 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
group-onsemi 0:098463de4c5d 457
group-onsemi 0:098463de4c5d 458 /** @brief Clear the SPI CRCERR pending flag.
group-onsemi 0:098463de4c5d 459 * @param __HANDLE__: specifies the SPI Handle.
group-onsemi 0:098463de4c5d 460 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
group-onsemi 0:098463de4c5d 461 * @retval None
group-onsemi 0:098463de4c5d 462 */
group-onsemi 0:098463de4c5d 463 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
group-onsemi 0:098463de4c5d 464
group-onsemi 0:098463de4c5d 465 /** @brief Clear the SPI MODF pending flag.
group-onsemi 0:098463de4c5d 466 * @param __HANDLE__: specifies the SPI Handle.
group-onsemi 0:098463de4c5d 467 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
group-onsemi 0:098463de4c5d 468 *
group-onsemi 0:098463de4c5d 469 * @retval None
group-onsemi 0:098463de4c5d 470 */
group-onsemi 0:098463de4c5d 471 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
group-onsemi 0:098463de4c5d 472 do{ \
group-onsemi 0:098463de4c5d 473 __IO uint32_t tmpreg_modf; \
group-onsemi 0:098463de4c5d 474 tmpreg_modf = (__HANDLE__)->Instance->SR; \
group-onsemi 0:098463de4c5d 475 (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
group-onsemi 0:098463de4c5d 476 UNUSED(tmpreg_modf); \
group-onsemi 0:098463de4c5d 477 } while(0)
group-onsemi 0:098463de4c5d 478
group-onsemi 0:098463de4c5d 479 /** @brief Clear the SPI OVR pending flag.
group-onsemi 0:098463de4c5d 480 * @param __HANDLE__: specifies the SPI Handle.
group-onsemi 0:098463de4c5d 481 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
group-onsemi 0:098463de4c5d 482 *
group-onsemi 0:098463de4c5d 483 * @retval None
group-onsemi 0:098463de4c5d 484 */
group-onsemi 0:098463de4c5d 485 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
group-onsemi 0:098463de4c5d 486 do{ \
group-onsemi 0:098463de4c5d 487 __IO uint32_t tmpreg_ovr; \
group-onsemi 0:098463de4c5d 488 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
group-onsemi 0:098463de4c5d 489 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
group-onsemi 0:098463de4c5d 490 UNUSED(tmpreg_ovr); \
group-onsemi 0:098463de4c5d 491 } while(0)
group-onsemi 0:098463de4c5d 492
group-onsemi 0:098463de4c5d 493 /** @brief Clear the SPI FRE pending flag.
group-onsemi 0:098463de4c5d 494 * @param __HANDLE__: specifies the SPI Handle.
group-onsemi 0:098463de4c5d 495 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
group-onsemi 0:098463de4c5d 496 *
group-onsemi 0:098463de4c5d 497 * @retval None
group-onsemi 0:098463de4c5d 498 */
group-onsemi 0:098463de4c5d 499 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
group-onsemi 0:098463de4c5d 500 do{ \
group-onsemi 0:098463de4c5d 501 __IO uint32_t tmpreg_fre; \
group-onsemi 0:098463de4c5d 502 tmpreg_fre = (__HANDLE__)->Instance->SR; \
group-onsemi 0:098463de4c5d 503 UNUSED(tmpreg_fre); \
group-onsemi 0:098463de4c5d 504 } while(0)
group-onsemi 0:098463de4c5d 505
group-onsemi 0:098463de4c5d 506 /** @brief Enable the SPI peripheral.
group-onsemi 0:098463de4c5d 507 * @param __HANDLE__: specifies the SPI Handle.
group-onsemi 0:098463de4c5d 508 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
group-onsemi 0:098463de4c5d 509 * @retval None
group-onsemi 0:098463de4c5d 510 */
group-onsemi 0:098463de4c5d 511 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
group-onsemi 0:098463de4c5d 512
group-onsemi 0:098463de4c5d 513 /** @brief Disable the SPI peripheral.
group-onsemi 0:098463de4c5d 514 * @param __HANDLE__: specifies the SPI Handle.
group-onsemi 0:098463de4c5d 515 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
group-onsemi 0:098463de4c5d 516 * @retval None
group-onsemi 0:098463de4c5d 517 */
group-onsemi 0:098463de4c5d 518 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
group-onsemi 0:098463de4c5d 519
group-onsemi 0:098463de4c5d 520 /**
group-onsemi 0:098463de4c5d 521 * @}
group-onsemi 0:098463de4c5d 522 */
group-onsemi 0:098463de4c5d 523
group-onsemi 0:098463de4c5d 524 /* Private macros --------------------------------------------------------*/
group-onsemi 0:098463de4c5d 525 /** @defgroup SPI_Private_Macros SPI Private Macros
group-onsemi 0:098463de4c5d 526 * @{
group-onsemi 0:098463de4c5d 527 */
group-onsemi 0:098463de4c5d 528
group-onsemi 0:098463de4c5d 529 /** @brief Set the SPI transmit-only mode.
group-onsemi 0:098463de4c5d 530 * @param __HANDLE__: specifies the SPI Handle.
group-onsemi 0:098463de4c5d 531 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
group-onsemi 0:098463de4c5d 532 * @retval None
group-onsemi 0:098463de4c5d 533 */
group-onsemi 0:098463de4c5d 534 #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
group-onsemi 0:098463de4c5d 535
group-onsemi 0:098463de4c5d 536 /** @brief Set the SPI receive-only mode.
group-onsemi 0:098463de4c5d 537 * @param __HANDLE__: specifies the SPI Handle.
group-onsemi 0:098463de4c5d 538 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
group-onsemi 0:098463de4c5d 539 * @retval None
group-onsemi 0:098463de4c5d 540 */
group-onsemi 0:098463de4c5d 541 #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
group-onsemi 0:098463de4c5d 542
group-onsemi 0:098463de4c5d 543 /** @brief Reset the CRC calculation of the SPI.
group-onsemi 0:098463de4c5d 544 * @param __HANDLE__: specifies the SPI Handle.
group-onsemi 0:098463de4c5d 545 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
group-onsemi 0:098463de4c5d 546 * @retval None
group-onsemi 0:098463de4c5d 547 */
group-onsemi 0:098463de4c5d 548 #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
group-onsemi 0:098463de4c5d 549 (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
group-onsemi 0:098463de4c5d 550
group-onsemi 0:098463de4c5d 551 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
group-onsemi 0:098463de4c5d 552 ((MODE) == SPI_MODE_MASTER))
group-onsemi 0:098463de4c5d 553
group-onsemi 0:098463de4c5d 554 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
group-onsemi 0:098463de4c5d 555 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
group-onsemi 0:098463de4c5d 556 ((MODE) == SPI_DIRECTION_1LINE))
group-onsemi 0:098463de4c5d 557
group-onsemi 0:098463de4c5d 558 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
group-onsemi 0:098463de4c5d 559
group-onsemi 0:098463de4c5d 560 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
group-onsemi 0:098463de4c5d 561 ((MODE) == SPI_DIRECTION_1LINE))
group-onsemi 0:098463de4c5d 562
group-onsemi 0:098463de4c5d 563 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
group-onsemi 0:098463de4c5d 564 ((DATASIZE) == SPI_DATASIZE_15BIT) || \
group-onsemi 0:098463de4c5d 565 ((DATASIZE) == SPI_DATASIZE_14BIT) || \
group-onsemi 0:098463de4c5d 566 ((DATASIZE) == SPI_DATASIZE_13BIT) || \
group-onsemi 0:098463de4c5d 567 ((DATASIZE) == SPI_DATASIZE_12BIT) || \
group-onsemi 0:098463de4c5d 568 ((DATASIZE) == SPI_DATASIZE_11BIT) || \
group-onsemi 0:098463de4c5d 569 ((DATASIZE) == SPI_DATASIZE_10BIT) || \
group-onsemi 0:098463de4c5d 570 ((DATASIZE) == SPI_DATASIZE_9BIT) || \
group-onsemi 0:098463de4c5d 571 ((DATASIZE) == SPI_DATASIZE_8BIT) || \
group-onsemi 0:098463de4c5d 572 ((DATASIZE) == SPI_DATASIZE_7BIT) || \
group-onsemi 0:098463de4c5d 573 ((DATASIZE) == SPI_DATASIZE_6BIT) || \
group-onsemi 0:098463de4c5d 574 ((DATASIZE) == SPI_DATASIZE_5BIT) || \
group-onsemi 0:098463de4c5d 575 ((DATASIZE) == SPI_DATASIZE_4BIT))
group-onsemi 0:098463de4c5d 576
group-onsemi 0:098463de4c5d 577 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
group-onsemi 0:098463de4c5d 578 ((CPOL) == SPI_POLARITY_HIGH))
group-onsemi 0:098463de4c5d 579
group-onsemi 0:098463de4c5d 580 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
group-onsemi 0:098463de4c5d 581 ((CPHA) == SPI_PHASE_2EDGE))
group-onsemi 0:098463de4c5d 582
group-onsemi 0:098463de4c5d 583 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
group-onsemi 0:098463de4c5d 584 ((NSS) == SPI_NSS_HARD_INPUT) || \
group-onsemi 0:098463de4c5d 585 ((NSS) == SPI_NSS_HARD_OUTPUT))
group-onsemi 0:098463de4c5d 586
group-onsemi 0:098463de4c5d 587 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
group-onsemi 0:098463de4c5d 588 ((NSSP) == SPI_NSS_PULSE_DISABLE))
group-onsemi 0:098463de4c5d 589
group-onsemi 0:098463de4c5d 590 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
group-onsemi 0:098463de4c5d 591 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
group-onsemi 0:098463de4c5d 592 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
group-onsemi 0:098463de4c5d 593 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
group-onsemi 0:098463de4c5d 594 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
group-onsemi 0:098463de4c5d 595 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
group-onsemi 0:098463de4c5d 596 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
group-onsemi 0:098463de4c5d 597 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
group-onsemi 0:098463de4c5d 598
group-onsemi 0:098463de4c5d 599 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
group-onsemi 0:098463de4c5d 600 ((BIT) == SPI_FIRSTBIT_LSB))
group-onsemi 0:098463de4c5d 601
group-onsemi 0:098463de4c5d 602 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
group-onsemi 0:098463de4c5d 603 ((MODE) == SPI_TIMODE_ENABLE))
group-onsemi 0:098463de4c5d 604
group-onsemi 0:098463de4c5d 605 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
group-onsemi 0:098463de4c5d 606 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
group-onsemi 0:098463de4c5d 607
group-onsemi 0:098463de4c5d 608 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
group-onsemi 0:098463de4c5d 609 ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
group-onsemi 0:098463de4c5d 610 ((LENGTH) == SPI_CRC_LENGTH_16BIT))
group-onsemi 0:098463de4c5d 611
group-onsemi 0:098463de4c5d 612 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF) && (((POLYNOMIAL)&0x1) != 0))
group-onsemi 0:098463de4c5d 613
group-onsemi 0:098463de4c5d 614
group-onsemi 0:098463de4c5d 615 /**
group-onsemi 0:098463de4c5d 616 * @}
group-onsemi 0:098463de4c5d 617 */
group-onsemi 0:098463de4c5d 618
group-onsemi 0:098463de4c5d 619 /* Include SPI HAL Extended module */
group-onsemi 0:098463de4c5d 620 #include "stm32f3xx_hal_spi_ex.h"
group-onsemi 0:098463de4c5d 621
group-onsemi 0:098463de4c5d 622 /* Exported functions --------------------------------------------------------*/
group-onsemi 0:098463de4c5d 623 /** @addtogroup SPI_Exported_Functions
group-onsemi 0:098463de4c5d 624 * @{
group-onsemi 0:098463de4c5d 625 */
group-onsemi 0:098463de4c5d 626
group-onsemi 0:098463de4c5d 627 /* Initialization and de-initialization functions ****************************/
group-onsemi 0:098463de4c5d 628 /** @addtogroup SPI_Exported_Functions_Group1
group-onsemi 0:098463de4c5d 629 * @{
group-onsemi 0:098463de4c5d 630 */
group-onsemi 0:098463de4c5d 631 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
group-onsemi 0:098463de4c5d 632 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
group-onsemi 0:098463de4c5d 633 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
group-onsemi 0:098463de4c5d 634 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
group-onsemi 0:098463de4c5d 635 /**
group-onsemi 0:098463de4c5d 636 * @}
group-onsemi 0:098463de4c5d 637 */
group-onsemi 0:098463de4c5d 638
group-onsemi 0:098463de4c5d 639 /* IO operation functions *****************************************************/
group-onsemi 0:098463de4c5d 640 /** @addtogroup SPI_Exported_Functions_Group2
group-onsemi 0:098463de4c5d 641 * @{
group-onsemi 0:098463de4c5d 642 */
group-onsemi 0:098463de4c5d 643 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
group-onsemi 0:098463de4c5d 644 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
group-onsemi 0:098463de4c5d 645 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
group-onsemi 0:098463de4c5d 646 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
group-onsemi 0:098463de4c5d 647 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
group-onsemi 0:098463de4c5d 648 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
group-onsemi 0:098463de4c5d 649 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
group-onsemi 0:098463de4c5d 650 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
group-onsemi 0:098463de4c5d 651 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
group-onsemi 0:098463de4c5d 652 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
group-onsemi 0:098463de4c5d 653 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
group-onsemi 0:098463de4c5d 654 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
group-onsemi 0:098463de4c5d 655
group-onsemi 0:098463de4c5d 656 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
group-onsemi 0:098463de4c5d 657 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
group-onsemi 0:098463de4c5d 658 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
group-onsemi 0:098463de4c5d 659 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
group-onsemi 0:098463de4c5d 660 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
group-onsemi 0:098463de4c5d 661 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
group-onsemi 0:098463de4c5d 662 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
group-onsemi 0:098463de4c5d 663 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
group-onsemi 0:098463de4c5d 664 /**
group-onsemi 0:098463de4c5d 665 * @}
group-onsemi 0:098463de4c5d 666 */
group-onsemi 0:098463de4c5d 667
group-onsemi 0:098463de4c5d 668 /* Peripheral State and Error functions ***************************************/
group-onsemi 0:098463de4c5d 669 /** @addtogroup SPI_Exported_Functions_Group3
group-onsemi 0:098463de4c5d 670 * @{
group-onsemi 0:098463de4c5d 671 */
group-onsemi 0:098463de4c5d 672 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
group-onsemi 0:098463de4c5d 673 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
group-onsemi 0:098463de4c5d 674 /**
group-onsemi 0:098463de4c5d 675 * @}
group-onsemi 0:098463de4c5d 676 */
group-onsemi 0:098463de4c5d 677
group-onsemi 0:098463de4c5d 678 /**
group-onsemi 0:098463de4c5d 679 * @}
group-onsemi 0:098463de4c5d 680 */
group-onsemi 0:098463de4c5d 681
group-onsemi 0:098463de4c5d 682 /**
group-onsemi 0:098463de4c5d 683 * @}
group-onsemi 0:098463de4c5d 684 */
group-onsemi 0:098463de4c5d 685
group-onsemi 0:098463de4c5d 686 /**
group-onsemi 0:098463de4c5d 687 * @}
group-onsemi 0:098463de4c5d 688 */
group-onsemi 0:098463de4c5d 689
group-onsemi 0:098463de4c5d 690 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 691 }
group-onsemi 0:098463de4c5d 692 #endif
group-onsemi 0:098463de4c5d 693
group-onsemi 0:098463de4c5d 694 #endif /* __STM32F3xx_HAL_SPI_H */
group-onsemi 0:098463de4c5d 695
group-onsemi 0:098463de4c5d 696 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/