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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2013 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 #include <stddef.h>
group-onsemi 0:098463de4c5d 17 #include "us_ticker_api.h"
group-onsemi 0:098463de4c5d 18 #include "PeripheralNames.h"
group-onsemi 0:098463de4c5d 19 #include "ostm_iodefine.h"
group-onsemi 0:098463de4c5d 20
group-onsemi 0:098463de4c5d 21 #include "RZ_A1_Init.h"
group-onsemi 0:098463de4c5d 22 #include "MBRZA1H.h"
group-onsemi 0:098463de4c5d 23 #include "vfp_neon_push_pop.h"
group-onsemi 0:098463de4c5d 24
group-onsemi 0:098463de4c5d 25 #define US_TICKER_TIMER_IRQn (OSTMI1TINT_IRQn)
group-onsemi 0:098463de4c5d 26 #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
group-onsemi 0:098463de4c5d 27
group-onsemi 0:098463de4c5d 28 #define US_TICKER_CLOCK_US_DEV (1000000)
group-onsemi 0:098463de4c5d 29
group-onsemi 0:098463de4c5d 30 int us_ticker_inited = 0;
group-onsemi 0:098463de4c5d 31 static double count_clock = 0;
group-onsemi 0:098463de4c5d 32 static uint32_t last_read = 0;
group-onsemi 0:098463de4c5d 33 static uint32_t wrap_arround = 0;
group-onsemi 0:098463de4c5d 34 static uint64_t ticker_us_last64 = 0;
group-onsemi 0:098463de4c5d 35 static uint64_t set_cmp_val64 = 0;
group-onsemi 0:098463de4c5d 36 static uint64_t timestamp64 = 0;
group-onsemi 0:098463de4c5d 37
group-onsemi 0:098463de4c5d 38 void us_ticker_interrupt(void) {
group-onsemi 0:098463de4c5d 39 us_ticker_irq_handler();
group-onsemi 0:098463de4c5d 40 }
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 void us_ticker_init(void) {
group-onsemi 0:098463de4c5d 43 if (us_ticker_inited) return;
group-onsemi 0:098463de4c5d 44 us_ticker_inited = 1;
group-onsemi 0:098463de4c5d 45
group-onsemi 0:098463de4c5d 46 /* set Counter Clock(us) */
group-onsemi 0:098463de4c5d 47 if (false == RZ_A1_IsClockMode0()) {
group-onsemi 0:098463de4c5d 48 count_clock = ((double)CM1_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
group-onsemi 0:098463de4c5d 49 } else {
group-onsemi 0:098463de4c5d 50 count_clock = ((double)CM0_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
group-onsemi 0:098463de4c5d 51 }
group-onsemi 0:098463de4c5d 52
group-onsemi 0:098463de4c5d 53 /* Power Control for Peripherals */
group-onsemi 0:098463de4c5d 54 CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */
group-onsemi 0:098463de4c5d 55
group-onsemi 0:098463de4c5d 56 // timer settings
group-onsemi 0:098463de4c5d 57 OSTM1TT = 0x01; /* Stop the counter and clears the OSTM1TE bit. */
group-onsemi 0:098463de4c5d 58 OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */
group-onsemi 0:098463de4c5d 59
group-onsemi 0:098463de4c5d 60 OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */
group-onsemi 0:098463de4c5d 61
group-onsemi 0:098463de4c5d 62 // INTC settings
group-onsemi 0:098463de4c5d 63 InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt);
group-onsemi 0:098463de4c5d 64 GIC_SetPriority(US_TICKER_TIMER_IRQn, 5);
group-onsemi 0:098463de4c5d 65 GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
group-onsemi 0:098463de4c5d 66 }
group-onsemi 0:098463de4c5d 67
group-onsemi 0:098463de4c5d 68 static uint64_t ticker_read_counter64(void) {
group-onsemi 0:098463de4c5d 69 uint32_t cnt_val;
group-onsemi 0:098463de4c5d 70 uint64_t cnt_val64;
group-onsemi 0:098463de4c5d 71
group-onsemi 0:098463de4c5d 72 if (!us_ticker_inited)
group-onsemi 0:098463de4c5d 73 us_ticker_init();
group-onsemi 0:098463de4c5d 74
group-onsemi 0:098463de4c5d 75 /* read counter */
group-onsemi 0:098463de4c5d 76 cnt_val = OSTM1CNT;
group-onsemi 0:098463de4c5d 77 if (last_read > cnt_val) {
group-onsemi 0:098463de4c5d 78 wrap_arround++;
group-onsemi 0:098463de4c5d 79 }
group-onsemi 0:098463de4c5d 80 last_read = cnt_val;
group-onsemi 0:098463de4c5d 81 cnt_val64 = ((uint64_t)wrap_arround << 32) + cnt_val;
group-onsemi 0:098463de4c5d 82
group-onsemi 0:098463de4c5d 83 return cnt_val64;
group-onsemi 0:098463de4c5d 84 }
group-onsemi 0:098463de4c5d 85
group-onsemi 0:098463de4c5d 86 static void us_ticker_read_last(void) {
group-onsemi 0:098463de4c5d 87 uint64_t cnt_val64;
group-onsemi 0:098463de4c5d 88
group-onsemi 0:098463de4c5d 89 cnt_val64 = ticker_read_counter64();
group-onsemi 0:098463de4c5d 90
group-onsemi 0:098463de4c5d 91 ticker_us_last64 = (cnt_val64 / count_clock);
group-onsemi 0:098463de4c5d 92 }
group-onsemi 0:098463de4c5d 93
group-onsemi 0:098463de4c5d 94 uint32_t us_ticker_read() {
group-onsemi 0:098463de4c5d 95 int check_irq_masked;
group-onsemi 0:098463de4c5d 96
group-onsemi 0:098463de4c5d 97 #if defined ( __ICCARM__)
group-onsemi 0:098463de4c5d 98 check_irq_masked = __disable_irq_iar();
group-onsemi 0:098463de4c5d 99 #else
group-onsemi 0:098463de4c5d 100 check_irq_masked = __disable_irq();
group-onsemi 0:098463de4c5d 101 #endif /* __ICCARM__ */
group-onsemi 0:098463de4c5d 102
group-onsemi 0:098463de4c5d 103 __vfp_neon_push();
group-onsemi 0:098463de4c5d 104 us_ticker_read_last();
group-onsemi 0:098463de4c5d 105 __vfp_neon_pop();
group-onsemi 0:098463de4c5d 106
group-onsemi 0:098463de4c5d 107 if (!check_irq_masked) {
group-onsemi 0:098463de4c5d 108 __enable_irq();
group-onsemi 0:098463de4c5d 109 }
group-onsemi 0:098463de4c5d 110
group-onsemi 0:098463de4c5d 111 /* clock to us */
group-onsemi 0:098463de4c5d 112 return (uint32_t)ticker_us_last64;
group-onsemi 0:098463de4c5d 113 }
group-onsemi 0:098463de4c5d 114
group-onsemi 0:098463de4c5d 115 static void us_ticker_calc_compare_match(void) {
group-onsemi 0:098463de4c5d 116 set_cmp_val64 = timestamp64 * count_clock;
group-onsemi 0:098463de4c5d 117 }
group-onsemi 0:098463de4c5d 118
group-onsemi 0:098463de4c5d 119 void us_ticker_set_interrupt(timestamp_t timestamp) {
group-onsemi 0:098463de4c5d 120 // set match value
group-onsemi 0:098463de4c5d 121 volatile uint32_t set_cmp_val;
group-onsemi 0:098463de4c5d 122 uint64_t count_val_64;
group-onsemi 0:098463de4c5d 123
group-onsemi 0:098463de4c5d 124 /* calc compare mach timestamp */
group-onsemi 0:098463de4c5d 125 timestamp64 = (ticker_us_last64 & 0xFFFFFFFF00000000) + timestamp;
group-onsemi 0:098463de4c5d 126 if (timestamp < (ticker_us_last64 & 0x00000000FFFFFFFF)) {
group-onsemi 0:098463de4c5d 127 /* This event is wrap arround */
group-onsemi 0:098463de4c5d 128 timestamp64 += 0x100000000;
group-onsemi 0:098463de4c5d 129 }
group-onsemi 0:098463de4c5d 130
group-onsemi 0:098463de4c5d 131 /* calc compare mach timestamp */
group-onsemi 0:098463de4c5d 132 __vfp_neon_push();
group-onsemi 0:098463de4c5d 133 us_ticker_calc_compare_match();
group-onsemi 0:098463de4c5d 134 __vfp_neon_pop();
group-onsemi 0:098463de4c5d 135
group-onsemi 0:098463de4c5d 136 set_cmp_val = (uint32_t)(set_cmp_val64 & 0x00000000FFFFFFFF);
group-onsemi 0:098463de4c5d 137 count_val_64 = ticker_read_counter64();
group-onsemi 0:098463de4c5d 138 if (set_cmp_val64 <= (count_val_64 + 500)) {
group-onsemi 0:098463de4c5d 139 GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
group-onsemi 0:098463de4c5d 140 GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
group-onsemi 0:098463de4c5d 141 return;
group-onsemi 0:098463de4c5d 142 }
group-onsemi 0:098463de4c5d 143 OSTM1CMP = set_cmp_val;
group-onsemi 0:098463de4c5d 144 GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
group-onsemi 0:098463de4c5d 145 }
group-onsemi 0:098463de4c5d 146
group-onsemi 0:098463de4c5d 147 void us_ticker_disable_interrupt(void) {
group-onsemi 0:098463de4c5d 148 GIC_DisableIRQ(US_TICKER_TIMER_IRQn);
group-onsemi 0:098463de4c5d 149 }
group-onsemi 0:098463de4c5d 150
group-onsemi 0:098463de4c5d 151 void us_ticker_clear_interrupt(void) {
group-onsemi 0:098463de4c5d 152 GIC_ClearPendingIRQ(US_TICKER_TIMER_IRQn);
group-onsemi 0:098463de4c5d 153 }