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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NXP/TARGET_LPC2460/analogin_api.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2015 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 17 #include "analogin_api.h"
group-onsemi 0:098463de4c5d 18 #include "cmsis.h"
group-onsemi 0:098463de4c5d 19 #include "pinmap.h"
group-onsemi 0:098463de4c5d 20
group-onsemi 0:098463de4c5d 21 #define ANALOGIN_MEDIAN_FILTER 1
group-onsemi 0:098463de4c5d 22
group-onsemi 0:098463de4c5d 23 #define ADC_10BIT_RANGE 0x3FF
group-onsemi 0:098463de4c5d 24 #define ADC_12BIT_RANGE 0xFFF
group-onsemi 0:098463de4c5d 25
group-onsemi 0:098463de4c5d 26 static inline int div_round_up(int x, int y) {
group-onsemi 0:098463de4c5d 27 return (x + (y - 1)) / y;
group-onsemi 0:098463de4c5d 28 }
group-onsemi 0:098463de4c5d 29
group-onsemi 0:098463de4c5d 30 static const PinMap PinMap_ADC[] = {
group-onsemi 0:098463de4c5d 31 {P0_23, ADC0_0, 1},
group-onsemi 0:098463de4c5d 32 {P0_24, ADC0_1, 1},
group-onsemi 0:098463de4c5d 33 {P0_25, ADC0_2, 1},
group-onsemi 0:098463de4c5d 34 {P0_26, ADC0_3, 1},
group-onsemi 0:098463de4c5d 35 {P1_30, ADC0_4, 3},
group-onsemi 0:098463de4c5d 36 {P1_31, ADC0_5, 3},
group-onsemi 0:098463de4c5d 37 {P0_12, ADC0_6, 3},
group-onsemi 0:098463de4c5d 38 {P0_13, ADC0_7, 3},
group-onsemi 0:098463de4c5d 39 {NC, NC, 0}
group-onsemi 0:098463de4c5d 40 };
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 #define ADC_RANGE ADC_10BIT_RANGE
group-onsemi 0:098463de4c5d 43
group-onsemi 0:098463de4c5d 44
group-onsemi 0:098463de4c5d 45 void analogin_init(analogin_t *obj, PinName pin) {
group-onsemi 0:098463de4c5d 46 obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
group-onsemi 0:098463de4c5d 47 MBED_ASSERT(obj->adc != (ADCName)NC);
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49 // ensure power is turned on
group-onsemi 0:098463de4c5d 50 LPC_SC->PCONP |= (1 << PCADC);
group-onsemi 0:098463de4c5d 51
group-onsemi 0:098463de4c5d 52 // set PCLK of ADC to /1
group-onsemi 0:098463de4c5d 53 LPC_SC->PCLKSEL0 &= ~(0x3 << 24);
group-onsemi 0:098463de4c5d 54 LPC_SC->PCLKSEL0 |= (0x1 << 24);
group-onsemi 0:098463de4c5d 55 uint32_t PCLK = SystemCoreClock;
group-onsemi 0:098463de4c5d 56
group-onsemi 0:098463de4c5d 57 // calculate minimum clock divider
group-onsemi 0:098463de4c5d 58 // clkdiv = divider - 1
group-onsemi 0:098463de4c5d 59 uint32_t MAX_ADC_CLK = 4500000;
group-onsemi 0:098463de4c5d 60 uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1;
group-onsemi 0:098463de4c5d 61
group-onsemi 0:098463de4c5d 62 // Set the generic software-controlled ADC settings
group-onsemi 0:098463de4c5d 63 LPC_ADC->ADCR = (0 << 0) // SEL: 0 = no channels selected
group-onsemi 0:098463de4c5d 64 | (clkdiv << 8) // CLKDIV: PCLK max ~= 25MHz, /25 to give safe 1MHz at fastest
group-onsemi 0:098463de4c5d 65 | (0 << 16) // BURST: 0 = software control
group-onsemi 0:098463de4c5d 66 | (0 << 17) // CLKS: not applicable
group-onsemi 0:098463de4c5d 67 | (1 << 21) // PDN: 1 = operational
group-onsemi 0:098463de4c5d 68 | (0 << 24) // START: 0 = no start
group-onsemi 0:098463de4c5d 69 | (0 << 27); // EDGE: not applicable
group-onsemi 0:098463de4c5d 70
group-onsemi 0:098463de4c5d 71 pinmap_pinout(pin, PinMap_ADC);
group-onsemi 0:098463de4c5d 72 }
group-onsemi 0:098463de4c5d 73
group-onsemi 0:098463de4c5d 74 static inline uint32_t adc_read(analogin_t *obj) {
group-onsemi 0:098463de4c5d 75 // Select the appropriate channel and start conversion
group-onsemi 0:098463de4c5d 76 LPC_ADC->ADCR &= ~0xFF;
group-onsemi 0:098463de4c5d 77 LPC_ADC->ADCR |= 1 << (int)obj->adc;
group-onsemi 0:098463de4c5d 78 LPC_ADC->ADCR |= 1 << 24;
group-onsemi 0:098463de4c5d 79
group-onsemi 0:098463de4c5d 80 // Repeatedly get the sample data until DONE bit
group-onsemi 0:098463de4c5d 81 unsigned int data;
group-onsemi 0:098463de4c5d 82 do {
group-onsemi 0:098463de4c5d 83 data = LPC_ADC->ADGDR;
group-onsemi 0:098463de4c5d 84 } while ((data & ((unsigned int)1 << 31)) == 0);
group-onsemi 0:098463de4c5d 85
group-onsemi 0:098463de4c5d 86 // Stop conversion
group-onsemi 0:098463de4c5d 87 LPC_ADC->ADCR &= ~(1 << 24);
group-onsemi 0:098463de4c5d 88
group-onsemi 0:098463de4c5d 89 return (data >> 6) & ADC_RANGE; // 10 bit
group-onsemi 0:098463de4c5d 90 }
group-onsemi 0:098463de4c5d 91
group-onsemi 0:098463de4c5d 92 static inline void order(uint32_t *a, uint32_t *b) {
group-onsemi 0:098463de4c5d 93 if (*a > *b) {
group-onsemi 0:098463de4c5d 94 uint32_t t = *a;
group-onsemi 0:098463de4c5d 95 *a = *b;
group-onsemi 0:098463de4c5d 96 *b = t;
group-onsemi 0:098463de4c5d 97 }
group-onsemi 0:098463de4c5d 98 }
group-onsemi 0:098463de4c5d 99
group-onsemi 0:098463de4c5d 100 static inline uint32_t adc_read_u32(analogin_t *obj) {
group-onsemi 0:098463de4c5d 101 uint32_t value;
group-onsemi 0:098463de4c5d 102 #if ANALOGIN_MEDIAN_FILTER
group-onsemi 0:098463de4c5d 103 uint32_t v1 = adc_read(obj);
group-onsemi 0:098463de4c5d 104 uint32_t v2 = adc_read(obj);
group-onsemi 0:098463de4c5d 105 uint32_t v3 = adc_read(obj);
group-onsemi 0:098463de4c5d 106 order(&v1, &v2);
group-onsemi 0:098463de4c5d 107 order(&v2, &v3);
group-onsemi 0:098463de4c5d 108 order(&v1, &v2);
group-onsemi 0:098463de4c5d 109 value = v2;
group-onsemi 0:098463de4c5d 110 #else
group-onsemi 0:098463de4c5d 111 value = adc_read(obj);
group-onsemi 0:098463de4c5d 112 #endif
group-onsemi 0:098463de4c5d 113 return value;
group-onsemi 0:098463de4c5d 114 }
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 uint16_t analogin_read_u16(analogin_t *obj) {
group-onsemi 0:098463de4c5d 117 uint32_t value = adc_read_u32(obj);
group-onsemi 0:098463de4c5d 118
group-onsemi 0:098463de4c5d 119 return (value << 6) | ((value >> 4) & 0x003F); // 10 bit
group-onsemi 0:098463de4c5d 120 }
group-onsemi 0:098463de4c5d 121
group-onsemi 0:098463de4c5d 122 float analogin_read(analogin_t *obj) {
group-onsemi 0:098463de4c5d 123 uint32_t value = adc_read_u32(obj);
group-onsemi 0:098463de4c5d 124 return (float)value * (1.0f / (float)ADC_RANGE);
group-onsemi 0:098463de4c5d 125 }