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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NXP/TARGET_LPC15XX/gpio_irq_api.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2013 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 #include <stddef.h>
group-onsemi 0:098463de4c5d 17
group-onsemi 0:098463de4c5d 18 #include "cmsis.h"
group-onsemi 0:098463de4c5d 19 #include "gpio_irq_api.h"
group-onsemi 0:098463de4c5d 20 #include "mbed_error.h"
group-onsemi 0:098463de4c5d 21
group-onsemi 0:098463de4c5d 22 #define CHANNEL_NUM 8
group-onsemi 0:098463de4c5d 23 #define LPC_GPIO_X LPC_PINT
group-onsemi 0:098463de4c5d 24 #define PININT_IRQ PIN_INT0_IRQn
group-onsemi 0:098463de4c5d 25
group-onsemi 0:098463de4c5d 26 static uint32_t channel_ids[CHANNEL_NUM] = {0};
group-onsemi 0:098463de4c5d 27 static gpio_irq_handler irq_handler;
group-onsemi 0:098463de4c5d 28
group-onsemi 0:098463de4c5d 29 static inline void handle_interrupt_in(uint32_t channel) {
group-onsemi 0:098463de4c5d 30 uint32_t ch_bit = (1 << channel);
group-onsemi 0:098463de4c5d 31 // Return immediately if:
group-onsemi 0:098463de4c5d 32 // * The interrupt was already served
group-onsemi 0:098463de4c5d 33 // * There is no user handler
group-onsemi 0:098463de4c5d 34 // * It is a level interrupt, not an edge interrupt
group-onsemi 0:098463de4c5d 35 if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
group-onsemi 0:098463de4c5d 36 (channel_ids[channel] == 0 ) ||
group-onsemi 0:098463de4c5d 37 (LPC_GPIO_X->ISEL & ch_bit ) ) return;
group-onsemi 0:098463de4c5d 38
group-onsemi 0:098463de4c5d 39 if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
group-onsemi 0:098463de4c5d 40 irq_handler(channel_ids[channel], IRQ_RISE);
group-onsemi 0:098463de4c5d 41 LPC_GPIO_X->RISE = ch_bit;
group-onsemi 0:098463de4c5d 42 }
group-onsemi 0:098463de4c5d 43 if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
group-onsemi 0:098463de4c5d 44 irq_handler(channel_ids[channel], IRQ_FALL);
group-onsemi 0:098463de4c5d 45 LPC_GPIO_X->FALL = ch_bit;
group-onsemi 0:098463de4c5d 46 }
group-onsemi 0:098463de4c5d 47 LPC_GPIO_X->IST = ch_bit;
group-onsemi 0:098463de4c5d 48 }
group-onsemi 0:098463de4c5d 49
group-onsemi 0:098463de4c5d 50 void gpio_irq0(void) {handle_interrupt_in(0);}
group-onsemi 0:098463de4c5d 51 void gpio_irq1(void) {handle_interrupt_in(1);}
group-onsemi 0:098463de4c5d 52 void gpio_irq2(void) {handle_interrupt_in(2);}
group-onsemi 0:098463de4c5d 53 void gpio_irq3(void) {handle_interrupt_in(3);}
group-onsemi 0:098463de4c5d 54 void gpio_irq4(void) {handle_interrupt_in(4);}
group-onsemi 0:098463de4c5d 55 void gpio_irq5(void) {handle_interrupt_in(5);}
group-onsemi 0:098463de4c5d 56 void gpio_irq6(void) {handle_interrupt_in(6);}
group-onsemi 0:098463de4c5d 57 void gpio_irq7(void) {handle_interrupt_in(7);}
group-onsemi 0:098463de4c5d 58
group-onsemi 0:098463de4c5d 59 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
group-onsemi 0:098463de4c5d 60 // PINT only supprt GPIO port 0 and 1 interrupt
group-onsemi 0:098463de4c5d 61 if (pin >= P2_0) return -1;
group-onsemi 0:098463de4c5d 62
group-onsemi 0:098463de4c5d 63 irq_handler = handler;
group-onsemi 0:098463de4c5d 64
group-onsemi 0:098463de4c5d 65 int found_free_channel = 0;
group-onsemi 0:098463de4c5d 66 int i = 0;
group-onsemi 0:098463de4c5d 67 for (i=0; i<CHANNEL_NUM; i++) {
group-onsemi 0:098463de4c5d 68 if (channel_ids[i] == 0) {
group-onsemi 0:098463de4c5d 69 channel_ids[i] = id;
group-onsemi 0:098463de4c5d 70 obj->ch = i;
group-onsemi 0:098463de4c5d 71 found_free_channel = 1;
group-onsemi 0:098463de4c5d 72 break;
group-onsemi 0:098463de4c5d 73 }
group-onsemi 0:098463de4c5d 74 }
group-onsemi 0:098463de4c5d 75 if (!found_free_channel) return -1;
group-onsemi 0:098463de4c5d 76
group-onsemi 0:098463de4c5d 77 /* Enable AHB clock to the PIN, GPIO0/1, IOCON and MUX domain. */
group-onsemi 0:098463de4c5d 78 LPC_SYSCON->SYSAHBCLKCTRL0 |= ((1 << 18) | (0x1D << 11));
group-onsemi 0:098463de4c5d 79
group-onsemi 0:098463de4c5d 80 LPC_INMUX->PINTSEL[obj->ch] = pin;
group-onsemi 0:098463de4c5d 81
group-onsemi 0:098463de4c5d 82 // Interrupt Wake-Up Enable
group-onsemi 0:098463de4c5d 83 LPC_SYSCON->STARTERP0 |= (1 << (obj->ch + 5));
group-onsemi 0:098463de4c5d 84
group-onsemi 0:098463de4c5d 85 LPC_GPIO_PORT->DIR[pin >> 5] &= ~(1 << (pin & 0x1F));
group-onsemi 0:098463de4c5d 86
group-onsemi 0:098463de4c5d 87 void (*channels_irq)(void) = NULL;
group-onsemi 0:098463de4c5d 88 switch (obj->ch) {
group-onsemi 0:098463de4c5d 89 case 0: channels_irq = &gpio_irq0; break;
group-onsemi 0:098463de4c5d 90 case 1: channels_irq = &gpio_irq1; break;
group-onsemi 0:098463de4c5d 91 case 2: channels_irq = &gpio_irq2; break;
group-onsemi 0:098463de4c5d 92 case 3: channels_irq = &gpio_irq3; break;
group-onsemi 0:098463de4c5d 93 case 4: channels_irq = &gpio_irq4; break;
group-onsemi 0:098463de4c5d 94 case 5: channels_irq = &gpio_irq5; break;
group-onsemi 0:098463de4c5d 95 case 6: channels_irq = &gpio_irq6; break;
group-onsemi 0:098463de4c5d 96 case 7: channels_irq = &gpio_irq7; break;
group-onsemi 0:098463de4c5d 97 }
group-onsemi 0:098463de4c5d 98 NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
group-onsemi 0:098463de4c5d 99 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
group-onsemi 0:098463de4c5d 100
group-onsemi 0:098463de4c5d 101 return 0;
group-onsemi 0:098463de4c5d 102 }
group-onsemi 0:098463de4c5d 103
group-onsemi 0:098463de4c5d 104 void gpio_irq_free(gpio_irq_t *obj) {
group-onsemi 0:098463de4c5d 105 channel_ids[obj->ch] = 0;
group-onsemi 0:098463de4c5d 106 LPC_SYSCON->STARTERP0 &= ~(1 << (obj->ch + 5));
group-onsemi 0:098463de4c5d 107 }
group-onsemi 0:098463de4c5d 108
group-onsemi 0:098463de4c5d 109 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
group-onsemi 0:098463de4c5d 110 unsigned int ch_bit = (1 << obj->ch);
group-onsemi 0:098463de4c5d 111
group-onsemi 0:098463de4c5d 112 // Clear interrupt
group-onsemi 0:098463de4c5d 113 if (!(LPC_GPIO_X->ISEL & ch_bit))
group-onsemi 0:098463de4c5d 114 LPC_GPIO_X->IST = ch_bit;
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 // Edge trigger
group-onsemi 0:098463de4c5d 117 LPC_GPIO_X->ISEL &= ~ch_bit;
group-onsemi 0:098463de4c5d 118 if (event == IRQ_RISE) {
group-onsemi 0:098463de4c5d 119 if (enable) {
group-onsemi 0:098463de4c5d 120 LPC_GPIO_X->IENR |= ch_bit;
group-onsemi 0:098463de4c5d 121 } else {
group-onsemi 0:098463de4c5d 122 LPC_GPIO_X->IENR &= ~ch_bit;
group-onsemi 0:098463de4c5d 123 }
group-onsemi 0:098463de4c5d 124 } else {
group-onsemi 0:098463de4c5d 125 if (enable) {
group-onsemi 0:098463de4c5d 126 LPC_GPIO_X->IENF |= ch_bit;
group-onsemi 0:098463de4c5d 127 } else {
group-onsemi 0:098463de4c5d 128 LPC_GPIO_X->IENF &= ~ch_bit;
group-onsemi 0:098463de4c5d 129 }
group-onsemi 0:098463de4c5d 130 }
group-onsemi 0:098463de4c5d 131 }
group-onsemi 0:098463de4c5d 132
group-onsemi 0:098463de4c5d 133 void gpio_irq_enable(gpio_irq_t *obj) {
group-onsemi 0:098463de4c5d 134 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
group-onsemi 0:098463de4c5d 135 }
group-onsemi 0:098463de4c5d 136
group-onsemi 0:098463de4c5d 137 void gpio_irq_disable(gpio_irq_t *obj) {
group-onsemi 0:098463de4c5d 138 NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
group-onsemi 0:098463de4c5d 139 }