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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /******************************************************************************
group-onsemi 0:098463de4c5d 2 * @file system_M451Series.c
group-onsemi 0:098463de4c5d 3 * @version V0.10
group-onsemi 0:098463de4c5d 4 * $Revision: 11 $
group-onsemi 0:098463de4c5d 5 * $Date: 15/09/02 10:02a $
group-onsemi 0:098463de4c5d 6 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M451 Series MCU
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * @note
group-onsemi 0:098463de4c5d 9 * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
group-onsemi 0:098463de4c5d 10 *****************************************************************************/
group-onsemi 0:098463de4c5d 11
group-onsemi 0:098463de4c5d 12 #include "M451Series.h"
group-onsemi 0:098463de4c5d 13
group-onsemi 0:098463de4c5d 14
group-onsemi 0:098463de4c5d 15 /*----------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 16 DEFINES
group-onsemi 0:098463de4c5d 17 *----------------------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 18
group-onsemi 0:098463de4c5d 19
group-onsemi 0:098463de4c5d 20 /*----------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 21 Clock Variable definitions
group-onsemi 0:098463de4c5d 22 *----------------------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 23 uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
group-onsemi 0:098463de4c5d 24 uint32_t CyclesPerUs = (__HSI / 1000000); /* Cycles per micro second */
group-onsemi 0:098463de4c5d 25 uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
group-onsemi 0:098463de4c5d 26 uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0, __LIRC, 0, 0, 0, __HIRC};
group-onsemi 0:098463de4c5d 27
group-onsemi 0:098463de4c5d 28 /*----------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 29 Clock functions
group-onsemi 0:098463de4c5d 30 *----------------------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 31 void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
group-onsemi 0:098463de4c5d 32 {
group-onsemi 0:098463de4c5d 33 #if 1
group-onsemi 0:098463de4c5d 34 uint32_t u32Freq, u32ClkSrc;
group-onsemi 0:098463de4c5d 35 uint32_t u32HclkDiv;
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 /* Update PLL Clock */
group-onsemi 0:098463de4c5d 38 PllClock = CLK_GetPLLClockFreq();
group-onsemi 0:098463de4c5d 39
group-onsemi 0:098463de4c5d 40 u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
group-onsemi 0:098463de4c5d 43 {
group-onsemi 0:098463de4c5d 44 /* Use PLL clock */
group-onsemi 0:098463de4c5d 45 u32Freq = PllClock;
group-onsemi 0:098463de4c5d 46 }
group-onsemi 0:098463de4c5d 47 else
group-onsemi 0:098463de4c5d 48 {
group-onsemi 0:098463de4c5d 49 /* Use the clock sources directly */
group-onsemi 0:098463de4c5d 50 u32Freq = gau32ClkSrcTbl[u32ClkSrc];
group-onsemi 0:098463de4c5d 51 }
group-onsemi 0:098463de4c5d 52
group-onsemi 0:098463de4c5d 53 u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
group-onsemi 0:098463de4c5d 54
group-onsemi 0:098463de4c5d 55 /* Update System Core Clock */
group-onsemi 0:098463de4c5d 56 SystemCoreClock = u32Freq / u32HclkDiv;
group-onsemi 0:098463de4c5d 57
group-onsemi 0:098463de4c5d 58
group-onsemi 0:098463de4c5d 59 //if(SystemCoreClock == 0)
group-onsemi 0:098463de4c5d 60 // __BKPT(0);
group-onsemi 0:098463de4c5d 61
group-onsemi 0:098463de4c5d 62 CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
group-onsemi 0:098463de4c5d 63 #endif
group-onsemi 0:098463de4c5d 64 }
group-onsemi 0:098463de4c5d 65
group-onsemi 0:098463de4c5d 66 /**
group-onsemi 0:098463de4c5d 67 * Initialize the system
group-onsemi 0:098463de4c5d 68 *
group-onsemi 0:098463de4c5d 69 * @param None
group-onsemi 0:098463de4c5d 70 * @return None
group-onsemi 0:098463de4c5d 71 *
group-onsemi 0:098463de4c5d 72 * @brief Setup the microcontroller system.
group-onsemi 0:098463de4c5d 73 * Initialize the System.
group-onsemi 0:098463de4c5d 74 */
group-onsemi 0:098463de4c5d 75 void SystemInit(void)
group-onsemi 0:098463de4c5d 76 {
group-onsemi 0:098463de4c5d 77 /* ToDo: add code to initialize the system
group-onsemi 0:098463de4c5d 78 do not use global variables because this function is called before
group-onsemi 0:098463de4c5d 79 reaching pre-main. RW section maybe overwritten afterwards. */
group-onsemi 0:098463de4c5d 80
group-onsemi 0:098463de4c5d 81 SYS_UnlockReg();
group-onsemi 0:098463de4c5d 82 /* One-time POR18 */
group-onsemi 0:098463de4c5d 83 if((SYS->PDID >> 12) == 0x945)
group-onsemi 0:098463de4c5d 84 {
group-onsemi 0:098463de4c5d 85 M32(GCR_BASE+0x14) |= BIT7;
group-onsemi 0:098463de4c5d 86 }
group-onsemi 0:098463de4c5d 87 /* Force to use INV type with HXT */
group-onsemi 0:098463de4c5d 88 CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk;
group-onsemi 0:098463de4c5d 89 SYS_LockReg();
group-onsemi 0:098463de4c5d 90
group-onsemi 0:098463de4c5d 91
group-onsemi 0:098463de4c5d 92 #if 0
group-onsemi 0:098463de4c5d 93 // NOTE: C-runtime not initialized yet. Ensure no static memory (global variable) are accessed in this function.
group-onsemi 0:098463de4c5d 94 nu_ebi_init();
group-onsemi 0:098463de4c5d 95 #endif
group-onsemi 0:098463de4c5d 96
group-onsemi 0:098463de4c5d 97 /* FPU settings ------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 98 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
group-onsemi 0:098463de4c5d 99 SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */
group-onsemi 0:098463de4c5d 100 (3UL << 11 * 2)); /* set CP11 Full Access */
group-onsemi 0:098463de4c5d 101 #endif
group-onsemi 0:098463de4c5d 102
group-onsemi 0:098463de4c5d 103 }
group-onsemi 0:098463de4c5d 104
group-onsemi 0:098463de4c5d 105 #if 0
group-onsemi 0:098463de4c5d 106 void nu_ebi_init(void)
group-onsemi 0:098463de4c5d 107 {
group-onsemi 0:098463de4c5d 108 // TO BE CONTINUED
group-onsemi 0:098463de4c5d 109 }
group-onsemi 0:098463de4c5d 110 #endif
group-onsemi 0:098463de4c5d 111 /*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/