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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Maxim/TARGET_MAX32620/device/pmu_regs.h@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #ifndef _MXC_PMU_REGS_H_
group-onsemi 0:098463de4c5d 35 #define _MXC_PMU_REGS_H_
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 38 extern "C" {
group-onsemi 0:098463de4c5d 39 #endif
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 #include <stdint.h>
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 /*
group-onsemi 0:098463de4c5d 44 If types are not defined elsewhere (CMSIS) define them here
group-onsemi 0:098463de4c5d 45 */
group-onsemi 0:098463de4c5d 46 #ifndef __IO
group-onsemi 0:098463de4c5d 47 #define __IO volatile
group-onsemi 0:098463de4c5d 48 #endif
group-onsemi 0:098463de4c5d 49 #ifndef __I
group-onsemi 0:098463de4c5d 50 #define __I volatile const
group-onsemi 0:098463de4c5d 51 #endif
group-onsemi 0:098463de4c5d 52 #ifndef __O
group-onsemi 0:098463de4c5d 53 #define __O volatile
group-onsemi 0:098463de4c5d 54 #endif
group-onsemi 0:098463de4c5d 55
group-onsemi 0:098463de4c5d 56
group-onsemi 0:098463de4c5d 57 typedef struct {
group-onsemi 0:098463de4c5d 58 __IO uint32_t start_opcode[32];
group-onsemi 0:098463de4c5d 59 __IO uint32_t enable;
group-onsemi 0:098463de4c5d 60 __IO uint32_t rsvd0;
group-onsemi 0:098463de4c5d 61 __IO uint32_t ll_stopped;
group-onsemi 0:098463de4c5d 62 __IO uint32_t manual;
group-onsemi 0:098463de4c5d 63 __IO uint32_t bus_error;
group-onsemi 0:098463de4c5d 64 __IO uint32_t rsvd1;
group-onsemi 0:098463de4c5d 65 __IO uint32_t to_stat;
group-onsemi 0:098463de4c5d 66 __IO uint32_t rsvd2[4];
group-onsemi 0:098463de4c5d 67 __IO uint32_t to_sel[3];
group-onsemi 0:098463de4c5d 68 __IO uint32_t ps_sel[2];
group-onsemi 0:098463de4c5d 69 __IO uint32_t interrupt;
group-onsemi 0:098463de4c5d 70 __IO uint32_t int_enable;
group-onsemi 0:098463de4c5d 71 __IO uint32_t rsvd3[6];
group-onsemi 0:098463de4c5d 72 __IO uint32_t burst_size[5];
group-onsemi 0:098463de4c5d 73 __IO uint32_t rsvd4[3];
group-onsemi 0:098463de4c5d 74 __IO uint32_t padding[192]; /* Offset to next channel */
group-onsemi 0:098463de4c5d 75 } mxc_pmu_bits_t;
group-onsemi 0:098463de4c5d 76
group-onsemi 0:098463de4c5d 77
group-onsemi 0:098463de4c5d 78 /*
group-onsemi 0:098463de4c5d 79 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
group-onsemi 0:098463de4c5d 80 access to each register in module.
group-onsemi 0:098463de4c5d 81 */
group-onsemi 0:098463de4c5d 82
group-onsemi 0:098463de4c5d 83 /* Offset Register Description
group-onsemi 0:098463de4c5d 84 ============= ============================================================================ */
group-onsemi 0:098463de4c5d 85 typedef struct {
group-onsemi 0:098463de4c5d 86 __IO uint32_t dscadr; /* 0x0000 PMU Channel Next Descriptor Address */
group-onsemi 0:098463de4c5d 87 __IO uint32_t cfg; /* 0x0004 PMU Channel Configuration */
group-onsemi 0:098463de4c5d 88 __IO uint32_t loop; /* 0x0008 PMU Channel Loop Counters */
group-onsemi 0:098463de4c5d 89 __IO uint32_t op; /* 0x000C PMU Channel Current Descriptor DWORD 0 [INTERNAL TEST ONLY] */
group-onsemi 0:098463de4c5d 90 __IO uint32_t dsc1; /* 0x0010 PMU Channel Current Descriptor DWORD 1 [INTERNAL TEST ONLY] */
group-onsemi 0:098463de4c5d 91 __IO uint32_t dsc2; /* 0x0014 PMU Channel Current Descriptor DWORD 2 [INTERNAL TEST ONLY] */
group-onsemi 0:098463de4c5d 92 __IO uint32_t dsc3; /* 0x0018 PMU Channel Current Descriptor DWORD 3 [INTERNAL TEST ONLY] */
group-onsemi 0:098463de4c5d 93 __IO uint32_t dsc4; /* 0x001C PMU Channel Current Descriptor DWORD 4 [INTERNAL TEST ONLY] */
group-onsemi 0:098463de4c5d 94 } mxc_pmu_regs_t;
group-onsemi 0:098463de4c5d 95
group-onsemi 0:098463de4c5d 96
group-onsemi 0:098463de4c5d 97 /*
group-onsemi 0:098463de4c5d 98 Register offsets for module PMU.
group-onsemi 0:098463de4c5d 99 */
group-onsemi 0:098463de4c5d 100
group-onsemi 0:098463de4c5d 101 #define MXC_R_PMU_OFFS_DSCADR ((uint32_t)0x00000000UL)
group-onsemi 0:098463de4c5d 102 #define MXC_R_PMU_OFFS_CFG ((uint32_t)0x00000004UL)
group-onsemi 0:098463de4c5d 103 #define MXC_R_PMU_OFFS_LOOP ((uint32_t)0x00000008UL)
group-onsemi 0:098463de4c5d 104 #define MXC_R_PMU_OFFS_OP ((uint32_t)0x0000000CUL)
group-onsemi 0:098463de4c5d 105 #define MXC_R_PMU_OFFS_DSC1 ((uint32_t)0x00000010UL)
group-onsemi 0:098463de4c5d 106 #define MXC_R_PMU_OFFS_DSC2 ((uint32_t)0x00000014UL)
group-onsemi 0:098463de4c5d 107 #define MXC_R_PMU_OFFS_DSC3 ((uint32_t)0x00000018UL)
group-onsemi 0:098463de4c5d 108 #define MXC_R_PMU_OFFS_DSC4 ((uint32_t)0x0000001CUL)
group-onsemi 0:098463de4c5d 109
group-onsemi 0:098463de4c5d 110
group-onsemi 0:098463de4c5d 111 /*
group-onsemi 0:098463de4c5d 112 Field positions and masks for module PMU.
group-onsemi 0:098463de4c5d 113 */
group-onsemi 0:098463de4c5d 114
group-onsemi 0:098463de4c5d 115 #define MXC_F_PMU_CFG_ENABLE_POS 0
group-onsemi 0:098463de4c5d 116 #define MXC_F_PMU_CFG_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS))
group-onsemi 0:098463de4c5d 117 #define MXC_F_PMU_CFG_LL_STOPPED_POS 2
group-onsemi 0:098463de4c5d 118 #define MXC_F_PMU_CFG_LL_STOPPED ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS))
group-onsemi 0:098463de4c5d 119 #define MXC_F_PMU_CFG_MANUAL_POS 3
group-onsemi 0:098463de4c5d 120 #define MXC_F_PMU_CFG_MANUAL ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS))
group-onsemi 0:098463de4c5d 121 #define MXC_F_PMU_CFG_BUS_ERROR_POS 4
group-onsemi 0:098463de4c5d 122 #define MXC_F_PMU_CFG_BUS_ERROR ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS))
group-onsemi 0:098463de4c5d 123 #define MXC_F_PMU_CFG_TO_STAT_POS 6
group-onsemi 0:098463de4c5d 124 #define MXC_F_PMU_CFG_TO_STAT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS))
group-onsemi 0:098463de4c5d 125 #define MXC_F_PMU_CFG_TO_SEL_POS 11
group-onsemi 0:098463de4c5d 126 #define MXC_F_PMU_CFG_TO_SEL ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS))
group-onsemi 0:098463de4c5d 127 #define MXC_F_PMU_CFG_PS_SEL_POS 14
group-onsemi 0:098463de4c5d 128 #define MXC_F_PMU_CFG_PS_SEL ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS))
group-onsemi 0:098463de4c5d 129 #define MXC_F_PMU_CFG_INTERRUPT_POS 16
group-onsemi 0:098463de4c5d 130 #define MXC_F_PMU_CFG_INTERRUPT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS))
group-onsemi 0:098463de4c5d 131 #define MXC_F_PMU_CFG_INT_EN_POS 17
group-onsemi 0:098463de4c5d 132 #define MXC_F_PMU_CFG_INT_EN ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS))
group-onsemi 0:098463de4c5d 133 #define MXC_F_PMU_CFG_BURST_SIZE_POS 24
group-onsemi 0:098463de4c5d 134 #define MXC_F_PMU_CFG_BURST_SIZE ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS))
group-onsemi 0:098463de4c5d 135
group-onsemi 0:098463de4c5d 136 #define MXC_F_PMU_LOOP_COUNTER_0_POS 0
group-onsemi 0:098463de4c5d 137 #define MXC_F_PMU_LOOP_COUNTER_0 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS))
group-onsemi 0:098463de4c5d 138 #define MXC_F_PMU_LOOP_COUNTER_1_POS 16
group-onsemi 0:098463de4c5d 139 #define MXC_F_PMU_LOOP_COUNTER_1 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS))
group-onsemi 0:098463de4c5d 140
group-onsemi 0:098463de4c5d 141
group-onsemi 0:098463de4c5d 142
group-onsemi 0:098463de4c5d 143 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 144 }
group-onsemi 0:098463de4c5d 145 #endif
group-onsemi 0:098463de4c5d 146
group-onsemi 0:098463de4c5d 147 #endif /* _MXC_PMU_REGS_H_ */
group-onsemi 0:098463de4c5d 148