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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Maxim/TARGET_MAX32620/device/adc_regs.h@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #ifndef _MXC_ADC_REGS_H_
group-onsemi 0:098463de4c5d 35 #define _MXC_ADC_REGS_H_
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 38 extern "C" {
group-onsemi 0:098463de4c5d 39 #endif
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 #include <stdint.h>
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 /*
group-onsemi 0:098463de4c5d 44 If types are not defined elsewhere (CMSIS) define them here
group-onsemi 0:098463de4c5d 45 */
group-onsemi 0:098463de4c5d 46 #ifndef __IO
group-onsemi 0:098463de4c5d 47 #define __IO volatile
group-onsemi 0:098463de4c5d 48 #endif
group-onsemi 0:098463de4c5d 49 #ifndef __I
group-onsemi 0:098463de4c5d 50 #define __I volatile const
group-onsemi 0:098463de4c5d 51 #endif
group-onsemi 0:098463de4c5d 52 #ifndef __O
group-onsemi 0:098463de4c5d 53 #define __O volatile
group-onsemi 0:098463de4c5d 54 #endif
group-onsemi 0:098463de4c5d 55
group-onsemi 0:098463de4c5d 56
group-onsemi 0:098463de4c5d 57 /*
group-onsemi 0:098463de4c5d 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
group-onsemi 0:098463de4c5d 59 access to each register in module.
group-onsemi 0:098463de4c5d 60 */
group-onsemi 0:098463de4c5d 61
group-onsemi 0:098463de4c5d 62 /* Offset Register Description
group-onsemi 0:098463de4c5d 63 ============= ============================================================================ */
group-onsemi 0:098463de4c5d 64 typedef struct {
group-onsemi 0:098463de4c5d 65 __IO uint32_t ctrl; /* 0x0000 ADC Control */
group-onsemi 0:098463de4c5d 66 __IO uint32_t status; /* 0x0004 ADC Status */
group-onsemi 0:098463de4c5d 67 __IO uint32_t data; /* 0x0008 ADC Output Data */
group-onsemi 0:098463de4c5d 68 __IO uint32_t intr; /* 0x000C ADC Interrupt Control Register */
group-onsemi 0:098463de4c5d 69 __IO uint32_t limit[4]; /* 0x0010-0x001C ADC Limit 0..3 */
group-onsemi 0:098463de4c5d 70 __IO uint32_t afe_ctrl; /* 0x0020 AFE Control Register */
group-onsemi 0:098463de4c5d 71 __IO uint32_t ro_cal0; /* 0x0024 RO Trim Calibration Register 0 */
group-onsemi 0:098463de4c5d 72 __IO uint32_t ro_cal1; /* 0x0028 RO Trim Calibration Register 1 */
group-onsemi 0:098463de4c5d 73 __IO uint32_t ro_cal2; /* 0x002C RO Trim Calibration Register 2 */
group-onsemi 0:098463de4c5d 74 } mxc_adc_regs_t;
group-onsemi 0:098463de4c5d 75
group-onsemi 0:098463de4c5d 76
group-onsemi 0:098463de4c5d 77 /*
group-onsemi 0:098463de4c5d 78 Register offsets for module ADC.
group-onsemi 0:098463de4c5d 79 */
group-onsemi 0:098463de4c5d 80
group-onsemi 0:098463de4c5d 81 #define MXC_R_ADC_OFFS_CTRL ((uint32_t)0x00000000UL)
group-onsemi 0:098463de4c5d 82 #define MXC_R_ADC_OFFS_STATUS ((uint32_t)0x00000004UL)
group-onsemi 0:098463de4c5d 83 #define MXC_R_ADC_OFFS_DATA ((uint32_t)0x00000008UL)
group-onsemi 0:098463de4c5d 84 #define MXC_R_ADC_OFFS_INTR ((uint32_t)0x0000000CUL)
group-onsemi 0:098463de4c5d 85 #define MXC_R_ADC_OFFS_LIMIT0 ((uint32_t)0x00000010UL)
group-onsemi 0:098463de4c5d 86 #define MXC_R_ADC_OFFS_LIMIT1 ((uint32_t)0x00000014UL)
group-onsemi 0:098463de4c5d 87 #define MXC_R_ADC_OFFS_LIMIT2 ((uint32_t)0x00000018UL)
group-onsemi 0:098463de4c5d 88 #define MXC_R_ADC_OFFS_LIMIT3 ((uint32_t)0x0000001CUL)
group-onsemi 0:098463de4c5d 89 #define MXC_R_ADC_OFFS_AFE_CTRL ((uint32_t)0x00000020UL)
group-onsemi 0:098463de4c5d 90 #define MXC_R_ADC_OFFS_RO_CAL0 ((uint32_t)0x00000024UL)
group-onsemi 0:098463de4c5d 91 #define MXC_R_ADC_OFFS_RO_CAL1 ((uint32_t)0x00000028UL)
group-onsemi 0:098463de4c5d 92 #define MXC_R_ADC_OFFS_RO_CAL2 ((uint32_t)0x0000002CUL)
group-onsemi 0:098463de4c5d 93
group-onsemi 0:098463de4c5d 94
group-onsemi 0:098463de4c5d 95 /*
group-onsemi 0:098463de4c5d 96 Field positions and masks for module ADC.
group-onsemi 0:098463de4c5d 97 */
group-onsemi 0:098463de4c5d 98
group-onsemi 0:098463de4c5d 99 #define MXC_F_ADC_CTRL_CPU_ADC_START_POS 0
group-onsemi 0:098463de4c5d 100 #define MXC_F_ADC_CTRL_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_CPU_ADC_START_POS))
group-onsemi 0:098463de4c5d 101 #define MXC_F_ADC_CTRL_ADC_PU_POS 1
group-onsemi 0:098463de4c5d 102 #define MXC_F_ADC_CTRL_ADC_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_PU_POS))
group-onsemi 0:098463de4c5d 103 #define MXC_F_ADC_CTRL_BUF_PU_POS 2
group-onsemi 0:098463de4c5d 104 #define MXC_F_ADC_CTRL_BUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PU_POS))
group-onsemi 0:098463de4c5d 105 #define MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS 3
group-onsemi 0:098463de4c5d 106 #define MXC_F_ADC_CTRL_ADC_REFBUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS))
group-onsemi 0:098463de4c5d 107 #define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS 4
group-onsemi 0:098463de4c5d 108 #define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS))
group-onsemi 0:098463de4c5d 109 #define MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS 5
group-onsemi 0:098463de4c5d 110 #define MXC_F_ADC_CTRL_BUF_CHOP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS))
group-onsemi 0:098463de4c5d 111 #define MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS 6
group-onsemi 0:098463de4c5d 112 #define MXC_F_ADC_CTRL_BUF_PUMP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS))
group-onsemi 0:098463de4c5d 113 #define MXC_F_ADC_CTRL_BUF_BYPASS_POS 7
group-onsemi 0:098463de4c5d 114 #define MXC_F_ADC_CTRL_BUF_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_BYPASS_POS))
group-onsemi 0:098463de4c5d 115 #define MXC_F_ADC_CTRL_ADC_REFSCL_POS 8
group-onsemi 0:098463de4c5d 116 #define MXC_F_ADC_CTRL_ADC_REFSCL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSCL_POS))
group-onsemi 0:098463de4c5d 117 #define MXC_F_ADC_CTRL_ADC_SCALE_POS 9
group-onsemi 0:098463de4c5d 118 #define MXC_F_ADC_CTRL_ADC_SCALE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_SCALE_POS))
group-onsemi 0:098463de4c5d 119 #define MXC_F_ADC_CTRL_ADC_REFSEL_POS 10
group-onsemi 0:098463de4c5d 120 #define MXC_F_ADC_CTRL_ADC_REFSEL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSEL_POS))
group-onsemi 0:098463de4c5d 121 #define MXC_F_ADC_CTRL_ADC_CLK_EN_POS 11
group-onsemi 0:098463de4c5d 122 #define MXC_F_ADC_CTRL_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CLK_EN_POS))
group-onsemi 0:098463de4c5d 123 #define MXC_F_ADC_CTRL_ADC_CHSEL_POS 12
group-onsemi 0:098463de4c5d 124 #define MXC_F_ADC_CTRL_ADC_CHSEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL_ADC_CHSEL_POS))
group-onsemi 0:098463de4c5d 125 #define MXC_F_ADC_CTRL_ADC_XREF_POS 16
group-onsemi 0:098463de4c5d 126 #define MXC_F_ADC_CTRL_ADC_XREF ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_XREF_POS))
group-onsemi 0:098463de4c5d 127 #define MXC_F_ADC_CTRL_ADC_DATAALIGN_POS 17
group-onsemi 0:098463de4c5d 128 #define MXC_F_ADC_CTRL_ADC_DATAALIGN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_DATAALIGN_POS))
group-onsemi 0:098463de4c5d 129 #define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS 24
group-onsemi 0:098463de4c5d 130 #define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY ((uint32_t)(0x000000FFUL << MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS))
group-onsemi 0:098463de4c5d 131
group-onsemi 0:098463de4c5d 132 #define MXC_F_ADC_STATUS_ADC_ACTIVE_POS 0
group-onsemi 0:098463de4c5d 133 #define MXC_F_ADC_STATUS_ADC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_ACTIVE_POS))
group-onsemi 0:098463de4c5d 134 #define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS 1
group-onsemi 0:098463de4c5d 135 #define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS))
group-onsemi 0:098463de4c5d 136 #define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS 2
group-onsemi 0:098463de4c5d 137 #define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS))
group-onsemi 0:098463de4c5d 138 #define MXC_F_ADC_STATUS_ADC_OVERFLOW_POS 3
group-onsemi 0:098463de4c5d 139 #define MXC_F_ADC_STATUS_ADC_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_OVERFLOW_POS))
group-onsemi 0:098463de4c5d 140
group-onsemi 0:098463de4c5d 141 #define MXC_F_ADC_DATA_ADC_DATA_POS 0
group-onsemi 0:098463de4c5d 142 #define MXC_F_ADC_DATA_ADC_DATA ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_DATA_ADC_DATA_POS))
group-onsemi 0:098463de4c5d 143
group-onsemi 0:098463de4c5d 144 #define MXC_F_ADC_INTR_ADC_DONE_IE_POS 0
group-onsemi 0:098463de4c5d 145 #define MXC_F_ADC_INTR_ADC_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IE_POS))
group-onsemi 0:098463de4c5d 146 #define MXC_F_ADC_INTR_ADC_REF_READY_IE_POS 1
group-onsemi 0:098463de4c5d 147 #define MXC_F_ADC_INTR_ADC_REF_READY_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IE_POS))
group-onsemi 0:098463de4c5d 148 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS 2
group-onsemi 0:098463de4c5d 149 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS))
group-onsemi 0:098463de4c5d 150 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS 3
group-onsemi 0:098463de4c5d 151 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS))
group-onsemi 0:098463de4c5d 152 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS 4
group-onsemi 0:098463de4c5d 153 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS))
group-onsemi 0:098463de4c5d 154 #define MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS 5
group-onsemi 0:098463de4c5d 155 #define MXC_F_ADC_INTR_RO_CAL_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS))
group-onsemi 0:098463de4c5d 156 #define MXC_F_ADC_INTR_ADC_DONE_IF_POS 16
group-onsemi 0:098463de4c5d 157 #define MXC_F_ADC_INTR_ADC_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IF_POS))
group-onsemi 0:098463de4c5d 158 #define MXC_F_ADC_INTR_ADC_REF_READY_IF_POS 17
group-onsemi 0:098463de4c5d 159 #define MXC_F_ADC_INTR_ADC_REF_READY_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IF_POS))
group-onsemi 0:098463de4c5d 160 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS 18
group-onsemi 0:098463de4c5d 161 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS))
group-onsemi 0:098463de4c5d 162 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS 19
group-onsemi 0:098463de4c5d 163 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS))
group-onsemi 0:098463de4c5d 164 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS 20
group-onsemi 0:098463de4c5d 165 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS))
group-onsemi 0:098463de4c5d 166 #define MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS 21
group-onsemi 0:098463de4c5d 167 #define MXC_F_ADC_INTR_RO_CAL_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS))
group-onsemi 0:098463de4c5d 168 #define MXC_F_ADC_INTR_ADC_INT_PENDING_POS 22
group-onsemi 0:098463de4c5d 169 #define MXC_F_ADC_INTR_ADC_INT_PENDING ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_INT_PENDING_POS))
group-onsemi 0:098463de4c5d 170
group-onsemi 0:098463de4c5d 171 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS 0
group-onsemi 0:098463de4c5d 172 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS))
group-onsemi 0:098463de4c5d 173 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS 12
group-onsemi 0:098463de4c5d 174 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS))
group-onsemi 0:098463de4c5d 175 #define MXC_F_ADC_LIMIT0_CH_SEL_POS 24
group-onsemi 0:098463de4c5d 176 #define MXC_F_ADC_LIMIT0_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT0_CH_SEL_POS))
group-onsemi 0:098463de4c5d 177 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS 28
group-onsemi 0:098463de4c5d 178 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS))
group-onsemi 0:098463de4c5d 179 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS 29
group-onsemi 0:098463de4c5d 180 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS))
group-onsemi 0:098463de4c5d 181
group-onsemi 0:098463de4c5d 182 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS 0
group-onsemi 0:098463de4c5d 183 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS))
group-onsemi 0:098463de4c5d 184 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS 12
group-onsemi 0:098463de4c5d 185 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS))
group-onsemi 0:098463de4c5d 186 #define MXC_F_ADC_LIMIT1_CH_SEL_POS 24
group-onsemi 0:098463de4c5d 187 #define MXC_F_ADC_LIMIT1_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT1_CH_SEL_POS))
group-onsemi 0:098463de4c5d 188 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS 28
group-onsemi 0:098463de4c5d 189 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS))
group-onsemi 0:098463de4c5d 190 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS 29
group-onsemi 0:098463de4c5d 191 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS))
group-onsemi 0:098463de4c5d 192
group-onsemi 0:098463de4c5d 193 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS 0
group-onsemi 0:098463de4c5d 194 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS))
group-onsemi 0:098463de4c5d 195 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS 12
group-onsemi 0:098463de4c5d 196 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS))
group-onsemi 0:098463de4c5d 197 #define MXC_F_ADC_LIMIT2_CH_SEL_POS 24
group-onsemi 0:098463de4c5d 198 #define MXC_F_ADC_LIMIT2_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT2_CH_SEL_POS))
group-onsemi 0:098463de4c5d 199 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS 28
group-onsemi 0:098463de4c5d 200 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS))
group-onsemi 0:098463de4c5d 201 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS 29
group-onsemi 0:098463de4c5d 202 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS))
group-onsemi 0:098463de4c5d 203
group-onsemi 0:098463de4c5d 204 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS 0
group-onsemi 0:098463de4c5d 205 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS))
group-onsemi 0:098463de4c5d 206 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS 12
group-onsemi 0:098463de4c5d 207 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS))
group-onsemi 0:098463de4c5d 208 #define MXC_F_ADC_LIMIT3_CH_SEL_POS 24
group-onsemi 0:098463de4c5d 209 #define MXC_F_ADC_LIMIT3_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT3_CH_SEL_POS))
group-onsemi 0:098463de4c5d 210 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS 28
group-onsemi 0:098463de4c5d 211 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS))
group-onsemi 0:098463de4c5d 212 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS 29
group-onsemi 0:098463de4c5d 213 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS))
group-onsemi 0:098463de4c5d 214
group-onsemi 0:098463de4c5d 215 #define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS 8
group-onsemi 0:098463de4c5d 216 #define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS))
group-onsemi 0:098463de4c5d 217 #define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS 9
group-onsemi 0:098463de4c5d 218 #define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS))
group-onsemi 0:098463de4c5d 219
group-onsemi 0:098463de4c5d 220 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0
group-onsemi 0:098463de4c5d 221 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS))
group-onsemi 0:098463de4c5d 222 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1
group-onsemi 0:098463de4c5d 223 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS))
group-onsemi 0:098463de4c5d 224 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2
group-onsemi 0:098463de4c5d 225 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS))
group-onsemi 0:098463de4c5d 226 #define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS 4
group-onsemi 0:098463de4c5d 227 #define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS))
group-onsemi 0:098463de4c5d 228 #define MXC_F_ADC_RO_CAL0_DUMMY_POS 5
group-onsemi 0:098463de4c5d 229 #define MXC_F_ADC_RO_CAL0_DUMMY ((uint32_t)(0x00000007UL << MXC_F_ADC_RO_CAL0_DUMMY_POS))
group-onsemi 0:098463de4c5d 230 #define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8
group-onsemi 0:098463de4c5d 231 #define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS))
group-onsemi 0:098463de4c5d 232 #define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23
group-onsemi 0:098463de4c5d 233 #define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS))
group-onsemi 0:098463de4c5d 234
group-onsemi 0:098463de4c5d 235 #define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0
group-onsemi 0:098463de4c5d 236 #define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS))
group-onsemi 0:098463de4c5d 237 #define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10
group-onsemi 0:098463de4c5d 238 #define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS))
group-onsemi 0:098463de4c5d 239 #define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20
group-onsemi 0:098463de4c5d 240 #define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS))
group-onsemi 0:098463de4c5d 241
group-onsemi 0:098463de4c5d 242 #define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS 0
group-onsemi 0:098463de4c5d 243 #define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT ((uint32_t)(0x000000FFUL << MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS))
group-onsemi 0:098463de4c5d 244
group-onsemi 0:098463de4c5d 245
group-onsemi 0:098463de4c5d 246
group-onsemi 0:098463de4c5d 247 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 248 }
group-onsemi 0:098463de4c5d 249 #endif
group-onsemi 0:098463de4c5d 250
group-onsemi 0:098463de4c5d 251 #endif /* _MXC_ADC_REGS_H_ */
group-onsemi 0:098463de4c5d 252