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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Maxim/TARGET_MAX32600/device/pwrseq_regs.h@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #ifndef _MXC_PWRSEQ_REGS_H
group-onsemi 0:098463de4c5d 35 #define _MXC_PWRSEQ_REGS_H
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 38 extern "C" {
group-onsemi 0:098463de4c5d 39 #endif
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 #include <stdint.h>
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 /**
group-onsemi 0:098463de4c5d 44 * @file pwrseq_regs.h
group-onsemi 0:098463de4c5d 45 * @addtogroup pwrseq PWRSEQ
group-onsemi 0:098463de4c5d 46 * @{
group-onsemi 0:098463de4c5d 47 */
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49 /* Offset Register Description
group-onsemi 0:098463de4c5d 50 ====== ================================================= */
group-onsemi 0:098463de4c5d 51 typedef struct {
group-onsemi 0:098463de4c5d 52 __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */
group-onsemi 0:098463de4c5d 53 __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */
group-onsemi 0:098463de4c5d 54 __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */
group-onsemi 0:098463de4c5d 55 __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */
group-onsemi 0:098463de4c5d 56 __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 */
group-onsemi 0:098463de4c5d 57 __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */
group-onsemi 0:098463de4c5d 58 __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */
group-onsemi 0:098463de4c5d 59 __I uint32_t rsv001C; /* 0x001C */
group-onsemi 0:098463de4c5d 60 __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */
group-onsemi 0:098463de4c5d 61 __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */
group-onsemi 0:098463de4c5d 62 } mxc_pwrseq_regs_t;
group-onsemi 0:098463de4c5d 63
group-onsemi 0:098463de4c5d 64
group-onsemi 0:098463de4c5d 65 /*
group-onsemi 0:098463de4c5d 66 Register offsets for module PWRSEQ.
group-onsemi 0:098463de4c5d 67 */
group-onsemi 0:098463de4c5d 68 #define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL)
group-onsemi 0:098463de4c5d 69 #define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL)
group-onsemi 0:098463de4c5d 70 #define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL)
group-onsemi 0:098463de4c5d 71 #define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL)
group-onsemi 0:098463de4c5d 72 #define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL)
group-onsemi 0:098463de4c5d 73 #define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL)
group-onsemi 0:098463de4c5d 74 #define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL)
group-onsemi 0:098463de4c5d 75 #define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL)
group-onsemi 0:098463de4c5d 76 #define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL)
group-onsemi 0:098463de4c5d 77
group-onsemi 0:098463de4c5d 78
group-onsemi 0:098463de4c5d 79 /*
group-onsemi 0:098463de4c5d 80 Field positions and masks for module PWRSEQ.
group-onsemi 0:098463de4c5d 81 */
group-onsemi 0:098463de4c5d 82 #define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0
group-onsemi 0:098463de4c5d 83 #define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS))
group-onsemi 0:098463de4c5d 84 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1
group-onsemi 0:098463de4c5d 85 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS))
group-onsemi 0:098463de4c5d 86 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2
group-onsemi 0:098463de4c5d 87 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS))
group-onsemi 0:098463de4c5d 88 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS 3
group-onsemi 0:098463de4c5d 89 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS))
group-onsemi 0:098463de4c5d 90 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS 4
group-onsemi 0:098463de4c5d 91 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS))
group-onsemi 0:098463de4c5d 92 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS 5
group-onsemi 0:098463de4c5d 93 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS))
group-onsemi 0:098463de4c5d 94 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS 6
group-onsemi 0:098463de4c5d 95 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS))
group-onsemi 0:098463de4c5d 96 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7
group-onsemi 0:098463de4c5d 97 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS))
group-onsemi 0:098463de4c5d 98 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8
group-onsemi 0:098463de4c5d 99 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS))
group-onsemi 0:098463de4c5d 100 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9
group-onsemi 0:098463de4c5d 101 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS))
group-onsemi 0:098463de4c5d 102 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10
group-onsemi 0:098463de4c5d 103 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS))
group-onsemi 0:098463de4c5d 104 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11
group-onsemi 0:098463de4c5d 105 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS))
group-onsemi 0:098463de4c5d 106 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12
group-onsemi 0:098463de4c5d 107 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS))
group-onsemi 0:098463de4c5d 108 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS 13
group-onsemi 0:098463de4c5d 109 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS))
group-onsemi 0:098463de4c5d 110 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS 14
group-onsemi 0:098463de4c5d 111 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS))
group-onsemi 0:098463de4c5d 112 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS 15
group-onsemi 0:098463de4c5d 113 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS))
group-onsemi 0:098463de4c5d 114 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS 16
group-onsemi 0:098463de4c5d 115 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS))
group-onsemi 0:098463de4c5d 116 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17
group-onsemi 0:098463de4c5d 117 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS))
group-onsemi 0:098463de4c5d 118 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS 18
group-onsemi 0:098463de4c5d 119 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS))
group-onsemi 0:098463de4c5d 120 #define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS 19
group-onsemi 0:098463de4c5d 121 #define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS))
group-onsemi 0:098463de4c5d 122
group-onsemi 0:098463de4c5d 123 #define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS 0
group-onsemi 0:098463de4c5d 124 #define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS))
group-onsemi 0:098463de4c5d 125 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS 8
group-onsemi 0:098463de4c5d 126 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS))
group-onsemi 0:098463de4c5d 127 #define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS 9
group-onsemi 0:098463de4c5d 128 #define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS))
group-onsemi 0:098463de4c5d 129 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS 10
group-onsemi 0:098463de4c5d 130 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS))
group-onsemi 0:098463de4c5d 131 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS 11
group-onsemi 0:098463de4c5d 132 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS))
group-onsemi 0:098463de4c5d 133 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS 12
group-onsemi 0:098463de4c5d 134 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS))
group-onsemi 0:098463de4c5d 135 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS 13
group-onsemi 0:098463de4c5d 136 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS))
group-onsemi 0:098463de4c5d 137 #define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS 14
group-onsemi 0:098463de4c5d 138 #define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS))
group-onsemi 0:098463de4c5d 139
group-onsemi 0:098463de4c5d 140 #define MXC_F_PWRSEQ_REG2_PWR_RST3_POS 0
group-onsemi 0:098463de4c5d 141 #define MXC_F_PWRSEQ_REG2_PWR_RST3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_RST3_POS))
group-onsemi 0:098463de4c5d 142 #define MXC_F_PWRSEQ_REG2_PWR_W3_POS 5
group-onsemi 0:098463de4c5d 143 #define MXC_F_PWRSEQ_REG2_PWR_W3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W3_POS))
group-onsemi 0:098463de4c5d 144 #define MXC_F_PWRSEQ_REG2_PWR_W1_POS 10
group-onsemi 0:098463de4c5d 145 #define MXC_F_PWRSEQ_REG2_PWR_W1 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_POS))
group-onsemi 0:098463de4c5d 146 #define MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS 15
group-onsemi 0:098463de4c5d 147 #define MXC_F_PWRSEQ_REG2_PWR_W1_LOW ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS))
group-onsemi 0:098463de4c5d 148 #define MXC_F_PWRSEQ_REG2_PWR_WRTC_POS 20
group-onsemi 0:098463de4c5d 149 #define MXC_F_PWRSEQ_REG2_PWR_WRTC ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_WRTC_POS))
group-onsemi 0:098463de4c5d 150 #define MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS 25
group-onsemi 0:098463de4c5d 151 #define MXC_F_PWRSEQ_REG2_PWR_WVDDA3 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS))
group-onsemi 0:098463de4c5d 152
group-onsemi 0:098463de4c5d 153 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0
group-onsemi 0:098463de4c5d 154 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS))
group-onsemi 0:098463de4c5d 155 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS 3
group-onsemi 0:098463de4c5d 156 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS))
group-onsemi 0:098463de4c5d 157 #define MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS 5
group-onsemi 0:098463de4c5d 158 #define MXC_F_PWRSEQ_REG3_PWR_SVMSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS))
group-onsemi 0:098463de4c5d 159 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS 8
group-onsemi 0:098463de4c5d 160 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS))
group-onsemi 0:098463de4c5d 161 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS 10
group-onsemi 0:098463de4c5d 162 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS))
group-onsemi 0:098463de4c5d 163 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 13
group-onsemi 0:098463de4c5d 164 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS))
group-onsemi 0:098463de4c5d 165 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 15
group-onsemi 0:098463de4c5d 166 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS))
group-onsemi 0:098463de4c5d 167 #define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS 16
group-onsemi 0:098463de4c5d 168 #define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS))
group-onsemi 0:098463de4c5d 169 #define MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS 17
group-onsemi 0:098463de4c5d 170 #define MXC_F_PWRSEQ_REG3_PWR_BO_TC ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS))
group-onsemi 0:098463de4c5d 171
group-onsemi 0:098463de4c5d 172 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0
group-onsemi 0:098463de4c5d 173 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS))
group-onsemi 0:098463de4c5d 174 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1
group-onsemi 0:098463de4c5d 175 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS))
group-onsemi 0:098463de4c5d 176 #define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS 2
group-onsemi 0:098463de4c5d 177 #define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS))
group-onsemi 0:098463de4c5d 178 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3
group-onsemi 0:098463de4c5d 179 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS))
group-onsemi 0:098463de4c5d 180 #define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS 4
group-onsemi 0:098463de4c5d 181 #define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS))
group-onsemi 0:098463de4c5d 182 #define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS 5
group-onsemi 0:098463de4c5d 183 #define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS))
group-onsemi 0:098463de4c5d 184 #define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS 6
group-onsemi 0:098463de4c5d 185 #define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS))
group-onsemi 0:098463de4c5d 186
group-onsemi 0:098463de4c5d 187 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0
group-onsemi 0:098463de4c5d 188 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS))
group-onsemi 0:098463de4c5d 189 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS 6
group-onsemi 0:098463de4c5d 190 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8 ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS))
group-onsemi 0:098463de4c5d 191 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS 10
group-onsemi 0:098463de4c5d 192 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS))
group-onsemi 0:098463de4c5d 193 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS 15
group-onsemi 0:098463de4c5d 194 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF ((uint32_t)(0x0000007FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS))
group-onsemi 0:098463de4c5d 195
group-onsemi 0:098463de4c5d 196 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0
group-onsemi 0:098463de4c5d 197 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS))
group-onsemi 0:098463de4c5d 198 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3
group-onsemi 0:098463de4c5d 199 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS))
group-onsemi 0:098463de4c5d 200 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7
group-onsemi 0:098463de4c5d 201 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS))
group-onsemi 0:098463de4c5d 202
group-onsemi 0:098463de4c5d 203 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0
group-onsemi 0:098463de4c5d 204 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS))
group-onsemi 0:098463de4c5d 205 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1
group-onsemi 0:098463de4c5d 206 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS))
group-onsemi 0:098463de4c5d 207 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS 2
group-onsemi 0:098463de4c5d 208 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS))
group-onsemi 0:098463de4c5d 209 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS 3
group-onsemi 0:098463de4c5d 210 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS))
group-onsemi 0:098463de4c5d 211 #define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS 4
group-onsemi 0:098463de4c5d 212 #define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS))
group-onsemi 0:098463de4c5d 213 #define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS 5
group-onsemi 0:098463de4c5d 214 #define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS))
group-onsemi 0:098463de4c5d 215 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS 6
group-onsemi 0:098463de4c5d 216 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS))
group-onsemi 0:098463de4c5d 217 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS 7
group-onsemi 0:098463de4c5d 218 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS))
group-onsemi 0:098463de4c5d 219 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS 8
group-onsemi 0:098463de4c5d 220 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS))
group-onsemi 0:098463de4c5d 221 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS 9
group-onsemi 0:098463de4c5d 222 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS))
group-onsemi 0:098463de4c5d 223 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS 10
group-onsemi 0:098463de4c5d 224 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS))
group-onsemi 0:098463de4c5d 225 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS 11
group-onsemi 0:098463de4c5d 226 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS))
group-onsemi 0:098463de4c5d 227 #define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS 12
group-onsemi 0:098463de4c5d 228 #define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS))
group-onsemi 0:098463de4c5d 229 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 13
group-onsemi 0:098463de4c5d 230 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS))
group-onsemi 0:098463de4c5d 231 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 14
group-onsemi 0:098463de4c5d 232 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS))
group-onsemi 0:098463de4c5d 233 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 15
group-onsemi 0:098463de4c5d 234 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS))
group-onsemi 0:098463de4c5d 235 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 16
group-onsemi 0:098463de4c5d 236 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS))
group-onsemi 0:098463de4c5d 237 #define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS 17
group-onsemi 0:098463de4c5d 238 #define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS))
group-onsemi 0:098463de4c5d 239 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18
group-onsemi 0:098463de4c5d 240 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
group-onsemi 0:098463de4c5d 241 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19
group-onsemi 0:098463de4c5d 242 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
group-onsemi 0:098463de4c5d 243 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS 20
group-onsemi 0:098463de4c5d 244 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS))
group-onsemi 0:098463de4c5d 245 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS 21
group-onsemi 0:098463de4c5d 246 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS))
group-onsemi 0:098463de4c5d 247
group-onsemi 0:098463de4c5d 248 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1
group-onsemi 0:098463de4c5d 249 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS))
group-onsemi 0:098463de4c5d 250 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS 2
group-onsemi 0:098463de4c5d 251 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS))
group-onsemi 0:098463de4c5d 252 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS 3
group-onsemi 0:098463de4c5d 253 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS))
group-onsemi 0:098463de4c5d 254 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS 4
group-onsemi 0:098463de4c5d 255 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS))
group-onsemi 0:098463de4c5d 256 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS 5
group-onsemi 0:098463de4c5d 257 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS))
group-onsemi 0:098463de4c5d 258 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS 6
group-onsemi 0:098463de4c5d 259 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS))
group-onsemi 0:098463de4c5d 260 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS 7
group-onsemi 0:098463de4c5d 261 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS))
group-onsemi 0:098463de4c5d 262 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS 8
group-onsemi 0:098463de4c5d 263 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS))
group-onsemi 0:098463de4c5d 264 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS 9
group-onsemi 0:098463de4c5d 265 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS))
group-onsemi 0:098463de4c5d 266 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS 10
group-onsemi 0:098463de4c5d 267 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS))
group-onsemi 0:098463de4c5d 268 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS 11
group-onsemi 0:098463de4c5d 269 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS))
group-onsemi 0:098463de4c5d 270 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS 12
group-onsemi 0:098463de4c5d 271 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS))
group-onsemi 0:098463de4c5d 272 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 13
group-onsemi 0:098463de4c5d 273 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS))
group-onsemi 0:098463de4c5d 274 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 14
group-onsemi 0:098463de4c5d 275 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS))
group-onsemi 0:098463de4c5d 276 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 15
group-onsemi 0:098463de4c5d 277 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS))
group-onsemi 0:098463de4c5d 278 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 16
group-onsemi 0:098463de4c5d 279 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS))
group-onsemi 0:098463de4c5d 280 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS 17
group-onsemi 0:098463de4c5d 281 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS))
group-onsemi 0:098463de4c5d 282 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18
group-onsemi 0:098463de4c5d 283 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
group-onsemi 0:098463de4c5d 284 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19
group-onsemi 0:098463de4c5d 285 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
group-onsemi 0:098463de4c5d 286 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS 20
group-onsemi 0:098463de4c5d 287 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS))
group-onsemi 0:098463de4c5d 288 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS 21
group-onsemi 0:098463de4c5d 289 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS))
group-onsemi 0:098463de4c5d 290
group-onsemi 0:098463de4c5d 291 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 292 }
group-onsemi 0:098463de4c5d 293 #endif
group-onsemi 0:098463de4c5d 294
group-onsemi 0:098463de4c5d 295 /**
group-onsemi 0:098463de4c5d 296 * @}
group-onsemi 0:098463de4c5d 297 */
group-onsemi 0:098463de4c5d 298
group-onsemi 0:098463de4c5d 299 #endif /* _MXC_PWRSEQ_REGS_H */