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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_ublox/TARGET_HI2110/gpio_irq_api.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2016 u-blox
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16
group-onsemi 0:098463de4c5d 17 /* TODO: this needs testing */
group-onsemi 0:098463de4c5d 18
group-onsemi 0:098463de4c5d 19 #include <stddef.h>
group-onsemi 0:098463de4c5d 20 #include "cmsis.h"
group-onsemi 0:098463de4c5d 21
group-onsemi 0:098463de4c5d 22 #include "gpio_irq_api.h"
group-onsemi 0:098463de4c5d 23 #include "mbed_error.h"
group-onsemi 0:098463de4c5d 24
group-onsemi 0:098463de4c5d 25 /* ----------------------------------------------------------------
group-onsemi 0:098463de4c5d 26 * MACROS
group-onsemi 0:098463de4c5d 27 * ----------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 28
group-onsemi 0:098463de4c5d 29 /* ----------------------------------------------------------------
group-onsemi 0:098463de4c5d 30 * TYPES
group-onsemi 0:098463de4c5d 31 * ----------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 32
group-onsemi 0:098463de4c5d 33 /* ----------------------------------------------------------------
group-onsemi 0:098463de4c5d 34 * GLOBAL VARIABLES
group-onsemi 0:098463de4c5d 35 * ----------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 /* Each GPIO pin is given an ID, if the ID is 0 the pin can be ignored. */
group-onsemi 0:098463de4c5d 38 static uint8_t channel_ids[20] = {0};
group-onsemi 0:098463de4c5d 39 static gpio_irq_handler irq_handler;
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 static bool initialised = false;
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 /* ----------------------------------------------------------------
group-onsemi 0:098463de4c5d 44 * FUNCTION PROTOTYPES
group-onsemi 0:098463de4c5d 45 * ----------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 46
group-onsemi 0:098463de4c5d 47 /* ----------------------------------------------------------------
group-onsemi 0:098463de4c5d 48 * NON-API FUNCTIONS
group-onsemi 0:098463de4c5d 49 * ----------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 50
group-onsemi 0:098463de4c5d 51 void IRQ5_GPIO_Handler()
group-onsemi 0:098463de4c5d 52 {
group-onsemi 0:098463de4c5d 53 if (initialised) {
group-onsemi 0:098463de4c5d 54 for (uint8_t i = 0; i < sizeof (channel_ids) / sizeof (channel_ids[0]); i++) {
group-onsemi 0:098463de4c5d 55 uint8_t id = channel_ids[i];
group-onsemi 0:098463de4c5d 56 uint32_t mask = 1 << id;
group-onsemi 0:098463de4c5d 57
group-onsemi 0:098463de4c5d 58 if (id != 0) {
group-onsemi 0:098463de4c5d 59 if (GPIO_IRQ | mask) {
group-onsemi 0:098463de4c5d 60 if (GPIO_INT_RISE | mask) {
group-onsemi 0:098463de4c5d 61 irq_handler(id, IRQ_RISE);
group-onsemi 0:098463de4c5d 62 } else if (GPIO_INT_FALL | mask) {
group-onsemi 0:098463de4c5d 63 irq_handler(id, IRQ_FALL);
group-onsemi 0:098463de4c5d 64 }
group-onsemi 0:098463de4c5d 65 }
group-onsemi 0:098463de4c5d 66 }
group-onsemi 0:098463de4c5d 67 }
group-onsemi 0:098463de4c5d 68 }
group-onsemi 0:098463de4c5d 69
group-onsemi 0:098463de4c5d 70 /* Clear all the interrupt bits (rather than wasting time on
group-onsemi 0:098463de4c5d 71 * each individual one), or we might get stuck if a spurious
group-onsemi 0:098463de4c5d 72 * one should arrive. */
group-onsemi 0:098463de4c5d 73 GPIO_INT_CLR = 0xFFFFFFFF;
group-onsemi 0:098463de4c5d 74 }
group-onsemi 0:098463de4c5d 75
group-onsemi 0:098463de4c5d 76 /* ----------------------------------------------------------------
group-onsemi 0:098463de4c5d 77 * MBED API CALLS
group-onsemi 0:098463de4c5d 78 * ----------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 79
group-onsemi 0:098463de4c5d 80 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
group-onsemi 0:098463de4c5d 81 {
group-onsemi 0:098463de4c5d 82 bool return_value = -1;
group-onsemi 0:098463de4c5d 83
group-onsemi 0:098463de4c5d 84 if (initialised) {
group-onsemi 0:098463de4c5d 85 return_value = 0;
group-onsemi 0:098463de4c5d 86 } else {
group-onsemi 0:098463de4c5d 87 if (pin != NC) {
group-onsemi 0:098463de4c5d 88 MBED_ASSERT (pin < NUM_PINS);
group-onsemi 0:098463de4c5d 89
group-onsemi 0:098463de4c5d 90 irq_handler = handler;
group-onsemi 0:098463de4c5d 91 obj->ch = pin;
group-onsemi 0:098463de4c5d 92 channel_ids[pin] = id;
group-onsemi 0:098463de4c5d 93
group-onsemi 0:098463de4c5d 94 uint32_t mask = 1 << obj->ch;
group-onsemi 0:098463de4c5d 95
group-onsemi 0:098463de4c5d 96 /* Remove any existing setting */
group-onsemi 0:098463de4c5d 97 GPIO_INT_RISE_BITCLR &= ~mask;
group-onsemi 0:098463de4c5d 98 GPIO_INT_FALL_BITCLR &= ~mask;
group-onsemi 0:098463de4c5d 99 GPIO_INT_LOW_BITCLR &= ~mask;
group-onsemi 0:098463de4c5d 100 GPIO_INT_HIGH_BITCLR &= ~mask;
group-onsemi 0:098463de4c5d 101
group-onsemi 0:098463de4c5d 102 initialised = true;
group-onsemi 0:098463de4c5d 103 NVIC_EnableIRQ (GPIO_IRQn);
group-onsemi 0:098463de4c5d 104
group-onsemi 0:098463de4c5d 105 return_value = 0;
group-onsemi 0:098463de4c5d 106 }
group-onsemi 0:098463de4c5d 107 }
group-onsemi 0:098463de4c5d 108
group-onsemi 0:098463de4c5d 109 return return_value;
group-onsemi 0:098463de4c5d 110 }
group-onsemi 0:098463de4c5d 111
group-onsemi 0:098463de4c5d 112 void gpio_irq_free(gpio_irq_t *obj)
group-onsemi 0:098463de4c5d 113 {
group-onsemi 0:098463de4c5d 114 channel_ids[obj->ch] = 0;
group-onsemi 0:098463de4c5d 115 }
group-onsemi 0:098463de4c5d 116
group-onsemi 0:098463de4c5d 117 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
group-onsemi 0:098463de4c5d 118 {
group-onsemi 0:098463de4c5d 119 uint32_t mask = 1 << obj->ch;
group-onsemi 0:098463de4c5d 120
group-onsemi 0:098463de4c5d 121 if (enable) {
group-onsemi 0:098463de4c5d 122 if (event == IRQ_RISE) {
group-onsemi 0:098463de4c5d 123 GPIO_INT_RISE_BITSET |= mask;
group-onsemi 0:098463de4c5d 124 } else if (event == IRQ_FALL) {
group-onsemi 0:098463de4c5d 125 GPIO_INT_FALL_BITSET |= mask;
group-onsemi 0:098463de4c5d 126 }
group-onsemi 0:098463de4c5d 127 }
group-onsemi 0:098463de4c5d 128 else
group-onsemi 0:098463de4c5d 129 {
group-onsemi 0:098463de4c5d 130 if (event == IRQ_RISE) {
group-onsemi 0:098463de4c5d 131 GPIO_INT_RISE_BITSET &= ~mask;
group-onsemi 0:098463de4c5d 132 } else if (event == IRQ_FALL) {
group-onsemi 0:098463de4c5d 133 GPIO_INT_FALL_BITSET &= ~mask;
group-onsemi 0:098463de4c5d 134 }
group-onsemi 0:098463de4c5d 135 }
group-onsemi 0:098463de4c5d 136 }
group-onsemi 0:098463de4c5d 137
group-onsemi 0:098463de4c5d 138 void gpio_irq_enable(gpio_irq_t *obj)
group-onsemi 0:098463de4c5d 139 {
group-onsemi 0:098463de4c5d 140 (void) obj;
group-onsemi 0:098463de4c5d 141 NVIC_EnableIRQ (GPIO_IRQn);
group-onsemi 0:098463de4c5d 142 }
group-onsemi 0:098463de4c5d 143
group-onsemi 0:098463de4c5d 144 void gpio_irq_disable(gpio_irq_t *obj)
group-onsemi 0:098463de4c5d 145 {
group-onsemi 0:098463de4c5d 146 (void) obj;
group-onsemi 0:098463de4c5d 147 NVIC_DisableIRQ (GPIO_IRQn);
group-onsemi 0:098463de4c5d 148 }