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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_ublox/TARGET_HI2110/device/hi2110.h@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2016 u-blox
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16
group-onsemi 0:098463de4c5d 17 #ifndef HI2110_H
group-onsemi 0:098463de4c5d 18 #define HI2110_H
group-onsemi 0:098463de4c5d 19
group-onsemi 0:098463de4c5d 20 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 21 extern "C" {
group-onsemi 0:098463de4c5d 22 #endif
group-onsemi 0:098463de4c5d 23
group-onsemi 0:098463de4c5d 24 /******************************************************************************/
group-onsemi 0:098463de4c5d 25 /* Processor and Core Peripherals */
group-onsemi 0:098463de4c5d 26 /******************************************************************************/
group-onsemi 0:098463de4c5d 27
group-onsemi 0:098463de4c5d 28 /*
group-onsemi 0:098463de4c5d 29 * ==========================================================================
group-onsemi 0:098463de4c5d 30 * ---------- Interrupt Number Definition -----------------------------------
group-onsemi 0:098463de4c5d 31 * ==========================================================================
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 typedef enum IRQn
group-onsemi 0:098463de4c5d 35 {
group-onsemi 0:098463de4c5d 36 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
group-onsemi 0:098463de4c5d 37 Thread_mode = -16, /*!< 0 Thread mode */
group-onsemi 0:098463de4c5d 38 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
group-onsemi 0:098463de4c5d 39 HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */
group-onsemi 0:098463de4c5d 40 SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
group-onsemi 0:098463de4c5d 41 PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
group-onsemi 0:098463de4c5d 42 SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
group-onsemi 0:098463de4c5d 43
group-onsemi 0:098463de4c5d 44 /****** Device Specific Interrupt Numbers ********************************************************/
group-onsemi 0:098463de4c5d 45 RTC_IRQn = 0, /*!< RTC Interrupt */
group-onsemi 0:098463de4c5d 46 Timer_IRQn = 1, /*!< Timer Interrupt */
group-onsemi 0:098463de4c5d 47 Security_IRQn = 2, /*!< From Security Interrupt */
group-onsemi 0:098463de4c5d 48 Protocol_IRQn = 3, /*!< From Protocol Interrupt */
group-onsemi 0:098463de4c5d 49 Apps_IRQn = 4, /*!< Core Self Interrupt */
group-onsemi 0:098463de4c5d 50 GPIO_IRQn = 5, /*!< GPIO Interrupt */
group-onsemi 0:098463de4c5d 51 DMA_IRQn = 6, /*!< DMA Interrupt */
group-onsemi 0:098463de4c5d 52 UART0_IRQn = 7, /*!< UART0 Interrupt */
group-onsemi 0:098463de4c5d 53 UART1_IRQn = 8, /*!< UART1 Interrupt */
group-onsemi 0:098463de4c5d 54 SSP0_IRQn = 9, /*!< SPI0 Interrupt */
group-onsemi 0:098463de4c5d 55 SSP1_IRQn = 10, /*!< SPI1 Interrupt */
group-onsemi 0:098463de4c5d 56 PWM0_Inner_IRQn = 11, /*!< PW0 Inner Interrupt */
group-onsemi 0:098463de4c5d 57 PWM0_Outer_IRQn = 12, /*!< PW0 Outer Interrupt */
group-onsemi 0:098463de4c5d 58 PWM1_Inner_IRQn = 13, /*!< PW1 Inner Interrupt */
group-onsemi 0:098463de4c5d 59 PWM1_Outer_IRQn = 14, /*!< PW1 Outer Interrupt */
group-onsemi 0:098463de4c5d 60 I2C_IRQn = 15, /*!< I2C Interrupt */
group-onsemi 0:098463de4c5d 61 LPUART_IRQn = 16, /*!< Low Power UART Interrupt */
group-onsemi 0:098463de4c5d 62 CAP_IRQn = 17, /*!< CAP Interrupt */
group-onsemi 0:098463de4c5d 63 COMP_IRQn = 18, /*!< COMP Interrupt */
group-onsemi 0:098463de4c5d 64 EDGE_IRQn = 19, /*!< EDGE Interrupt */
group-onsemi 0:098463de4c5d 65 Pulse_SWD_IRQn = 23, /*!< SWD Pulse Interrupt */
group-onsemi 0:098463de4c5d 66
group-onsemi 0:098463de4c5d 67 } IRQn_Type;
group-onsemi 0:098463de4c5d 68
group-onsemi 0:098463de4c5d 69 /*
group-onsemi 0:098463de4c5d 70 * ==========================================================================
group-onsemi 0:098463de4c5d 71 * ----------- Processor and Core Peripheral Section ------------------------
group-onsemi 0:098463de4c5d 72 * ==========================================================================
group-onsemi 0:098463de4c5d 73 */
group-onsemi 0:098463de4c5d 74
group-onsemi 0:098463de4c5d 75 /* Configuration of the Cortex-M# Processor and Core Peripherals */
group-onsemi 0:098463de4c5d 76 #define __CM0_REV 0x0000 /*!< Core Revision r2p1 */
group-onsemi 0:098463de4c5d 77 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
group-onsemi 0:098463de4c5d 78 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
group-onsemi 0:098463de4c5d 79 #define __MPU_PRESENT 0 /*!< MPU present or not */
group-onsemi 0:098463de4c5d 80 #define __FPU_PRESENT 0 /*!< FPU present or not */
group-onsemi 0:098463de4c5d 81
group-onsemi 0:098463de4c5d 82 #include <core_cm0.h> /* Cortex-M# processor and core peripherals */
group-onsemi 0:098463de4c5d 83
group-onsemi 0:098463de4c5d 84 /******************************************************************************/
group-onsemi 0:098463de4c5d 85 /* Device Specific Peripheral registers structures */
group-onsemi 0:098463de4c5d 86 /******************************************************************************/
group-onsemi 0:098463de4c5d 87
group-onsemi 0:098463de4c5d 88 /* UART */
group-onsemi 0:098463de4c5d 89 typedef struct {
group-onsemi 0:098463de4c5d 90 uint32_t UARTDR;
group-onsemi 0:098463de4c5d 91 uint32_t UARTRSR;
group-onsemi 0:098463de4c5d 92 uint32_t res0;
group-onsemi 0:098463de4c5d 93 uint32_t res1;
group-onsemi 0:098463de4c5d 94 uint32_t res2;
group-onsemi 0:098463de4c5d 95 uint32_t res3;
group-onsemi 0:098463de4c5d 96 uint32_t UARTFR;
group-onsemi 0:098463de4c5d 97 uint32_t res4;
group-onsemi 0:098463de4c5d 98 uint32_t UARTILPR;
group-onsemi 0:098463de4c5d 99 uint32_t UARTIBRD; // Integer baud divider
group-onsemi 0:098463de4c5d 100 uint32_t UARTFBRD; // Fractional Baud divider
group-onsemi 0:098463de4c5d 101 uint32_t UARTLCR_H;
group-onsemi 0:098463de4c5d 102 uint32_t UARTCR;
group-onsemi 0:098463de4c5d 103 uint32_t UARTIFLS;
group-onsemi 0:098463de4c5d 104 uint32_t UARTIMSC;
group-onsemi 0:098463de4c5d 105 uint32_t UARTRIS;
group-onsemi 0:098463de4c5d 106 uint32_t UARTMIS;
group-onsemi 0:098463de4c5d 107 uint32_t UARTICR;
group-onsemi 0:098463de4c5d 108 uint32_t UARTDMACR;
group-onsemi 0:098463de4c5d 109 } uart_ctrl_t;
group-onsemi 0:098463de4c5d 110
group-onsemi 0:098463de4c5d 111 /******************************************************************************/
group-onsemi 0:098463de4c5d 112 /* Peripheral memory map */
group-onsemi 0:098463de4c5d 113 /******************************************************************************/
group-onsemi 0:098463de4c5d 114
group-onsemi 0:098463de4c5d 115 #define RTC_IRQ_TIME_LSBS (*(volatile uint32_t *)(0x40002000))
group-onsemi 0:098463de4c5d 116 #define RTC_IRQ_TIME_LSBS_BITSET (*(volatile uint32_t *)(0x40002400))
group-onsemi 0:098463de4c5d 117 #define RTC_IRQ_TIME_LSBS_BITCLR (*(volatile uint32_t *)(0x40002800))
group-onsemi 0:098463de4c5d 118 #define RTC_IRQ_TIME_LSBS_BITTOG (*(volatile uint32_t *)(0x40002C00))
group-onsemi 0:098463de4c5d 119 #define RTC_IRQ_TIME_MSBS (*(volatile uint32_t *)(0x40002004))
group-onsemi 0:098463de4c5d 120 #define RTC_IRQ_TIME_MSBS_BITSET (*(volatile uint32_t *)(0x40002404))
group-onsemi 0:098463de4c5d 121 #define RTC_IRQ_TIME_MSBS_BITCLR (*(volatile uint32_t *)(0x40002804))
group-onsemi 0:098463de4c5d 122 #define RTC_IRQ_TIME_MSBS_BITTOG (*(volatile uint32_t *)(0x40002C04))
group-onsemi 0:098463de4c5d 123 #define RTC_IRQ_CLR (*(volatile uint32_t *)(0x40002008))
group-onsemi 0:098463de4c5d 124 #define RTC_IRQ_CLR_BITSET (*(volatile uint32_t *)(0x40002408))
group-onsemi 0:098463de4c5d 125 #define RTC_IRQ_CLR_BITCLR (*(volatile uint32_t *)(0x40002808))
group-onsemi 0:098463de4c5d 126 #define RTC_IRQ_CLR_BITTOG (*(volatile uint32_t *)(0x40002C08))
group-onsemi 0:098463de4c5d 127 #define TIMER0_LOAD (*(volatile uint32_t *)(0x4000200C))
group-onsemi 0:098463de4c5d 128 #define TIMER0_LOAD_BITSET (*(volatile uint32_t *)(0x4000240C))
group-onsemi 0:098463de4c5d 129 #define TIMER0_LOAD_BITCLR (*(volatile uint32_t *)(0x4000280C))
group-onsemi 0:098463de4c5d 130 #define TIMER0_LOAD_BITTOG (*(volatile uint32_t *)(0x40002C0C))
group-onsemi 0:098463de4c5d 131 #define TIMER0_CTRL (*(volatile uint32_t *)(0x40002010))
group-onsemi 0:098463de4c5d 132 #define TIMER0_CTRL_BITSET (*(volatile uint32_t *)(0x40002410))
group-onsemi 0:098463de4c5d 133 #define TIMER0_CTRL_BITCLR (*(volatile uint32_t *)(0x40002810))
group-onsemi 0:098463de4c5d 134 #define TIMER0_CTRL_BITTOG (*(volatile uint32_t *)(0x40002C10))
group-onsemi 0:098463de4c5d 135 #define TIMER0_TIME (*(volatile uint32_t *)(0x40002014))
group-onsemi 0:098463de4c5d 136 #define ARM_IRQ_REG (*(volatile uint32_t *)(0x40002018))
group-onsemi 0:098463de4c5d 137 #define ARM_IRQ_REG_BITSET (*(volatile uint32_t *)(0x40002418))
group-onsemi 0:098463de4c5d 138 #define ARM_IRQ_REG_BITCLR (*(volatile uint32_t *)(0x40002818))
group-onsemi 0:098463de4c5d 139 #define ARM_IRQ_REG_BITTOG (*(volatile uint32_t *)(0x40002C18))
group-onsemi 0:098463de4c5d 140 #define PIO_FUNC0 (*(volatile uint32_t *)(0x4000201C))
group-onsemi 0:098463de4c5d 141 #define PIO_FUNC0_BITSET (*(volatile uint32_t *)(0x4000241C))
group-onsemi 0:098463de4c5d 142 #define PIO_FUNC0_BITCLR (*(volatile uint32_t *)(0x4000281C))
group-onsemi 0:098463de4c5d 143 #define PIO_FUNC0_BITTOG (*(volatile uint32_t *)(0x40002C1C))
group-onsemi 0:098463de4c5d 144 #define PIO_FUNC1 (*(volatile uint32_t *)(0x40002020))
group-onsemi 0:098463de4c5d 145 #define PIO_FUNC1_BITSET (*(volatile uint32_t *)(0x40002420))
group-onsemi 0:098463de4c5d 146 #define PIO_FUNC1_BITCLR (*(volatile uint32_t *)(0x40002820))
group-onsemi 0:098463de4c5d 147 #define PIO_FUNC1_BITTOG (*(volatile uint32_t *)(0x40002C20))
group-onsemi 0:098463de4c5d 148 #define PIO_FUNC2 (*(volatile uint32_t *)(0x40002024))
group-onsemi 0:098463de4c5d 149 #define PIO_FUNC2_BITSET (*(volatile uint32_t *)(0x40002424))
group-onsemi 0:098463de4c5d 150 #define PIO_FUNC2_BITCLR (*(volatile uint32_t *)(0x40002824))
group-onsemi 0:098463de4c5d 151 #define PIO_FUNC2_BITTOG (*(volatile uint32_t *)(0x40002C24))
group-onsemi 0:098463de4c5d 152 #define PIO_FUNC3 (*(volatile uint32_t *)(0x40002028))
group-onsemi 0:098463de4c5d 153 #define PIO_FUNC3_BITSET (*(volatile uint32_t *)(0x40002428))
group-onsemi 0:098463de4c5d 154 #define PIO_FUNC3_BITCLR (*(volatile uint32_t *)(0x40002828))
group-onsemi 0:098463de4c5d 155 #define PIO_FUNC3_BITTOG (*(volatile uint32_t *)(0x40002C28))
group-onsemi 0:098463de4c5d 156 #define PIO_FUNC4 (*(volatile uint32_t *)(0x4000202C))
group-onsemi 0:098463de4c5d 157 #define PIO_FUNC4_BITSET (*(volatile uint32_t *)(0x4000242C))
group-onsemi 0:098463de4c5d 158 #define PIO_FUNC4_BITCLR (*(volatile uint32_t *)(0x4000282C))
group-onsemi 0:098463de4c5d 159 #define PIO_FUNC4_BITTOG (*(volatile uint32_t *)(0x40002C2C))
group-onsemi 0:098463de4c5d 160 #define GPIO_DIR (*(volatile uint32_t *)(0x40002030))
group-onsemi 0:098463de4c5d 161 #define GPIO_DIR_BITSET (*(volatile uint32_t *)(0x40002430))
group-onsemi 0:098463de4c5d 162 #define GPIO_DIR_BITCLR (*(volatile uint32_t *)(0x40002830))
group-onsemi 0:098463de4c5d 163 #define GPIO_DIR_BITTOG (*(volatile uint32_t *)(0x40002C30))
group-onsemi 0:098463de4c5d 164 #define GPIO_OUT (*(volatile uint32_t *)(0x40002034))
group-onsemi 0:098463de4c5d 165 #define GPIO_OUT_BITSET (*(volatile uint32_t *)(0x40002434))
group-onsemi 0:098463de4c5d 166 #define GPIO_OUT_BITCLR (*(volatile uint32_t *)(0x40002834))
group-onsemi 0:098463de4c5d 167 #define GPIO_OUT_BITTOG (*(volatile uint32_t *)(0x40002C34))
group-onsemi 0:098463de4c5d 168 #define GPIO_DRIVE (*(volatile uint32_t *)(0x40002038))
group-onsemi 0:098463de4c5d 169 #define GPIO_DRIVE_BITSET (*(volatile uint32_t *)(0x40002438))
group-onsemi 0:098463de4c5d 170 #define GPIO_DRIVE_BITCLR (*(volatile uint32_t *)(0x40002838))
group-onsemi 0:098463de4c5d 171 #define GPIO_DRIVE_BITTOG (*(volatile uint32_t *)(0x40002C38))
group-onsemi 0:098463de4c5d 172 #define GPIO_PULLEN (*(volatile uint32_t *)(0x4000203C))
group-onsemi 0:098463de4c5d 173 #define GPIO_PULLEN_BITSET (*(volatile uint32_t *)(0x4000243C))
group-onsemi 0:098463de4c5d 174 #define GPIO_PULLEN_BITCLR (*(volatile uint32_t *)(0x4000283C))
group-onsemi 0:098463de4c5d 175 #define GPIO_PULLEN_BITTOG (*(volatile uint32_t *)(0x40002C3C))
group-onsemi 0:098463de4c5d 176 #define GPIO_INT_RISE (*(volatile uint32_t *)(0x40002040))
group-onsemi 0:098463de4c5d 177 #define GPIO_INT_RISE_BITSET (*(volatile uint32_t *)(0x40002440))
group-onsemi 0:098463de4c5d 178 #define GPIO_INT_RISE_BITCLR (*(volatile uint32_t *)(0x40002840))
group-onsemi 0:098463de4c5d 179 #define GPIO_INT_RISE_BITTOG (*(volatile uint32_t *)(0x40002C40))
group-onsemi 0:098463de4c5d 180 #define GPIO_INT_FALL (*(volatile uint32_t *)(0x40002044))
group-onsemi 0:098463de4c5d 181 #define GPIO_INT_FALL_BITSET (*(volatile uint32_t *)(0x40002444))
group-onsemi 0:098463de4c5d 182 #define GPIO_INT_FALL_BITCLR (*(volatile uint32_t *)(0x40002844))
group-onsemi 0:098463de4c5d 183 #define GPIO_INT_FALL_BITTOG (*(volatile uint32_t *)(0x40002C44))
group-onsemi 0:098463de4c5d 184 #define GPIO_INT_HIGH (*(volatile uint32_t *)(0x40002048))
group-onsemi 0:098463de4c5d 185 #define GPIO_INT_HIGH_BITSET (*(volatile uint32_t *)(0x40002448))
group-onsemi 0:098463de4c5d 186 #define GPIO_INT_HIGH_BITCLR (*(volatile uint32_t *)(0x40002848))
group-onsemi 0:098463de4c5d 187 #define GPIO_INT_HIGH_BITTOG (*(volatile uint32_t *)(0x40002C48))
group-onsemi 0:098463de4c5d 188 #define GPIO_INT_LOW (*(volatile uint32_t *)(0x4000204C))
group-onsemi 0:098463de4c5d 189 #define GPIO_INT_LOW_BITSET (*(volatile uint32_t *)(0x4000244C))
group-onsemi 0:098463de4c5d 190 #define GPIO_INT_LOW_BITCLR (*(volatile uint32_t *)(0x4000284C))
group-onsemi 0:098463de4c5d 191 #define GPIO_INT_LOW_BITTOG (*(volatile uint32_t *)(0x40002C4C))
group-onsemi 0:098463de4c5d 192 #define GPIO_INT_CLR (*(volatile uint32_t *)(0x40002050))
group-onsemi 0:098463de4c5d 193 #define GPIO_INT_CLR_BITSET (*(volatile uint32_t *)(0x40002450))
group-onsemi 0:098463de4c5d 194 #define GPIO_INT_CLR_BITCLR (*(volatile uint32_t *)(0x40002850))
group-onsemi 0:098463de4c5d 195 #define GPIO_INT_CLR_BITTOG (*(volatile uint32_t *)(0x40002C50))
group-onsemi 0:098463de4c5d 196 #define GPIO_VALUE (*(volatile uint32_t *)(0x40002054))
group-onsemi 0:098463de4c5d 197 #define GPIO_IRQ (*(volatile uint32_t *)(0x40002058))
group-onsemi 0:098463de4c5d 198 #define WDT_INTERVAL (*(volatile uint32_t *)(0x4000205C))
group-onsemi 0:098463de4c5d 199 #define WDT_INTERVAL_BITSET (*(volatile uint32_t *)(0x4000245C))
group-onsemi 0:098463de4c5d 200 #define WDT_INTERVAL_BITCLR (*(volatile uint32_t *)(0x4000285C))
group-onsemi 0:098463de4c5d 201 #define WDT_INTERVAL_BITTOG (*(volatile uint32_t *)(0x40002C5C))
group-onsemi 0:098463de4c5d 202 #define WDT_CTRL (*(volatile uint32_t *)(0x40002060))
group-onsemi 0:098463de4c5d 203 #define WDT_CTRL_BITSET (*(volatile uint32_t *)(0x40002460))
group-onsemi 0:098463de4c5d 204 #define WDT_CTRL_BITCLR (*(volatile uint32_t *)(0x40002860))
group-onsemi 0:098463de4c5d 205 #define WDT_CTRL_BITTOG (*(volatile uint32_t *)(0x40002C60))
group-onsemi 0:098463de4c5d 206 #define WDT_TIME (*(volatile uint32_t *)(0x40002064))
group-onsemi 0:098463de4c5d 207 #define RESET_CAUSE (*(volatile uint32_t *)(0x40002134))
group-onsemi 0:098463de4c5d 208 #define PWM0_CTRL (*(volatile uint32_t *)(0x40002068))
group-onsemi 0:098463de4c5d 209 #define PWM0_CTRL_BITSET (*(volatile uint32_t *)(0x40002468))
group-onsemi 0:098463de4c5d 210 #define PWM0_CTRL_BITCLR (*(volatile uint32_t *)(0x40002868))
group-onsemi 0:098463de4c5d 211 #define PWM0_CTRL_BITTOG (*(volatile uint32_t *)(0x40002C68))
group-onsemi 0:098463de4c5d 212 #define PWM0_COUNT (*(volatile uint32_t *)(0x4000206C))
group-onsemi 0:098463de4c5d 213 #define PWM0_COUNT_BITSET (*(volatile uint32_t *)(0x4000246C))
group-onsemi 0:098463de4c5d 214 #define PWM0_COUNT_BITCLR (*(volatile uint32_t *)(0x4000286C))
group-onsemi 0:098463de4c5d 215 #define PWM0_COUNT_BITTOG (*(volatile uint32_t *)(0x40002C6C))
group-onsemi 0:098463de4c5d 216 #define PWM1_CTRL (*(volatile uint32_t *)(0x40002070))
group-onsemi 0:098463de4c5d 217 #define PWM1_CTRL_BITSET (*(volatile uint32_t *)(0x40002470))
group-onsemi 0:098463de4c5d 218 #define PWM1_CTRL_BITCLR (*(volatile uint32_t *)(0x40002870))
group-onsemi 0:098463de4c5d 219 #define PWM1_CTRL_BITTOG (*(volatile uint32_t *)(0x40002C70))
group-onsemi 0:098463de4c5d 220 #define PWM1_COUNT (*(volatile uint32_t *)(0x40002074))
group-onsemi 0:098463de4c5d 221 #define PWM1_COUNT_BITSET (*(volatile uint32_t *)(0x40002474))
group-onsemi 0:098463de4c5d 222 #define PWM1_COUNT_BITCLR (*(volatile uint32_t *)(0x40002874))
group-onsemi 0:098463de4c5d 223 #define PWM1_COUNT_BITTOG (*(volatile uint32_t *)(0x40002C74))
group-onsemi 0:098463de4c5d 224 #define PWM_STATUS (*(volatile uint32_t *)(0x40002078))
group-onsemi 0:098463de4c5d 225 #define CLKEN_REG (*(volatile uint32_t *)(0x4000207C))
group-onsemi 0:098463de4c5d 226 #define CLKEN_REG_BITSET (*(volatile uint32_t *)(0x4000247C))
group-onsemi 0:098463de4c5d 227 #define CLKEN_REG_BITCLR (*(volatile uint32_t *)(0x4000287C))
group-onsemi 0:098463de4c5d 228 #define CLKEN_REG_BITTOG (*(volatile uint32_t *)(0x40002C7C))
group-onsemi 0:098463de4c5d 229 #define I2C_INTERRUPT_STATUS (*(volatile uint32_t *)(0x40002080))
group-onsemi 0:098463de4c5d 230 #define I2C_INTERRUPT_CLEAR (*(volatile uint32_t *)(0x40002084))
group-onsemi 0:098463de4c5d 231 #define I2C_INTERRUPT_CLEAR_BITSET (*(volatile uint32_t *)(0x40002484))
group-onsemi 0:098463de4c5d 232 #define I2C_INTERRUPT_CLEAR_BITCLR (*(volatile uint32_t *)(0x40002884))
group-onsemi 0:098463de4c5d 233 #define I2C_INTERRUPT_CLEAR_BITTOG (*(volatile uint32_t *)(0x40002C84))
group-onsemi 0:098463de4c5d 234 #define I2C_INTERRUPT_ENABLE (*(volatile uint32_t *)(0x40002088))
group-onsemi 0:098463de4c5d 235 #define I2C_INTERRUPT_ENABLE_BITSET (*(volatile uint32_t *)(0x40002488))
group-onsemi 0:098463de4c5d 236 #define I2C_INTERRUPT_ENABLE_BITCLR (*(volatile uint32_t *)(0x40002888))
group-onsemi 0:098463de4c5d 237 #define I2C_INTERRUPT_ENABLE_BITTOG (*(volatile uint32_t *)(0x40002C88))
group-onsemi 0:098463de4c5d 238 #define I2C_MODE (*(volatile uint32_t *)(0x4000208C))
group-onsemi 0:098463de4c5d 239 #define I2C_MODE_BITSET (*(volatile uint32_t *)(0x4000248C))
group-onsemi 0:098463de4c5d 240 #define I2C_MODE_BITCLR (*(volatile uint32_t *)(0x4000288C))
group-onsemi 0:098463de4c5d 241 #define I2C_MODE_BITTOG (*(volatile uint32_t *)(0x40002C8C))
group-onsemi 0:098463de4c5d 242 #define I2C_TX_DATA (*(volatile uint32_t *)(0x40002090))
group-onsemi 0:098463de4c5d 243 #define I2C_TX_DATA_BITSET (*(volatile uint32_t *)(0x40002490))
group-onsemi 0:098463de4c5d 244 #define I2C_TX_DATA_BITCLR (*(volatile uint32_t *)(0x40002890))
group-onsemi 0:098463de4c5d 245 #define I2C_TX_DATA_BITTOG (*(volatile uint32_t *)(0x40002C90))
group-onsemi 0:098463de4c5d 246 #define I2C_RX_DATA (*(volatile uint32_t *)(0x40002144))
group-onsemi 0:098463de4c5d 247 #define I2C_TX_RD_WRB (*(volatile uint32_t *)(0x40002094))
group-onsemi 0:098463de4c5d 248 #define I2C_TX_RD_WRB_BITSET (*(volatile uint32_t *)(0x40002494))
group-onsemi 0:098463de4c5d 249 #define I2C_TX_RD_WRB_BITCLR (*(volatile uint32_t *)(0x40002894))
group-onsemi 0:098463de4c5d 250 #define I2C_TX_RD_WRB_BITTOG (*(volatile uint32_t *)(0x40002C94))
group-onsemi 0:098463de4c5d 251 #define I2C_TX_NO_BYTES (*(volatile uint32_t *)(0x40002098))
group-onsemi 0:098463de4c5d 252 #define I2C_TX_NO_BYTES_BITSET (*(volatile uint32_t *)(0x40002498))
group-onsemi 0:098463de4c5d 253 #define I2C_TX_NO_BYTES_BITCLR (*(volatile uint32_t *)(0x40002898))
group-onsemi 0:098463de4c5d 254 #define I2C_TX_NO_BYTES_BITTOG (*(volatile uint32_t *)(0x40002C98))
group-onsemi 0:098463de4c5d 255 #define I2C_RX_NO_BYTES (*(volatile uint32_t *)(0x4000209C))
group-onsemi 0:098463de4c5d 256 #define I2C_RX_NO_BYTES_MASTER (*(volatile uint32_t *)(0x400020A0))
group-onsemi 0:098463de4c5d 257 #define I2C_RX_NO_BYTES_MASTER_BITSET (*(volatile uint32_t *)(0x400024A0))
group-onsemi 0:098463de4c5d 258 #define I2C_RX_NO_BYTES_MASTER_BITCLR (*(volatile uint32_t *)(0x400028A0))
group-onsemi 0:098463de4c5d 259 #define I2C_RX_NO_BYTES_MASTER_BITTOG (*(volatile uint32_t *)(0x40002CA0))
group-onsemi 0:098463de4c5d 260 #define I2C_GO (*(volatile uint32_t *)(0x400020A4))
group-onsemi 0:098463de4c5d 261 #define I2C_GO_BITSET (*(volatile uint32_t *)(0x400024A4))
group-onsemi 0:098463de4c5d 262 #define I2C_GO_BITCLR (*(volatile uint32_t *)(0x400028A4))
group-onsemi 0:098463de4c5d 263 #define I2C_GO_BITTOG (*(volatile uint32_t *)(0x40002CA4))
group-onsemi 0:098463de4c5d 264 #define I2C_RX_EARLY_THRESHOLD (*(volatile uint32_t *)(0x400020A8))
group-onsemi 0:098463de4c5d 265 #define I2C_RX_EARLY_THRESHOLD_BITSET (*(volatile uint32_t *)(0x400024A8))
group-onsemi 0:098463de4c5d 266 #define I2C_RX_EARLY_THRESHOLD_BITCLR (*(volatile uint32_t *)(0x400028A8))
group-onsemi 0:098463de4c5d 267 #define I2C_RX_EARLY_THRESHOLD_BITTOG (*(volatile uint32_t *)(0x40002CA8))
group-onsemi 0:098463de4c5d 268 #define I2C_RX_AUTO_NAG_BYTE_CNT (*(volatile uint32_t *)(0x400020AC))
group-onsemi 0:098463de4c5d 269 #define I2C_RX_AUTO_NAG_BYTE_CNT_BITSET (*(volatile uint32_t *)(0x400024AC))
group-onsemi 0:098463de4c5d 270 #define I2C_RX_AUTO_NAG_BYTE_CNT_BITCLR (*(volatile uint32_t *)(0x400028AC))
group-onsemi 0:098463de4c5d 271 #define I2C_RX_AUTO_NAG_BYTE_CNT_BITTOG (*(volatile uint32_t *)(0x40002CAC))
group-onsemi 0:098463de4c5d 272 #define I2C_HALF_TIME (*(volatile uint32_t *)(0x400020B0))
group-onsemi 0:098463de4c5d 273 #define I2C_HALF_TIME_BITSET (*(volatile uint32_t *)(0x400024B0))
group-onsemi 0:098463de4c5d 274 #define I2C_HALF_TIME_BITCLR (*(volatile uint32_t *)(0x400028B0))
group-onsemi 0:098463de4c5d 275 #define I2C_HALF_TIME_BITTOG (*(volatile uint32_t *)(0x40002CB0))
group-onsemi 0:098463de4c5d 276 #define I2C_ADDRESS (*(volatile uint32_t *)(0x400020B4))
group-onsemi 0:098463de4c5d 277 #define I2C_ADDRESS_BITSET (*(volatile uint32_t *)(0x400024B4))
group-onsemi 0:098463de4c5d 278 #define I2C_ADDRESS_BITCLR (*(volatile uint32_t *)(0x400028B4))
group-onsemi 0:098463de4c5d 279 #define I2C_ADDRESS_BITTOG (*(volatile uint32_t *)(0x40002CB4))
group-onsemi 0:098463de4c5d 280 #define I2C_ADDR_TYPE (*(volatile uint32_t *)(0x400020B8))
group-onsemi 0:098463de4c5d 281 #define I2C_ADDR_TYPE_BITSET (*(volatile uint32_t *)(0x400024B8))
group-onsemi 0:098463de4c5d 282 #define I2C_ADDR_TYPE_BITCLR (*(volatile uint32_t *)(0x400028B8))
group-onsemi 0:098463de4c5d 283 #define I2C_ADDR_TYPE_BITTOG (*(volatile uint32_t *)(0x40002CB8))
group-onsemi 0:098463de4c5d 284 #define I2C_SOFT_RESET (*(volatile uint32_t *)(0x400020BC))
group-onsemi 0:098463de4c5d 285 #define I2C_SOFT_RESET_BITSET (*(volatile uint32_t *)(0x400024BC))
group-onsemi 0:098463de4c5d 286 #define I2C_SOFT_RESET_BITCLR (*(volatile uint32_t *)(0x400028BC))
group-onsemi 0:098463de4c5d 287 #define I2C_SOFT_RESET_BITTOG (*(volatile uint32_t *)(0x40002CBC))
group-onsemi 0:098463de4c5d 288 #define I2C_SLAVE_RWB (*(volatile uint32_t *)(0x400020C0))
group-onsemi 0:098463de4c5d 289 #define I2C_MASTER_SM (*(volatile uint32_t *)(0x400020C4))
group-onsemi 0:098463de4c5d 290 #define I2C_SLAVE_SM (*(volatile uint32_t *)(0x400020C8))
group-onsemi 0:098463de4c5d 291 #define I2C_SLAVE_ENABLE (*(volatile uint32_t *)(0x400020CC))
group-onsemi 0:098463de4c5d 292 #define I2C_SLAVE_ENABLE_BITSET (*(volatile uint32_t *)(0x400024CC))
group-onsemi 0:098463de4c5d 293 #define I2C_SLAVE_ENABLE_BITCLR (*(volatile uint32_t *)(0x400028CC))
group-onsemi 0:098463de4c5d 294 #define I2C_SLAVE_ENABLE_BITTOG (*(volatile uint32_t *)(0x40002CCC))
group-onsemi 0:098463de4c5d 295 #define I2C_MASTER_SEND_RESTART (*(volatile uint32_t *)(0x400020D0))
group-onsemi 0:098463de4c5d 296 #define I2C_MASTER_SEND_RESTART_BITSET (*(volatile uint32_t *)(0x400024D0))
group-onsemi 0:098463de4c5d 297 #define I2C_MASTER_SEND_RESTART_BITCLR (*(volatile uint32_t *)(0x400028D0))
group-onsemi 0:098463de4c5d 298 #define I2C_MASTER_SEND_RESTART_BITTOG (*(volatile uint32_t *)(0x40002CD0))
group-onsemi 0:098463de4c5d 299 #define DMA_MUX (*(volatile uint32_t *)(0x400020D4))
group-onsemi 0:098463de4c5d 300 #define DMA_MUX_BITSET (*(volatile uint32_t *)(0x400024D4))
group-onsemi 0:098463de4c5d 301 #define DMA_MUX_BITCLR (*(volatile uint32_t *)(0x400028D4))
group-onsemi 0:098463de4c5d 302 #define DMA_MUX_BITTOG (*(volatile uint32_t *)(0x40002CD4))
group-onsemi 0:098463de4c5d 303 #define DMA_CTRL_STAT (*(volatile uint32_t *)(0x400020D8))
group-onsemi 0:098463de4c5d 304 #define COMP_CTRL (*(volatile uint32_t *)(0x400020DC))
group-onsemi 0:098463de4c5d 305 #define COMP_CTRL_BITSET (*(volatile uint32_t *)(0x400024DC))
group-onsemi 0:098463de4c5d 306 #define COMP_CTRL_BITCLR (*(volatile uint32_t *)(0x400028DC))
group-onsemi 0:098463de4c5d 307 #define COMP_CTRL_BITTOG (*(volatile uint32_t *)(0x40002CDC))
group-onsemi 0:098463de4c5d 308 #define COMP_STAT (*(volatile uint32_t *)(0x400020E0))
group-onsemi 0:098463de4c5d 309 #define LP_UART_CTRL (*(volatile uint32_t *)(0x400020E4))
group-onsemi 0:098463de4c5d 310 #define LP_UART_CTRL_BITSET (*(volatile uint32_t *)(0x400024E4))
group-onsemi 0:098463de4c5d 311 #define LP_UART_CTRL_BITCLR (*(volatile uint32_t *)(0x400028E4))
group-onsemi 0:098463de4c5d 312 #define LP_UART_CTRL_BITTOG (*(volatile uint32_t *)(0x40002CE4))
group-onsemi 0:098463de4c5d 313 #define LP_UART_STATUS (*(volatile uint32_t *)(0x400020E8))
group-onsemi 0:098463de4c5d 314 #define LP_UART_DATA (*(volatile uint32_t *)(0x40002154))
group-onsemi 0:098463de4c5d 315 #define CAP_FILT_CONF (*(volatile uint32_t *)(0x400020EC))
group-onsemi 0:098463de4c5d 316 #define CAP_FILT_CONF_BITSET (*(volatile uint32_t *)(0x400024EC))
group-onsemi 0:098463de4c5d 317 #define CAP_FILT_CONF_BITCLR (*(volatile uint32_t *)(0x400028EC))
group-onsemi 0:098463de4c5d 318 #define CAP_FILT_CONF_BITTOG (*(volatile uint32_t *)(0x40002CEC))
group-onsemi 0:098463de4c5d 319 #define CAP_IRQ_CONF (*(volatile uint32_t *)(0x400020F0))
group-onsemi 0:098463de4c5d 320 #define CAP_IRQ_CONF_BITSET (*(volatile uint32_t *)(0x400024F0))
group-onsemi 0:098463de4c5d 321 #define CAP_IRQ_CONF_BITCLR (*(volatile uint32_t *)(0x400028F0))
group-onsemi 0:098463de4c5d 322 #define CAP_IRQ_CONF_BITTOG (*(volatile uint32_t *)(0x40002CF0))
group-onsemi 0:098463de4c5d 323 #define CAP_STATUS (*(volatile uint32_t *)(0x400020F4))
group-onsemi 0:098463de4c5d 324 #define CORE_ENABLE_SWD_ACCESS_APPS (*(volatile uint32_t *)(0x400020F8))
group-onsemi 0:098463de4c5d 325 #define CORE_ENABLE_SWD_ACCESS_APPS_BITSET (*(volatile uint32_t *)(0x400024F8))
group-onsemi 0:098463de4c5d 326 #define CORE_ENABLE_SWD_ACCESS_APPS_BITCLR (*(volatile uint32_t *)(0x400028F8))
group-onsemi 0:098463de4c5d 327 #define CORE_ENABLE_SWD_ACCESS_APPS_BITTOG (*(volatile uint32_t *)(0x40002CF8))
group-onsemi 0:098463de4c5d 328 #define APPS_DEBUGGER_TO_CORE_DATA (*(volatile uint32_t *)(0x400020FC))
group-onsemi 0:098463de4c5d 329 #define APPS_CORE_TO_DEBUGGER_DATA (*(volatile uint32_t *)(0x40002100))
group-onsemi 0:098463de4c5d 330 #define APPS_CORE_TO_DEBUGGER_DATA_BITSET (*(volatile uint32_t *)(0x40002500))
group-onsemi 0:098463de4c5d 331 #define APPS_CORE_TO_DEBUGGER_DATA_BITCLR (*(volatile uint32_t *)(0x40002900))
group-onsemi 0:098463de4c5d 332 #define APPS_CORE_TO_DEBUGGER_DATA_BITTOG (*(volatile uint32_t *)(0x40002D00))
group-onsemi 0:098463de4c5d 333 #define APPS_DEBUG_DATA_TO_CORE_AVAILABLE (*(volatile uint32_t *)(0x40002104))
group-onsemi 0:098463de4c5d 334 #define APPS_DEBUG_DATA_TO_CORE_ACCEPTED (*(volatile uint32_t *)(0x40002108))
group-onsemi 0:098463de4c5d 335 #define APPS_DEBUG_DATA_TO_CORE_ACCEPTED_BITSET (*(volatile uint32_t *)(0x40002508))
group-onsemi 0:098463de4c5d 336 #define APPS_DEBUG_DATA_TO_CORE_ACCEPTED_BITCLR (*(volatile uint32_t *)(0x40002908))
group-onsemi 0:098463de4c5d 337 #define APPS_DEBUG_DATA_TO_CORE_ACCEPTED_BITTOG (*(volatile uint32_t *)(0x40002D08))
group-onsemi 0:098463de4c5d 338 #define APPS_CORE_DATA_TO_DEBUGGER_AVAILABLE (*(volatile uint32_t *)(0x4000210C))
group-onsemi 0:098463de4c5d 339 #define APPS_CORE_DATA_TO_DEBUGGER_AVAILABLE_BITSET (*(volatile uint32_t *)(0x4000250C))
group-onsemi 0:098463de4c5d 340 #define APPS_CORE_DATA_TO_DEBUGGER_AVAILABLE_BITCLR (*(volatile uint32_t *)(0x4000290C))
group-onsemi 0:098463de4c5d 341 #define APPS_CORE_DATA_TO_DEBUGGER_AVAILABLE_BITTOG (*(volatile uint32_t *)(0x40002D0C))
group-onsemi 0:098463de4c5d 342 #define APPS_CORE_DATA_TO_DEBUGGER_ACCEPTED (*(volatile uint32_t *)(0x40002110))
group-onsemi 0:098463de4c5d 343 #define SWD_REQUEST (*(volatile uint32_t *)(0x40002114))
group-onsemi 0:098463de4c5d 344 #define EDGE_CTRL0 (*(volatile uint32_t *)(0x40002118))
group-onsemi 0:098463de4c5d 345 #define EDGE_CTRL0_BITSET (*(volatile uint32_t *)(0x40002518))
group-onsemi 0:098463de4c5d 346 #define EDGE_CTRL0_BITCLR (*(volatile uint32_t *)(0x40002918))
group-onsemi 0:098463de4c5d 347 #define EDGE_CTRL0_BITTOG (*(volatile uint32_t *)(0x40002D18))
group-onsemi 0:098463de4c5d 348 #define EDGE_CTRL1 (*(volatile uint32_t *)(0x4000211C))
group-onsemi 0:098463de4c5d 349 #define EDGE_CTRL1_BITSET (*(volatile uint32_t *)(0x4000251C))
group-onsemi 0:098463de4c5d 350 #define EDGE_CTRL1_BITCLR (*(volatile uint32_t *)(0x4000291C))
group-onsemi 0:098463de4c5d 351 #define EDGE_CTRL1_BITTOG (*(volatile uint32_t *)(0x40002D1C))
group-onsemi 0:098463de4c5d 352 #define EDGE_COUNT (*(volatile uint32_t *)(0x40002120))
group-onsemi 0:098463de4c5d 353 #define RESET_REG (*(volatile uint32_t *)(0x40002124))
group-onsemi 0:098463de4c5d 354 #define RESET_REG_BITSET (*(volatile uint32_t *)(0x40002524))
group-onsemi 0:098463de4c5d 355 #define RESET_REG_BITCLR (*(volatile uint32_t *)(0x40002924))
group-onsemi 0:098463de4c5d 356 #define RESET_REG_BITTOG (*(volatile uint32_t *)(0x40002D24))
group-onsemi 0:098463de4c5d 357 #define DIGITAL_VERSION (*(volatile uint32_t *)(0x40000000))
group-onsemi 0:098463de4c5d 358 #define CLK_FREQ_DAC (*(volatile uint32_t *)(0x40000004))
group-onsemi 0:098463de4c5d 359 #define CLK_FREQ_SET (*(volatile uint32_t *)(0x40000008))
group-onsemi 0:098463de4c5d 360 #define CLK_FREQ_SET_BITSET (*(volatile uint32_t *)(0x40000408))
group-onsemi 0:098463de4c5d 361 #define CLK_FREQ_SET_BITCLR (*(volatile uint32_t *)(0x40000808))
group-onsemi 0:098463de4c5d 362 #define CLK_FREQ_SET_BITTOG (*(volatile uint32_t *)(0x40000C08))
group-onsemi 0:098463de4c5d 363 #define CLK_FREQ_NREFCLKS (*(volatile uint32_t *)(0x4000000C))
group-onsemi 0:098463de4c5d 364 #define CLK_FREQ_NREFCLKS_BITSET (*(volatile uint32_t *)(0x4000040C))
group-onsemi 0:098463de4c5d 365 #define CLK_FREQ_NREFCLKS_BITCLR (*(volatile uint32_t *)(0x4000080C))
group-onsemi 0:098463de4c5d 366 #define CLK_FREQ_NREFCLKS_BITTOG (*(volatile uint32_t *)(0x40000C0C))
group-onsemi 0:098463de4c5d 367 #define CLK_FREQ_REF_SEL (*(volatile uint32_t *)(0x40000010))
group-onsemi 0:098463de4c5d 368 #define CLK_FREQ_REF_SEL_BITSET (*(volatile uint32_t *)(0x40000410))
group-onsemi 0:098463de4c5d 369 #define CLK_FREQ_REF_SEL_BITCLR (*(volatile uint32_t *)(0x40000810))
group-onsemi 0:098463de4c5d 370 #define CLK_FREQ_REF_SEL_BITTOG (*(volatile uint32_t *)(0x40000C10))
group-onsemi 0:098463de4c5d 371 #define CLK_FREQ_DIG_CLKS (*(volatile uint32_t *)(0x40000014))
group-onsemi 0:098463de4c5d 372 #define CLK_FREQ_HIGHTARGET (*(volatile uint32_t *)(0x40000018))
group-onsemi 0:098463de4c5d 373 #define CLK_FREQ_HIGHTARGET_BITSET (*(volatile uint32_t *)(0x40000418))
group-onsemi 0:098463de4c5d 374 #define CLK_FREQ_HIGHTARGET_BITCLR (*(volatile uint32_t *)(0x40000818))
group-onsemi 0:098463de4c5d 375 #define CLK_FREQ_HIGHTARGET_BITTOG (*(volatile uint32_t *)(0x40000C18))
group-onsemi 0:098463de4c5d 376 #define CLK_FREQ_LOWTARGET (*(volatile uint32_t *)(0x4000001C))
group-onsemi 0:098463de4c5d 377 #define CLK_FREQ_LOWTARGET_BITSET (*(volatile uint32_t *)(0x4000041C))
group-onsemi 0:098463de4c5d 378 #define CLK_FREQ_LOWTARGET_BITCLR (*(volatile uint32_t *)(0x4000081C))
group-onsemi 0:098463de4c5d 379 #define CLK_FREQ_LOWTARGET_BITTOG (*(volatile uint32_t *)(0x40000C1C))
group-onsemi 0:098463de4c5d 380 #define CLK_FREQ_LP_BACKOFF (*(volatile uint32_t *)(0x40000020))
group-onsemi 0:098463de4c5d 381 #define CLK_FREQ_LP_BACKOFF_BITSET (*(volatile uint32_t *)(0x40000420))
group-onsemi 0:098463de4c5d 382 #define CLK_FREQ_LP_BACKOFF_BITCLR (*(volatile uint32_t *)(0x40000820))
group-onsemi 0:098463de4c5d 383 #define CLK_FREQ_LP_BACKOFF_BITTOG (*(volatile uint32_t *)(0x40000C20))
group-onsemi 0:098463de4c5d 384 #define CLK_FREQ_ENABLE (*(volatile uint32_t *)(0x40000024))
group-onsemi 0:098463de4c5d 385 #define CLK_FREQ_ENABLE_BITSET (*(volatile uint32_t *)(0x40000424))
group-onsemi 0:098463de4c5d 386 #define CLK_FREQ_ENABLE_BITCLR (*(volatile uint32_t *)(0x40000824))
group-onsemi 0:098463de4c5d 387 #define CLK_FREQ_ENABLE_BITTOG (*(volatile uint32_t *)(0x40000C24))
group-onsemi 0:098463de4c5d 388 #define CLK_GATE_SYS (*(volatile uint32_t *)(0x40000028))
group-onsemi 0:098463de4c5d 389 #define CLK_GATE_SYS_BITSET (*(volatile uint32_t *)(0x40000428))
group-onsemi 0:098463de4c5d 390 #define CLK_GATE_SYS_BITCLR (*(volatile uint32_t *)(0x40000828))
group-onsemi 0:098463de4c5d 391 #define CLK_GATE_SYS_BITTOG (*(volatile uint32_t *)(0x40000C28))
group-onsemi 0:098463de4c5d 392 #define CLK_GATE_MODEM (*(volatile uint32_t *)(0x4000002C))
group-onsemi 0:098463de4c5d 393 #define CLK_GATE_MODEM_BITSET (*(volatile uint32_t *)(0x4000042C))
group-onsemi 0:098463de4c5d 394 #define CLK_GATE_MODEM_BITCLR (*(volatile uint32_t *)(0x4000082C))
group-onsemi 0:098463de4c5d 395 #define CLK_GATE_MODEM_BITTOG (*(volatile uint32_t *)(0x40000C2C))
group-onsemi 0:098463de4c5d 396 #define CLK_GATE_RADIO (*(volatile uint32_t *)(0x40000030))
group-onsemi 0:098463de4c5d 397 #define CLK_GATE_RADIO_BITSET (*(volatile uint32_t *)(0x40000430))
group-onsemi 0:098463de4c5d 398 #define CLK_GATE_RADIO_BITCLR (*(volatile uint32_t *)(0x40000830))
group-onsemi 0:098463de4c5d 399 #define CLK_GATE_RADIO_BITTOG (*(volatile uint32_t *)(0x40000C30))
group-onsemi 0:098463de4c5d 400 #define CLK_GATE_DEBUG (*(volatile uint32_t *)(0x40000034))
group-onsemi 0:098463de4c5d 401 #define CLK_GATE_DEBUG_BITSET (*(volatile uint32_t *)(0x40000434))
group-onsemi 0:098463de4c5d 402 #define CLK_GATE_DEBUG_BITCLR (*(volatile uint32_t *)(0x40000834))
group-onsemi 0:098463de4c5d 403 #define CLK_GATE_DEBUG_BITTOG (*(volatile uint32_t *)(0x40000C34))
group-onsemi 0:098463de4c5d 404 #define CLK_GATE_RBIST (*(volatile uint32_t *)(0x40000038))
group-onsemi 0:098463de4c5d 405 #define CLK_GATE_RBIST_BITSET (*(volatile uint32_t *)(0x40000438))
group-onsemi 0:098463de4c5d 406 #define CLK_GATE_RBIST_BITCLR (*(volatile uint32_t *)(0x40000838))
group-onsemi 0:098463de4c5d 407 #define CLK_GATE_RBIST_BITTOG (*(volatile uint32_t *)(0x40000C38))
group-onsemi 0:098463de4c5d 408 #define LPC_CTRL (*(volatile uint32_t *)(0x4000003C))
group-onsemi 0:098463de4c5d 409 #define LPC_CTRL_BITSET (*(volatile uint32_t *)(0x4000043C))
group-onsemi 0:098463de4c5d 410 #define LPC_CTRL_BITCLR (*(volatile uint32_t *)(0x4000083C))
group-onsemi 0:098463de4c5d 411 #define LPC_CTRL_BITTOG (*(volatile uint32_t *)(0x40000C3C))
group-onsemi 0:098463de4c5d 412 #define LPC_TEST (*(volatile uint32_t *)(0x40000040))
group-onsemi 0:098463de4c5d 413 #define LPC_TEST_BITSET (*(volatile uint32_t *)(0x40000440))
group-onsemi 0:098463de4c5d 414 #define LPC_TEST_BITCLR (*(volatile uint32_t *)(0x40000840))
group-onsemi 0:098463de4c5d 415 #define LPC_TEST_BITTOG (*(volatile uint32_t *)(0x40000C40))
group-onsemi 0:098463de4c5d 416 #define FPGA_FLASH_WR (*(volatile uint32_t *)(0x40000044))
group-onsemi 0:098463de4c5d 417 #define FPGA_FLASH_WR_BITSET (*(volatile uint32_t *)(0x40000444))
group-onsemi 0:098463de4c5d 418 #define FPGA_FLASH_WR_BITCLR (*(volatile uint32_t *)(0x40000844))
group-onsemi 0:098463de4c5d 419 #define FPGA_FLASH_WR_BITTOG (*(volatile uint32_t *)(0x40000C44))
group-onsemi 0:098463de4c5d 420 #define FPGA_FLASH_RD (*(volatile uint32_t *)(0x40000048))
group-onsemi 0:098463de4c5d 421 #define PMU_CTRL (*(volatile uint32_t *)(0x4000004C))
group-onsemi 0:098463de4c5d 422 #define PMU_CTRL_BITSET (*(volatile uint32_t *)(0x4000044C))
group-onsemi 0:098463de4c5d 423 #define PMU_CTRL_BITCLR (*(volatile uint32_t *)(0x4000084C))
group-onsemi 0:098463de4c5d 424 #define PMU_CTRL_BITTOG (*(volatile uint32_t *)(0x40000C4C))
group-onsemi 0:098463de4c5d 425 #define APP_CTRL0 (*(volatile uint32_t *)(0x40000050))
group-onsemi 0:098463de4c5d 426 #define APP_CTRL0_BITSET (*(volatile uint32_t *)(0x40000450))
group-onsemi 0:098463de4c5d 427 #define APP_CTRL0_BITCLR (*(volatile uint32_t *)(0x40000850))
group-onsemi 0:098463de4c5d 428 #define APP_CTRL0_BITTOG (*(volatile uint32_t *)(0x40000C50))
group-onsemi 0:098463de4c5d 429 #define APP_CTRL1 (*(volatile uint32_t *)(0x40000054))
group-onsemi 0:098463de4c5d 430 #define APP_CTRL1_BITSET (*(volatile uint32_t *)(0x40000454))
group-onsemi 0:098463de4c5d 431 #define APP_CTRL1_BITCLR (*(volatile uint32_t *)(0x40000854))
group-onsemi 0:098463de4c5d 432 #define APP_CTRL1_BITTOG (*(volatile uint32_t *)(0x40000C54))
group-onsemi 0:098463de4c5d 433 #define APP_CTRL2 (*(volatile uint32_t *)(0x40000058))
group-onsemi 0:098463de4c5d 434 #define APP_CTRL2_BITSET (*(volatile uint32_t *)(0x40000458))
group-onsemi 0:098463de4c5d 435 #define APP_CTRL2_BITCLR (*(volatile uint32_t *)(0x40000858))
group-onsemi 0:098463de4c5d 436 #define APP_CTRL2_BITTOG (*(volatile uint32_t *)(0x40000C58))
group-onsemi 0:098463de4c5d 437 #define APP_CTRL3 (*(volatile uint32_t *)(0x4000005C))
group-onsemi 0:098463de4c5d 438 #define APP_CTRL3_BITSET (*(volatile uint32_t *)(0x4000045C))
group-onsemi 0:098463de4c5d 439 #define APP_CTRL3_BITCLR (*(volatile uint32_t *)(0x4000085C))
group-onsemi 0:098463de4c5d 440 #define APP_CTRL3_BITTOG (*(volatile uint32_t *)(0x40000C5C))
group-onsemi 0:098463de4c5d 441 #define PMU_STAT (*(volatile uint32_t *)(0x40000060))
group-onsemi 0:098463de4c5d 442 #define PMUBIST_ADC_CONF (*(volatile uint32_t *)(0x40000064))
group-onsemi 0:098463de4c5d 443 #define PMUBIST_ADC_CONF_BITSET (*(volatile uint32_t *)(0x40000464))
group-onsemi 0:098463de4c5d 444 #define PMUBIST_ADC_CONF_BITCLR (*(volatile uint32_t *)(0x40000864))
group-onsemi 0:098463de4c5d 445 #define PMUBIST_ADC_CONF_BITTOG (*(volatile uint32_t *)(0x40000C64))
group-onsemi 0:098463de4c5d 446 #define PMUBIST_ADC_DATA (*(volatile uint32_t *)(0x40000068))
group-onsemi 0:098463de4c5d 447 #define STATUS (*(volatile uint32_t *)(0x4000006C))
group-onsemi 0:098463de4c5d 448 #define LPC_STATUS (*(volatile uint32_t *)(0x40000070))
group-onsemi 0:098463de4c5d 449 #define LPC_PDTIMER (*(volatile uint32_t *)(0x40000074))
group-onsemi 0:098463de4c5d 450 #define LPC_PDTIMER_BITSET (*(volatile uint32_t *)(0x40000474))
group-onsemi 0:098463de4c5d 451 #define LPC_PDTIMER_BITCLR (*(volatile uint32_t *)(0x40000874))
group-onsemi 0:098463de4c5d 452 #define LPC_PDTIMER_BITTOG (*(volatile uint32_t *)(0x40000C74))
group-onsemi 0:098463de4c5d 453 #define PIO_OWNER0 (*(volatile uint32_t *)(0x40000078))
group-onsemi 0:098463de4c5d 454 #define PIO_OWNER1 (*(volatile uint32_t *)(0x4000007C))
group-onsemi 0:098463de4c5d 455 #define RTC_TIME_LSBS (*(volatile uint32_t *)(0x40000080))
group-onsemi 0:098463de4c5d 456 #define RTC_TIME_MSBS (*(volatile uint32_t *)(0x40000084))
group-onsemi 0:098463de4c5d 457 #define DEBUG_SEL (*(volatile uint32_t *)(0x40000088))
group-onsemi 0:098463de4c5d 458 #define DEBUG_SEL_BITSET (*(volatile uint32_t *)(0x40000488))
group-onsemi 0:098463de4c5d 459 #define DEBUG_SEL_BITCLR (*(volatile uint32_t *)(0x40000888))
group-onsemi 0:098463de4c5d 460 #define DEBUG_SEL_BITTOG (*(volatile uint32_t *)(0x40000C88))
group-onsemi 0:098463de4c5d 461 #define FLASH_STATUS (*(volatile uint32_t *)(0x4000008C))
group-onsemi 0:098463de4c5d 462 #define CHIP_WDT_INTERVAL (*(volatile uint32_t *)(0x40000090))
group-onsemi 0:098463de4c5d 463 #define CHIP_WDT_INTERVAL_BITSET (*(volatile uint32_t *)(0x40000490))
group-onsemi 0:098463de4c5d 464 #define CHIP_WDT_INTERVAL_BITCLR (*(volatile uint32_t *)(0x40000890))
group-onsemi 0:098463de4c5d 465 #define CHIP_WDT_INTERVAL_BITTOG (*(volatile uint32_t *)(0x40000C90))
group-onsemi 0:098463de4c5d 466 #define CHIP_WDT_CTRL (*(volatile uint32_t *)(0x40000094))
group-onsemi 0:098463de4c5d 467 #define CHIP_WDT_CTRL_BITSET (*(volatile uint32_t *)(0x40000494))
group-onsemi 0:098463de4c5d 468 #define CHIP_WDT_CTRL_BITCLR (*(volatile uint32_t *)(0x40000894))
group-onsemi 0:098463de4c5d 469 #define CHIP_WDT_CTRL_BITTOG (*(volatile uint32_t *)(0x40000C94))
group-onsemi 0:098463de4c5d 470 #define CHIP_WDT_TIME (*(volatile uint32_t *)(0x40000098))
group-onsemi 0:098463de4c5d 471 #define CHIP_RESET (*(volatile uint32_t *)(0x4000009C))
group-onsemi 0:098463de4c5d 472 #define CHIP_RESET_BITSET (*(volatile uint32_t *)(0x4000049C))
group-onsemi 0:098463de4c5d 473 #define CHIP_RESET_BITCLR (*(volatile uint32_t *)(0x4000089C))
group-onsemi 0:098463de4c5d 474 #define CHIP_RESET_BITTOG (*(volatile uint32_t *)(0x40000C9C))
group-onsemi 0:098463de4c5d 475 #define SWD_PIN_CFG (*(volatile uint32_t *)(0x400000A0))
group-onsemi 0:098463de4c5d 476 #define SWD_PIN_CFG_BITSET (*(volatile uint32_t *)(0x400004A0))
group-onsemi 0:098463de4c5d 477 #define SWD_PIN_CFG_BITCLR (*(volatile uint32_t *)(0x400008A0))
group-onsemi 0:098463de4c5d 478 #define SWD_PIN_CFG_BITTOG (*(volatile uint32_t *)(0x40000CA0))
group-onsemi 0:098463de4c5d 479
group-onsemi 0:098463de4c5d 480 /******************************************************************************/
group-onsemi 0:098463de4c5d 481 /* Peripheral declaration */
group-onsemi 0:098463de4c5d 482 /******************************************************************************/
group-onsemi 0:098463de4c5d 483
group-onsemi 0:098463de4c5d 484 /* UART Defines */
group-onsemi 0:098463de4c5d 485 #define UART0_BASE 0x50003000
group-onsemi 0:098463de4c5d 486 #define UART1_BASE 0x50004000
group-onsemi 0:098463de4c5d 487
group-onsemi 0:098463de4c5d 488 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 489 }
group-onsemi 0:098463de4c5d 490 #endif
group-onsemi 0:098463de4c5d 491
group-onsemi 0:098463de4c5d 492 #endif /* HI2110_H */