ON Semiconductor / mbed-os

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg110f8.h@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /**************************************************************************//**
group-onsemi 0:098463de4c5d 2 * @file efm32zg110f8.h
group-onsemi 0:098463de4c5d 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
group-onsemi 0:098463de4c5d 4 * for EFM32ZG110F8
group-onsemi 0:098463de4c5d 5 * @version 5.0.0
group-onsemi 0:098463de4c5d 6 ******************************************************************************
group-onsemi 0:098463de4c5d 7 * @section License
group-onsemi 0:098463de4c5d 8 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
group-onsemi 0:098463de4c5d 9 ******************************************************************************
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * Permission is granted to anyone to use this software for any purpose,
group-onsemi 0:098463de4c5d 12 * including commercial applications, and to alter it and redistribute it
group-onsemi 0:098463de4c5d 13 * freely, subject to the following restrictions:
group-onsemi 0:098463de4c5d 14 *
group-onsemi 0:098463de4c5d 15 * 1. The origin of this software must not be misrepresented; you must not
group-onsemi 0:098463de4c5d 16 * claim that you wrote the original software.@n
group-onsemi 0:098463de4c5d 17 * 2. Altered source versions must be plainly marked as such, and must not be
group-onsemi 0:098463de4c5d 18 * misrepresented as being the original software.@n
group-onsemi 0:098463de4c5d 19 * 3. This notice may not be removed or altered from any source distribution.
group-onsemi 0:098463de4c5d 20 *
group-onsemi 0:098463de4c5d 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
group-onsemi 0:098463de4c5d 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
group-onsemi 0:098463de4c5d 23 * providing the Software "AS IS", with no express or implied warranties of any
group-onsemi 0:098463de4c5d 24 * kind, including, but not limited to, any implied warranties of
group-onsemi 0:098463de4c5d 25 * merchantability or fitness for any particular purpose or warranties against
group-onsemi 0:098463de4c5d 26 * infringement of any proprietary rights of a third party.
group-onsemi 0:098463de4c5d 27 *
group-onsemi 0:098463de4c5d 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
group-onsemi 0:098463de4c5d 29 * incidental, or special damages, or any other relief, or for any claim by
group-onsemi 0:098463de4c5d 30 * any third party, arising from your use of this Software.
group-onsemi 0:098463de4c5d 31 *
group-onsemi 0:098463de4c5d 32 *****************************************************************************/
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #ifndef EFM32ZG110F8_H
group-onsemi 0:098463de4c5d 35 #define EFM32ZG110F8_H
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 38 extern "C" {
group-onsemi 0:098463de4c5d 39 #endif
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 /**************************************************************************//**
group-onsemi 0:098463de4c5d 42 * @addtogroup Parts
group-onsemi 0:098463de4c5d 43 * @{
group-onsemi 0:098463de4c5d 44 *****************************************************************************/
group-onsemi 0:098463de4c5d 45
group-onsemi 0:098463de4c5d 46 /**************************************************************************//**
group-onsemi 0:098463de4c5d 47 * @defgroup EFM32ZG110F8 EFM32ZG110F8
group-onsemi 0:098463de4c5d 48 * @{
group-onsemi 0:098463de4c5d 49 *****************************************************************************/
group-onsemi 0:098463de4c5d 50
group-onsemi 0:098463de4c5d 51 /** Interrupt Number Definition */
group-onsemi 0:098463de4c5d 52 typedef enum IRQn
group-onsemi 0:098463de4c5d 53 {
group-onsemi 0:098463de4c5d 54 /****** Cortex-M0+ Processor Exceptions Numbers *****************************************/
group-onsemi 0:098463de4c5d 55 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M0+ Non Maskable Interrupt */
group-onsemi 0:098463de4c5d 56 HardFault_IRQn = -13, /*!< -13 Cortex-M0+ Hard Fault Interrupt */
group-onsemi 0:098463de4c5d 57 SVCall_IRQn = -5, /*!< -5 Cortex-M0+ SV Call Interrupt */
group-onsemi 0:098463de4c5d 58 PendSV_IRQn = -2, /*!< -2 Cortex-M0+ Pend SV Interrupt */
group-onsemi 0:098463de4c5d 59 SysTick_IRQn = -1, /*!< -1 Cortex-M0+ System Tick Interrupt */
group-onsemi 0:098463de4c5d 60
group-onsemi 0:098463de4c5d 61 /****** EFM32ZG Peripheral Interrupt Numbers ********************************************/
group-onsemi 0:098463de4c5d 62 DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
group-onsemi 0:098463de4c5d 63 GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
group-onsemi 0:098463de4c5d 64 TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
group-onsemi 0:098463de4c5d 65 ACMP0_IRQn = 3, /*!< 3 EFM32 ACMP0 Interrupt */
group-onsemi 0:098463de4c5d 66 ADC0_IRQn = 4, /*!< 4 EFM32 ADC0 Interrupt */
group-onsemi 0:098463de4c5d 67 I2C0_IRQn = 5, /*!< 5 EFM32 I2C0 Interrupt */
group-onsemi 0:098463de4c5d 68 GPIO_ODD_IRQn = 6, /*!< 6 EFM32 GPIO_ODD Interrupt */
group-onsemi 0:098463de4c5d 69 TIMER1_IRQn = 7, /*!< 7 EFM32 TIMER1 Interrupt */
group-onsemi 0:098463de4c5d 70 USART1_RX_IRQn = 8, /*!< 8 EFM32 USART1_RX Interrupt */
group-onsemi 0:098463de4c5d 71 USART1_TX_IRQn = 9, /*!< 9 EFM32 USART1_TX Interrupt */
group-onsemi 0:098463de4c5d 72 LEUART0_IRQn = 10, /*!< 10 EFM32 LEUART0 Interrupt */
group-onsemi 0:098463de4c5d 73 PCNT0_IRQn = 11, /*!< 11 EFM32 PCNT0 Interrupt */
group-onsemi 0:098463de4c5d 74 RTC_IRQn = 12, /*!< 12 EFM32 RTC Interrupt */
group-onsemi 0:098463de4c5d 75 CMU_IRQn = 13, /*!< 13 EFM32 CMU Interrupt */
group-onsemi 0:098463de4c5d 76 VCMP_IRQn = 14, /*!< 14 EFM32 VCMP Interrupt */
group-onsemi 0:098463de4c5d 77 MSC_IRQn = 15, /*!< 15 EFM32 MSC Interrupt */
group-onsemi 0:098463de4c5d 78 AES_IRQn = 16, /*!< 16 EFM32 AES Interrupt */
group-onsemi 0:098463de4c5d 79 } IRQn_Type;
group-onsemi 0:098463de4c5d 80
group-onsemi 0:098463de4c5d 81 /**************************************************************************//**
group-onsemi 0:098463de4c5d 82 * @defgroup EFM32ZG110F8_Core EFM32ZG110F8 Core
group-onsemi 0:098463de4c5d 83 * @{
group-onsemi 0:098463de4c5d 84 * @brief Processor and Core Peripheral Section
group-onsemi 0:098463de4c5d 85 *****************************************************************************/
group-onsemi 0:098463de4c5d 86 #define __MPU_PRESENT 0 /**< MPU not present */
group-onsemi 0:098463de4c5d 87 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
group-onsemi 0:098463de4c5d 88 #define __NVIC_PRIO_BITS 2 /**< NVIC interrupt priority bits */
group-onsemi 0:098463de4c5d 89 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
group-onsemi 0:098463de4c5d 90
group-onsemi 0:098463de4c5d 91 /** @} End of group EFM32ZG110F8_Core */
group-onsemi 0:098463de4c5d 92
group-onsemi 0:098463de4c5d 93 /**************************************************************************//**
group-onsemi 0:098463de4c5d 94 * @defgroup EFM32ZG110F8_Part EFM32ZG110F8 Part
group-onsemi 0:098463de4c5d 95 * @{
group-onsemi 0:098463de4c5d 96 ******************************************************************************/
group-onsemi 0:098463de4c5d 97
group-onsemi 0:098463de4c5d 98 /** Part family */
group-onsemi 0:098463de4c5d 99 #define _EFM32_ZERO_FAMILY 1 /**< Zero Gecko EFM32ZG MCU Family */
group-onsemi 0:098463de4c5d 100 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
group-onsemi 0:098463de4c5d 101 #define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
group-onsemi 0:098463de4c5d 102 #define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
group-onsemi 0:098463de4c5d 103 #define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
group-onsemi 0:098463de4c5d 104 #define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
group-onsemi 0:098463de4c5d 105
group-onsemi 0:098463de4c5d 106 /* If part number is not defined as compiler option, define it */
group-onsemi 0:098463de4c5d 107 #if !defined(EFM32ZG110F8)
group-onsemi 0:098463de4c5d 108 #define EFM32ZG110F8 1 /**< Zero Gecko Part */
group-onsemi 0:098463de4c5d 109 #endif
group-onsemi 0:098463de4c5d 110
group-onsemi 0:098463de4c5d 111 /** Configure part number */
group-onsemi 0:098463de4c5d 112 #define PART_NUMBER "EFM32ZG110F8" /**< Part Number */
group-onsemi 0:098463de4c5d 113
group-onsemi 0:098463de4c5d 114 /** Memory Base addresses and limits */
group-onsemi 0:098463de4c5d 115 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
group-onsemi 0:098463de4c5d 116 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
group-onsemi 0:098463de4c5d 117 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
group-onsemi 0:098463de4c5d 118 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
group-onsemi 0:098463de4c5d 119 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
group-onsemi 0:098463de4c5d 120 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
group-onsemi 0:098463de4c5d 121 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
group-onsemi 0:098463de4c5d 122 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
group-onsemi 0:098463de4c5d 123 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
group-onsemi 0:098463de4c5d 124 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
group-onsemi 0:098463de4c5d 125 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
group-onsemi 0:098463de4c5d 126 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
group-onsemi 0:098463de4c5d 127 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
group-onsemi 0:098463de4c5d 128 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
group-onsemi 0:098463de4c5d 129 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
group-onsemi 0:098463de4c5d 130 #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
group-onsemi 0:098463de4c5d 131 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
group-onsemi 0:098463de4c5d 132 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
group-onsemi 0:098463de4c5d 133 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
group-onsemi 0:098463de4c5d 134 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
group-onsemi 0:098463de4c5d 135
group-onsemi 0:098463de4c5d 136 /** Flash and SRAM limits for EFM32ZG110F8 */
group-onsemi 0:098463de4c5d 137 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
group-onsemi 0:098463de4c5d 138 #define FLASH_SIZE (0x00002000UL) /**< Available Flash Memory */
group-onsemi 0:098463de4c5d 139 #define FLASH_PAGE_SIZE 1024 /**< Flash Memory page size */
group-onsemi 0:098463de4c5d 140 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
group-onsemi 0:098463de4c5d 141 #define SRAM_SIZE (0x00000800UL) /**< Available SRAM Memory */
group-onsemi 0:098463de4c5d 142 #define __CM0PLUS_REV 0x001 /**< Cortex-M0+ Core revision r0p1 */
group-onsemi 0:098463de4c5d 143 #define PRS_CHAN_COUNT 4 /**< Number of PRS channels */
group-onsemi 0:098463de4c5d 144 #define DMA_CHAN_COUNT 4 /**< Number of DMA channels */
group-onsemi 0:098463de4c5d 145 #define EXT_IRQ_COUNT 19 /**< Number of External (NVIC) interrupts */
group-onsemi 0:098463de4c5d 146
group-onsemi 0:098463de4c5d 147 /** AF channels connect the different on-chip peripherals with the af-mux */
group-onsemi 0:098463de4c5d 148 #define AFCHAN_MAX 33
group-onsemi 0:098463de4c5d 149 #define AFCHANLOC_MAX 7
group-onsemi 0:098463de4c5d 150 /** Analog AF channels */
group-onsemi 0:098463de4c5d 151 #define AFACHAN_MAX 25
group-onsemi 0:098463de4c5d 152
group-onsemi 0:098463de4c5d 153 /* Part number capabilities */
group-onsemi 0:098463de4c5d 154
group-onsemi 0:098463de4c5d 155 #define TIMER_PRESENT /**< TIMER is available in this part */
group-onsemi 0:098463de4c5d 156 #define TIMER_COUNT 2 /**< 2 TIMERs available */
group-onsemi 0:098463de4c5d 157 #define ACMP_PRESENT /**< ACMP is available in this part */
group-onsemi 0:098463de4c5d 158 #define ACMP_COUNT 1 /**< 1 ACMPs available */
group-onsemi 0:098463de4c5d 159 #define USART_PRESENT /**< USART is available in this part */
group-onsemi 0:098463de4c5d 160 #define USART_COUNT 1 /**< 1 USARTs available */
group-onsemi 0:098463de4c5d 161 #define IDAC_PRESENT /**< IDAC is available in this part */
group-onsemi 0:098463de4c5d 162 #define IDAC_COUNT 1 /**< 1 IDACs available */
group-onsemi 0:098463de4c5d 163 #define ADC_PRESENT /**< ADC is available in this part */
group-onsemi 0:098463de4c5d 164 #define ADC_COUNT 1 /**< 1 ADCs available */
group-onsemi 0:098463de4c5d 165 #define LEUART_PRESENT /**< LEUART is available in this part */
group-onsemi 0:098463de4c5d 166 #define LEUART_COUNT 1 /**< 1 LEUARTs available */
group-onsemi 0:098463de4c5d 167 #define PCNT_PRESENT /**< PCNT is available in this part */
group-onsemi 0:098463de4c5d 168 #define PCNT_COUNT 1 /**< 1 PCNTs available */
group-onsemi 0:098463de4c5d 169 #define I2C_PRESENT /**< I2C is available in this part */
group-onsemi 0:098463de4c5d 170 #define I2C_COUNT 1 /**< 1 I2Cs available */
group-onsemi 0:098463de4c5d 171 #define AES_PRESENT
group-onsemi 0:098463de4c5d 172 #define AES_COUNT 1
group-onsemi 0:098463de4c5d 173 #define DMA_PRESENT
group-onsemi 0:098463de4c5d 174 #define DMA_COUNT 1
group-onsemi 0:098463de4c5d 175 #define LE_PRESENT
group-onsemi 0:098463de4c5d 176 #define LE_COUNT 1
group-onsemi 0:098463de4c5d 177 #define MSC_PRESENT
group-onsemi 0:098463de4c5d 178 #define MSC_COUNT 1
group-onsemi 0:098463de4c5d 179 #define EMU_PRESENT
group-onsemi 0:098463de4c5d 180 #define EMU_COUNT 1
group-onsemi 0:098463de4c5d 181 #define RMU_PRESENT
group-onsemi 0:098463de4c5d 182 #define RMU_COUNT 1
group-onsemi 0:098463de4c5d 183 #define CMU_PRESENT
group-onsemi 0:098463de4c5d 184 #define CMU_COUNT 1
group-onsemi 0:098463de4c5d 185 #define PRS_PRESENT
group-onsemi 0:098463de4c5d 186 #define PRS_COUNT 1
group-onsemi 0:098463de4c5d 187 #define GPIO_PRESENT
group-onsemi 0:098463de4c5d 188 #define GPIO_COUNT 1
group-onsemi 0:098463de4c5d 189 #define VCMP_PRESENT
group-onsemi 0:098463de4c5d 190 #define VCMP_COUNT 1
group-onsemi 0:098463de4c5d 191 #define RTC_PRESENT
group-onsemi 0:098463de4c5d 192 #define RTC_COUNT 1
group-onsemi 0:098463de4c5d 193 #define HFXTAL_PRESENT
group-onsemi 0:098463de4c5d 194 #define HFXTAL_COUNT 1
group-onsemi 0:098463de4c5d 195 #define LFXTAL_PRESENT
group-onsemi 0:098463de4c5d 196 #define LFXTAL_COUNT 1
group-onsemi 0:098463de4c5d 197 #define WDOG_PRESENT
group-onsemi 0:098463de4c5d 198 #define WDOG_COUNT 1
group-onsemi 0:098463de4c5d 199 #define DBG_PRESENT
group-onsemi 0:098463de4c5d 200 #define DBG_COUNT 1
group-onsemi 0:098463de4c5d 201 #define BOOTLOADER_PRESENT
group-onsemi 0:098463de4c5d 202 #define BOOTLOADER_COUNT 1
group-onsemi 0:098463de4c5d 203 #define ANALOG_PRESENT
group-onsemi 0:098463de4c5d 204 #define ANALOG_COUNT 1
group-onsemi 0:098463de4c5d 205
group-onsemi 0:098463de4c5d 206 /** @} End of group EFM32ZG110F8_Part */
group-onsemi 0:098463de4c5d 207
group-onsemi 0:098463de4c5d 208 #define ARM_MATH_CM0PLUS
group-onsemi 0:098463de4c5d 209 #include "arm_math.h" /* To get __CLZ definitions etc. */
group-onsemi 0:098463de4c5d 210 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
group-onsemi 0:098463de4c5d 211 #include "system_efm32zg.h" /* System Header */
group-onsemi 0:098463de4c5d 212
group-onsemi 0:098463de4c5d 213 /**************************************************************************//**
group-onsemi 0:098463de4c5d 214 * @defgroup EFM32ZG110F8_Peripheral_TypeDefs EFM32ZG110F8 Peripheral TypeDefs
group-onsemi 0:098463de4c5d 215 * @{
group-onsemi 0:098463de4c5d 216 * @brief Device Specific Peripheral Register Structures
group-onsemi 0:098463de4c5d 217 *****************************************************************************/
group-onsemi 0:098463de4c5d 218
group-onsemi 0:098463de4c5d 219 #include "efm32zg_aes.h"
group-onsemi 0:098463de4c5d 220 #include "efm32zg_dma_ch.h"
group-onsemi 0:098463de4c5d 221 #include "efm32zg_dma.h"
group-onsemi 0:098463de4c5d 222 #include "efm32zg_msc.h"
group-onsemi 0:098463de4c5d 223 #include "efm32zg_emu.h"
group-onsemi 0:098463de4c5d 224 #include "efm32zg_rmu.h"
group-onsemi 0:098463de4c5d 225 #include "efm32zg_cmu.h"
group-onsemi 0:098463de4c5d 226 #include "efm32zg_timer_cc.h"
group-onsemi 0:098463de4c5d 227 #include "efm32zg_timer.h"
group-onsemi 0:098463de4c5d 228 #include "efm32zg_acmp.h"
group-onsemi 0:098463de4c5d 229 #include "efm32zg_usart.h"
group-onsemi 0:098463de4c5d 230 #include "efm32zg_prs_ch.h"
group-onsemi 0:098463de4c5d 231 #include "efm32zg_prs.h"
group-onsemi 0:098463de4c5d 232 #include "efm32zg_idac.h"
group-onsemi 0:098463de4c5d 233 #include "efm32zg_gpio_p.h"
group-onsemi 0:098463de4c5d 234 #include "efm32zg_gpio.h"
group-onsemi 0:098463de4c5d 235 #include "efm32zg_vcmp.h"
group-onsemi 0:098463de4c5d 236 #include "efm32zg_adc.h"
group-onsemi 0:098463de4c5d 237 #include "efm32zg_leuart.h"
group-onsemi 0:098463de4c5d 238 #include "efm32zg_pcnt.h"
group-onsemi 0:098463de4c5d 239 #include "efm32zg_i2c.h"
group-onsemi 0:098463de4c5d 240 #include "efm32zg_rtc.h"
group-onsemi 0:098463de4c5d 241 #include "efm32zg_wdog.h"
group-onsemi 0:098463de4c5d 242 #include "efm32zg_dma_descriptor.h"
group-onsemi 0:098463de4c5d 243 #include "efm32zg_devinfo.h"
group-onsemi 0:098463de4c5d 244 #include "efm32zg_romtable.h"
group-onsemi 0:098463de4c5d 245 #include "efm32zg_calibrate.h"
group-onsemi 0:098463de4c5d 246
group-onsemi 0:098463de4c5d 247 /** @} End of group EFM32ZG110F8_Peripheral_TypeDefs */
group-onsemi 0:098463de4c5d 248
group-onsemi 0:098463de4c5d 249 /**************************************************************************//**
group-onsemi 0:098463de4c5d 250 * @defgroup EFM32ZG110F8_Peripheral_Base EFM32ZG110F8 Peripheral Memory Map
group-onsemi 0:098463de4c5d 251 * @{
group-onsemi 0:098463de4c5d 252 *****************************************************************************/
group-onsemi 0:098463de4c5d 253
group-onsemi 0:098463de4c5d 254 #define AES_BASE (0x400E0000UL) /**< AES base address */
group-onsemi 0:098463de4c5d 255 #define DMA_BASE (0x400C2000UL) /**< DMA base address */
group-onsemi 0:098463de4c5d 256 #define MSC_BASE (0x400C0000UL) /**< MSC base address */
group-onsemi 0:098463de4c5d 257 #define EMU_BASE (0x400C6000UL) /**< EMU base address */
group-onsemi 0:098463de4c5d 258 #define RMU_BASE (0x400CA000UL) /**< RMU base address */
group-onsemi 0:098463de4c5d 259 #define CMU_BASE (0x400C8000UL) /**< CMU base address */
group-onsemi 0:098463de4c5d 260 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
group-onsemi 0:098463de4c5d 261 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
group-onsemi 0:098463de4c5d 262 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
group-onsemi 0:098463de4c5d 263 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */
group-onsemi 0:098463de4c5d 264 #define PRS_BASE (0x400CC000UL) /**< PRS base address */
group-onsemi 0:098463de4c5d 265 #define IDAC0_BASE (0x40004000UL) /**< IDAC0 base address */
group-onsemi 0:098463de4c5d 266 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */
group-onsemi 0:098463de4c5d 267 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */
group-onsemi 0:098463de4c5d 268 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
group-onsemi 0:098463de4c5d 269 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
group-onsemi 0:098463de4c5d 270 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
group-onsemi 0:098463de4c5d 271 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
group-onsemi 0:098463de4c5d 272 #define RTC_BASE (0x40080000UL) /**< RTC base address */
group-onsemi 0:098463de4c5d 273 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */
group-onsemi 0:098463de4c5d 274 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
group-onsemi 0:098463de4c5d 275 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
group-onsemi 0:098463de4c5d 276 #define ROMTABLE_BASE (0xF00FFFD0UL) /**< ROMTABLE base address */
group-onsemi 0:098463de4c5d 277 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
group-onsemi 0:098463de4c5d 278 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
group-onsemi 0:098463de4c5d 279
group-onsemi 0:098463de4c5d 280 /** @} End of group EFM32ZG110F8_Peripheral_Base */
group-onsemi 0:098463de4c5d 281
group-onsemi 0:098463de4c5d 282 /**************************************************************************//**
group-onsemi 0:098463de4c5d 283 * @defgroup EFM32ZG110F8_Peripheral_Declaration EFM32ZG110F8 Peripheral Declarations
group-onsemi 0:098463de4c5d 284 * @{
group-onsemi 0:098463de4c5d 285 *****************************************************************************/
group-onsemi 0:098463de4c5d 286
group-onsemi 0:098463de4c5d 287 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
group-onsemi 0:098463de4c5d 288 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
group-onsemi 0:098463de4c5d 289 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
group-onsemi 0:098463de4c5d 290 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
group-onsemi 0:098463de4c5d 291 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
group-onsemi 0:098463de4c5d 292 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
group-onsemi 0:098463de4c5d 293 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
group-onsemi 0:098463de4c5d 294 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
group-onsemi 0:098463de4c5d 295 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
group-onsemi 0:098463de4c5d 296 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
group-onsemi 0:098463de4c5d 297 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
group-onsemi 0:098463de4c5d 298 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
group-onsemi 0:098463de4c5d 299 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
group-onsemi 0:098463de4c5d 300 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
group-onsemi 0:098463de4c5d 301 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
group-onsemi 0:098463de4c5d 302 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
group-onsemi 0:098463de4c5d 303 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
group-onsemi 0:098463de4c5d 304 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
group-onsemi 0:098463de4c5d 305 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
group-onsemi 0:098463de4c5d 306 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
group-onsemi 0:098463de4c5d 307 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
group-onsemi 0:098463de4c5d 308 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
group-onsemi 0:098463de4c5d 309 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
group-onsemi 0:098463de4c5d 310
group-onsemi 0:098463de4c5d 311 /** @} End of group EFM32ZG110F8_Peripheral_Declaration */
group-onsemi 0:098463de4c5d 312
group-onsemi 0:098463de4c5d 313 /**************************************************************************//**
group-onsemi 0:098463de4c5d 314 * @defgroup EFM32ZG110F8_BitFields EFM32ZG110F8 Bit Fields
group-onsemi 0:098463de4c5d 315 * @{
group-onsemi 0:098463de4c5d 316 *****************************************************************************/
group-onsemi 0:098463de4c5d 317
group-onsemi 0:098463de4c5d 318 #include "efm32zg_prs_signals.h"
group-onsemi 0:098463de4c5d 319 #include "efm32zg_dmareq.h"
group-onsemi 0:098463de4c5d 320 #include "efm32zg_dmactrl.h"
group-onsemi 0:098463de4c5d 321
group-onsemi 0:098463de4c5d 322 /**************************************************************************//**
group-onsemi 0:098463de4c5d 323 * @defgroup EFM32ZG110F8_UNLOCK EFM32ZG110F8 Unlock Codes
group-onsemi 0:098463de4c5d 324 * @{
group-onsemi 0:098463de4c5d 325 *****************************************************************************/
group-onsemi 0:098463de4c5d 326 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
group-onsemi 0:098463de4c5d 327 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
group-onsemi 0:098463de4c5d 328 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
group-onsemi 0:098463de4c5d 329 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
group-onsemi 0:098463de4c5d 330 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
group-onsemi 0:098463de4c5d 331
group-onsemi 0:098463de4c5d 332 /** @} End of group EFM32ZG110F8_UNLOCK */
group-onsemi 0:098463de4c5d 333
group-onsemi 0:098463de4c5d 334 /** @} End of group EFM32ZG110F8_BitFields */
group-onsemi 0:098463de4c5d 335
group-onsemi 0:098463de4c5d 336 /**************************************************************************//**
group-onsemi 0:098463de4c5d 337 * @defgroup EFM32ZG110F8_Alternate_Function EFM32ZG110F8 Alternate Function
group-onsemi 0:098463de4c5d 338 * @{
group-onsemi 0:098463de4c5d 339 *****************************************************************************/
group-onsemi 0:098463de4c5d 340
group-onsemi 0:098463de4c5d 341 #include "efm32zg_af_ports.h"
group-onsemi 0:098463de4c5d 342 #include "efm32zg_af_pins.h"
group-onsemi 0:098463de4c5d 343
group-onsemi 0:098463de4c5d 344 /** @} End of group EFM32ZG110F8_Alternate_Function */
group-onsemi 0:098463de4c5d 345
group-onsemi 0:098463de4c5d 346 /**************************************************************************//**
group-onsemi 0:098463de4c5d 347 * @brief Set the value of a bit field within a register.
group-onsemi 0:098463de4c5d 348 *
group-onsemi 0:098463de4c5d 349 * @param REG
group-onsemi 0:098463de4c5d 350 * The register to update
group-onsemi 0:098463de4c5d 351 * @param MASK
group-onsemi 0:098463de4c5d 352 * The mask for the bit field to update
group-onsemi 0:098463de4c5d 353 * @param VALUE
group-onsemi 0:098463de4c5d 354 * The value to write to the bit field
group-onsemi 0:098463de4c5d 355 * @param OFFSET
group-onsemi 0:098463de4c5d 356 * The number of bits that the field is offset within the register.
group-onsemi 0:098463de4c5d 357 * 0 (zero) means LSB.
group-onsemi 0:098463de4c5d 358 *****************************************************************************/
group-onsemi 0:098463de4c5d 359 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
group-onsemi 0:098463de4c5d 360 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
group-onsemi 0:098463de4c5d 361
group-onsemi 0:098463de4c5d 362 /** @} End of group EFM32ZG110F8 */
group-onsemi 0:098463de4c5d 363
group-onsemi 0:098463de4c5d 364 /** @} End of group Parts */
group-onsemi 0:098463de4c5d 365
group-onsemi 0:098463de4c5d 366 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 367 }
group-onsemi 0:098463de4c5d 368 #endif
group-onsemi 0:098463de4c5d 369 #endif /* EFM32ZG110F8_H */