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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_fmc.h@0:098463de4c5d, 2017-01-25 (annotated)
- Committer:
- group-onsemi
- Date:
- Wed Jan 25 20:34:15 2017 +0000
- Revision:
- 0:098463de4c5d
Initial commit
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| group-onsemi | 0:098463de4c5d | 1 | /** |
| group-onsemi | 0:098463de4c5d | 2 | ****************************************************************************** |
| group-onsemi | 0:098463de4c5d | 3 | * @file stm32l4xx_ll_fmc.h |
| group-onsemi | 0:098463de4c5d | 4 | * @author MCD Application Team |
| group-onsemi | 0:098463de4c5d | 5 | * @version V1.5.1 |
| group-onsemi | 0:098463de4c5d | 6 | * @date 31-May-2016 |
| group-onsemi | 0:098463de4c5d | 7 | * @brief Header file of FMC HAL module. |
| group-onsemi | 0:098463de4c5d | 8 | ****************************************************************************** |
| group-onsemi | 0:098463de4c5d | 9 | * @attention |
| group-onsemi | 0:098463de4c5d | 10 | * |
| group-onsemi | 0:098463de4c5d | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| group-onsemi | 0:098463de4c5d | 12 | * |
| group-onsemi | 0:098463de4c5d | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| group-onsemi | 0:098463de4c5d | 14 | * are permitted provided that the following conditions are met: |
| group-onsemi | 0:098463de4c5d | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| group-onsemi | 0:098463de4c5d | 16 | * this list of conditions and the following disclaimer. |
| group-onsemi | 0:098463de4c5d | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| group-onsemi | 0:098463de4c5d | 18 | * this list of conditions and the following disclaimer in the documentation |
| group-onsemi | 0:098463de4c5d | 19 | * and/or other materials provided with the distribution. |
| group-onsemi | 0:098463de4c5d | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| group-onsemi | 0:098463de4c5d | 21 | * may be used to endorse or promote products derived from this software |
| group-onsemi | 0:098463de4c5d | 22 | * without specific prior written permission. |
| group-onsemi | 0:098463de4c5d | 23 | * |
| group-onsemi | 0:098463de4c5d | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| group-onsemi | 0:098463de4c5d | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| group-onsemi | 0:098463de4c5d | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| group-onsemi | 0:098463de4c5d | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| group-onsemi | 0:098463de4c5d | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| group-onsemi | 0:098463de4c5d | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| group-onsemi | 0:098463de4c5d | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| group-onsemi | 0:098463de4c5d | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| group-onsemi | 0:098463de4c5d | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| group-onsemi | 0:098463de4c5d | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| group-onsemi | 0:098463de4c5d | 34 | * |
| group-onsemi | 0:098463de4c5d | 35 | ****************************************************************************** |
| group-onsemi | 0:098463de4c5d | 36 | */ |
| group-onsemi | 0:098463de4c5d | 37 | |
| group-onsemi | 0:098463de4c5d | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 39 | #ifndef __STM32L4xx_LL_FMC_H |
| group-onsemi | 0:098463de4c5d | 40 | #define __STM32L4xx_LL_FMC_H |
| group-onsemi | 0:098463de4c5d | 41 | |
| group-onsemi | 0:098463de4c5d | 42 | #ifdef __cplusplus |
| group-onsemi | 0:098463de4c5d | 43 | extern "C" { |
| group-onsemi | 0:098463de4c5d | 44 | #endif |
| group-onsemi | 0:098463de4c5d | 45 | |
| group-onsemi | 0:098463de4c5d | 46 | #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
| group-onsemi | 0:098463de4c5d | 47 | |
| group-onsemi | 0:098463de4c5d | 48 | /* Includes ------------------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 49 | #include "stm32l4xx_hal_def.h" |
| group-onsemi | 0:098463de4c5d | 50 | |
| group-onsemi | 0:098463de4c5d | 51 | /** @addtogroup STM32L4xx_HAL_Driver |
| group-onsemi | 0:098463de4c5d | 52 | * @{ |
| group-onsemi | 0:098463de4c5d | 53 | */ |
| group-onsemi | 0:098463de4c5d | 54 | |
| group-onsemi | 0:098463de4c5d | 55 | /** @addtogroup FMC_LL FMC Low Layer |
| group-onsemi | 0:098463de4c5d | 56 | * @{ |
| group-onsemi | 0:098463de4c5d | 57 | */ |
| group-onsemi | 0:098463de4c5d | 58 | |
| group-onsemi | 0:098463de4c5d | 59 | /** @addtogroup FMC_LL_Private_Macros FMC Low Layer Private Macros |
| group-onsemi | 0:098463de4c5d | 60 | * @{ |
| group-onsemi | 0:098463de4c5d | 61 | */ |
| group-onsemi | 0:098463de4c5d | 62 | #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ |
| group-onsemi | 0:098463de4c5d | 63 | ((__BANK__) == FMC_NORSRAM_BANK2) || \ |
| group-onsemi | 0:098463de4c5d | 64 | ((__BANK__) == FMC_NORSRAM_BANK3) || \ |
| group-onsemi | 0:098463de4c5d | 65 | ((__BANK__) == FMC_NORSRAM_BANK4)) |
| group-onsemi | 0:098463de4c5d | 66 | |
| group-onsemi | 0:098463de4c5d | 67 | |
| group-onsemi | 0:098463de4c5d | 68 | #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ |
| group-onsemi | 0:098463de4c5d | 69 | ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) |
| group-onsemi | 0:098463de4c5d | 70 | |
| group-onsemi | 0:098463de4c5d | 71 | |
| group-onsemi | 0:098463de4c5d | 72 | #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ |
| group-onsemi | 0:098463de4c5d | 73 | ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ |
| group-onsemi | 0:098463de4c5d | 74 | ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) |
| group-onsemi | 0:098463de4c5d | 75 | |
| group-onsemi | 0:098463de4c5d | 76 | #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ |
| group-onsemi | 0:098463de4c5d | 77 | ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ |
| group-onsemi | 0:098463de4c5d | 78 | ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) |
| group-onsemi | 0:098463de4c5d | 79 | |
| group-onsemi | 0:098463de4c5d | 80 | #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ |
| group-onsemi | 0:098463de4c5d | 81 | ((__SIZE__) == FMC_PAGE_SIZE_128) || \ |
| group-onsemi | 0:098463de4c5d | 82 | ((__SIZE__) == FMC_PAGE_SIZE_256) || \ |
| group-onsemi | 0:098463de4c5d | 83 | ((__SIZE__) == FMC_PAGE_SIZE_512) || \ |
| group-onsemi | 0:098463de4c5d | 84 | ((__SIZE__) == FMC_PAGE_SIZE_1024)) |
| group-onsemi | 0:098463de4c5d | 85 | |
| group-onsemi | 0:098463de4c5d | 86 | #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ |
| group-onsemi | 0:098463de4c5d | 87 | ((__BURST__) == FMC_WRITE_BURST_ENABLE)) |
| group-onsemi | 0:098463de4c5d | 88 | |
| group-onsemi | 0:098463de4c5d | 89 | #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ |
| group-onsemi | 0:098463de4c5d | 90 | ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) |
| group-onsemi | 0:098463de4c5d | 91 | |
| group-onsemi | 0:098463de4c5d | 92 | #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ |
| group-onsemi | 0:098463de4c5d | 93 | ((__MODE__) == FMC_ACCESS_MODE_B) || \ |
| group-onsemi | 0:098463de4c5d | 94 | ((__MODE__) == FMC_ACCESS_MODE_C) || \ |
| group-onsemi | 0:098463de4c5d | 95 | ((__MODE__) == FMC_ACCESS_MODE_D)) |
| group-onsemi | 0:098463de4c5d | 96 | |
| group-onsemi | 0:098463de4c5d | 97 | |
| group-onsemi | 0:098463de4c5d | 98 | #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) |
| group-onsemi | 0:098463de4c5d | 99 | |
| group-onsemi | 0:098463de4c5d | 100 | #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ |
| group-onsemi | 0:098463de4c5d | 101 | ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) |
| group-onsemi | 0:098463de4c5d | 102 | |
| group-onsemi | 0:098463de4c5d | 103 | #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ |
| group-onsemi | 0:098463de4c5d | 104 | ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) |
| group-onsemi | 0:098463de4c5d | 105 | |
| group-onsemi | 0:098463de4c5d | 106 | #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ |
| group-onsemi | 0:098463de4c5d | 107 | ((__STATE__) == FMC_NAND_ECC_ENABLE)) |
| group-onsemi | 0:098463de4c5d | 108 | |
| group-onsemi | 0:098463de4c5d | 109 | |
| group-onsemi | 0:098463de4c5d | 110 | #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ |
| group-onsemi | 0:098463de4c5d | 111 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ |
| group-onsemi | 0:098463de4c5d | 112 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ |
| group-onsemi | 0:098463de4c5d | 113 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ |
| group-onsemi | 0:098463de4c5d | 114 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ |
| group-onsemi | 0:098463de4c5d | 115 | ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) |
| group-onsemi | 0:098463de4c5d | 116 | |
| group-onsemi | 0:098463de4c5d | 117 | |
| group-onsemi | 0:098463de4c5d | 118 | /** @defgroup FMC_NORSRAM_Device_Instance FMC NOR/SRAM Device Instance |
| group-onsemi | 0:098463de4c5d | 119 | * @{ |
| group-onsemi | 0:098463de4c5d | 120 | */ |
| group-onsemi | 0:098463de4c5d | 121 | #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) |
| group-onsemi | 0:098463de4c5d | 122 | /** |
| group-onsemi | 0:098463de4c5d | 123 | * @} |
| group-onsemi | 0:098463de4c5d | 124 | */ |
| group-onsemi | 0:098463de4c5d | 125 | |
| group-onsemi | 0:098463de4c5d | 126 | /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NOR/SRAM EXTENDED Device Instance |
| group-onsemi | 0:098463de4c5d | 127 | * @{ |
| group-onsemi | 0:098463de4c5d | 128 | */ |
| group-onsemi | 0:098463de4c5d | 129 | #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) |
| group-onsemi | 0:098463de4c5d | 130 | /** |
| group-onsemi | 0:098463de4c5d | 131 | * @} |
| group-onsemi | 0:098463de4c5d | 132 | */ |
| group-onsemi | 0:098463de4c5d | 133 | |
| group-onsemi | 0:098463de4c5d | 134 | /** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance |
| group-onsemi | 0:098463de4c5d | 135 | * @{ |
| group-onsemi | 0:098463de4c5d | 136 | */ |
| group-onsemi | 0:098463de4c5d | 137 | #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) |
| group-onsemi | 0:098463de4c5d | 138 | /** |
| group-onsemi | 0:098463de4c5d | 139 | * @} |
| group-onsemi | 0:098463de4c5d | 140 | */ |
| group-onsemi | 0:098463de4c5d | 141 | |
| group-onsemi | 0:098463de4c5d | 142 | #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ |
| group-onsemi | 0:098463de4c5d | 143 | ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) |
| group-onsemi | 0:098463de4c5d | 144 | |
| group-onsemi | 0:098463de4c5d | 145 | #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ |
| group-onsemi | 0:098463de4c5d | 146 | ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) |
| group-onsemi | 0:098463de4c5d | 147 | |
| group-onsemi | 0:098463de4c5d | 148 | #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ |
| group-onsemi | 0:098463de4c5d | 149 | ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) |
| group-onsemi | 0:098463de4c5d | 150 | |
| group-onsemi | 0:098463de4c5d | 151 | |
| group-onsemi | 0:098463de4c5d | 152 | #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ |
| group-onsemi | 0:098463de4c5d | 153 | ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) |
| group-onsemi | 0:098463de4c5d | 154 | |
| group-onsemi | 0:098463de4c5d | 155 | #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ |
| group-onsemi | 0:098463de4c5d | 156 | ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) |
| group-onsemi | 0:098463de4c5d | 157 | |
| group-onsemi | 0:098463de4c5d | 158 | #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ |
| group-onsemi | 0:098463de4c5d | 159 | ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) |
| group-onsemi | 0:098463de4c5d | 160 | |
| group-onsemi | 0:098463de4c5d | 161 | #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ |
| group-onsemi | 0:098463de4c5d | 162 | ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) |
| group-onsemi | 0:098463de4c5d | 163 | |
| group-onsemi | 0:098463de4c5d | 164 | /** @defgroup FMC_Address_Setup_Time |
| group-onsemi | 0:098463de4c5d | 165 | * @{ |
| group-onsemi | 0:098463de4c5d | 166 | */ |
| group-onsemi | 0:098463de4c5d | 167 | #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) |
| group-onsemi | 0:098463de4c5d | 168 | /** |
| group-onsemi | 0:098463de4c5d | 169 | * @} |
| group-onsemi | 0:098463de4c5d | 170 | */ |
| group-onsemi | 0:098463de4c5d | 171 | |
| group-onsemi | 0:098463de4c5d | 172 | /** @defgroup FMC_Address_Hold_Time |
| group-onsemi | 0:098463de4c5d | 173 | * @{ |
| group-onsemi | 0:098463de4c5d | 174 | */ |
| group-onsemi | 0:098463de4c5d | 175 | #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) |
| group-onsemi | 0:098463de4c5d | 176 | /** |
| group-onsemi | 0:098463de4c5d | 177 | * @} |
| group-onsemi | 0:098463de4c5d | 178 | */ |
| group-onsemi | 0:098463de4c5d | 179 | |
| group-onsemi | 0:098463de4c5d | 180 | /** @defgroup FMC_Data_Setup_Time |
| group-onsemi | 0:098463de4c5d | 181 | * @{ |
| group-onsemi | 0:098463de4c5d | 182 | */ |
| group-onsemi | 0:098463de4c5d | 183 | #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) |
| group-onsemi | 0:098463de4c5d | 184 | /** |
| group-onsemi | 0:098463de4c5d | 185 | * @} |
| group-onsemi | 0:098463de4c5d | 186 | */ |
| group-onsemi | 0:098463de4c5d | 187 | |
| group-onsemi | 0:098463de4c5d | 188 | /** @defgroup FMC_Bus_Turn_around_Duration |
| group-onsemi | 0:098463de4c5d | 189 | * @{ |
| group-onsemi | 0:098463de4c5d | 190 | */ |
| group-onsemi | 0:098463de4c5d | 191 | #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) |
| group-onsemi | 0:098463de4c5d | 192 | /** |
| group-onsemi | 0:098463de4c5d | 193 | * @} |
| group-onsemi | 0:098463de4c5d | 194 | */ |
| group-onsemi | 0:098463de4c5d | 195 | |
| group-onsemi | 0:098463de4c5d | 196 | /** @defgroup FMC_CLK_Division |
| group-onsemi | 0:098463de4c5d | 197 | * @{ |
| group-onsemi | 0:098463de4c5d | 198 | */ |
| group-onsemi | 0:098463de4c5d | 199 | #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16)) |
| group-onsemi | 0:098463de4c5d | 200 | /** |
| group-onsemi | 0:098463de4c5d | 201 | * @} |
| group-onsemi | 0:098463de4c5d | 202 | */ |
| group-onsemi | 0:098463de4c5d | 203 | |
| group-onsemi | 0:098463de4c5d | 204 | /** @defgroup FMC_Data_Latency |
| group-onsemi | 0:098463de4c5d | 205 | * @{ |
| group-onsemi | 0:098463de4c5d | 206 | */ |
| group-onsemi | 0:098463de4c5d | 207 | #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) |
| group-onsemi | 0:098463de4c5d | 208 | /** |
| group-onsemi | 0:098463de4c5d | 209 | * @} |
| group-onsemi | 0:098463de4c5d | 210 | */ |
| group-onsemi | 0:098463de4c5d | 211 | |
| group-onsemi | 0:098463de4c5d | 212 | /** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time |
| group-onsemi | 0:098463de4c5d | 213 | * @{ |
| group-onsemi | 0:098463de4c5d | 214 | */ |
| group-onsemi | 0:098463de4c5d | 215 | #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) |
| group-onsemi | 0:098463de4c5d | 216 | /** |
| group-onsemi | 0:098463de4c5d | 217 | * @} |
| group-onsemi | 0:098463de4c5d | 218 | */ |
| group-onsemi | 0:098463de4c5d | 219 | |
| group-onsemi | 0:098463de4c5d | 220 | /** @defgroup FMC_TAR_Setup_Time |
| group-onsemi | 0:098463de4c5d | 221 | * @{ |
| group-onsemi | 0:098463de4c5d | 222 | */ |
| group-onsemi | 0:098463de4c5d | 223 | #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255) |
| group-onsemi | 0:098463de4c5d | 224 | /** |
| group-onsemi | 0:098463de4c5d | 225 | * @} |
| group-onsemi | 0:098463de4c5d | 226 | */ |
| group-onsemi | 0:098463de4c5d | 227 | |
| group-onsemi | 0:098463de4c5d | 228 | /** @defgroup FMC_Setup_Time |
| group-onsemi | 0:098463de4c5d | 229 | * @{ |
| group-onsemi | 0:098463de4c5d | 230 | */ |
| group-onsemi | 0:098463de4c5d | 231 | #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255) |
| group-onsemi | 0:098463de4c5d | 232 | /** |
| group-onsemi | 0:098463de4c5d | 233 | * @} |
| group-onsemi | 0:098463de4c5d | 234 | */ |
| group-onsemi | 0:098463de4c5d | 235 | |
| group-onsemi | 0:098463de4c5d | 236 | /** @defgroup FMC_Wait_Setup_Time |
| group-onsemi | 0:098463de4c5d | 237 | * @{ |
| group-onsemi | 0:098463de4c5d | 238 | */ |
| group-onsemi | 0:098463de4c5d | 239 | #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255) |
| group-onsemi | 0:098463de4c5d | 240 | /** |
| group-onsemi | 0:098463de4c5d | 241 | * @} |
| group-onsemi | 0:098463de4c5d | 242 | */ |
| group-onsemi | 0:098463de4c5d | 243 | |
| group-onsemi | 0:098463de4c5d | 244 | /** @defgroup FMC_Hold_Setup_Time |
| group-onsemi | 0:098463de4c5d | 245 | * @{ |
| group-onsemi | 0:098463de4c5d | 246 | */ |
| group-onsemi | 0:098463de4c5d | 247 | #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255) |
| group-onsemi | 0:098463de4c5d | 248 | /** |
| group-onsemi | 0:098463de4c5d | 249 | * @} |
| group-onsemi | 0:098463de4c5d | 250 | */ |
| group-onsemi | 0:098463de4c5d | 251 | |
| group-onsemi | 0:098463de4c5d | 252 | /** @defgroup FMC_HiZ_Setup_Time |
| group-onsemi | 0:098463de4c5d | 253 | * @{ |
| group-onsemi | 0:098463de4c5d | 254 | */ |
| group-onsemi | 0:098463de4c5d | 255 | #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255) |
| group-onsemi | 0:098463de4c5d | 256 | /** |
| group-onsemi | 0:098463de4c5d | 257 | * @} |
| group-onsemi | 0:098463de4c5d | 258 | */ |
| group-onsemi | 0:098463de4c5d | 259 | |
| group-onsemi | 0:098463de4c5d | 260 | /** |
| group-onsemi | 0:098463de4c5d | 261 | * @} |
| group-onsemi | 0:098463de4c5d | 262 | */ |
| group-onsemi | 0:098463de4c5d | 263 | |
| group-onsemi | 0:098463de4c5d | 264 | /* Exported typedef ----------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 265 | /** @addtogroup FMC_LL_Exported_Typedef FMC Low Layer Exported Typedef |
| group-onsemi | 0:098463de4c5d | 266 | * @{ |
| group-onsemi | 0:098463de4c5d | 267 | */ |
| group-onsemi | 0:098463de4c5d | 268 | #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef |
| group-onsemi | 0:098463de4c5d | 269 | #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef |
| group-onsemi | 0:098463de4c5d | 270 | #define FMC_NAND_TypeDef FMC_Bank3_TypeDef |
| group-onsemi | 0:098463de4c5d | 271 | |
| group-onsemi | 0:098463de4c5d | 272 | #define FMC_NORSRAM_DEVICE FMC_Bank1_R |
| group-onsemi | 0:098463de4c5d | 273 | #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R |
| group-onsemi | 0:098463de4c5d | 274 | #define FMC_NAND_DEVICE FMC_Bank3_R |
| group-onsemi | 0:098463de4c5d | 275 | |
| group-onsemi | 0:098463de4c5d | 276 | /** |
| group-onsemi | 0:098463de4c5d | 277 | * @brief FMC_NORSRAM Configuration Structure definition |
| group-onsemi | 0:098463de4c5d | 278 | */ |
| group-onsemi | 0:098463de4c5d | 279 | typedef struct |
| group-onsemi | 0:098463de4c5d | 280 | { |
| group-onsemi | 0:098463de4c5d | 281 | uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. |
| group-onsemi | 0:098463de4c5d | 282 | This parameter can be a value of @ref FMC_NORSRAM_Bank */ |
| group-onsemi | 0:098463de4c5d | 283 | |
| group-onsemi | 0:098463de4c5d | 284 | uint32_t DataAddressMux; /*!< Specifies whether the address and data values are |
| group-onsemi | 0:098463de4c5d | 285 | multiplexed on the data bus or not. |
| group-onsemi | 0:098463de4c5d | 286 | This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ |
| group-onsemi | 0:098463de4c5d | 287 | |
| group-onsemi | 0:098463de4c5d | 288 | uint32_t MemoryType; /*!< Specifies the type of external memory attached to |
| group-onsemi | 0:098463de4c5d | 289 | the corresponding memory device. |
| group-onsemi | 0:098463de4c5d | 290 | This parameter can be a value of @ref FMC_Memory_Type */ |
| group-onsemi | 0:098463de4c5d | 291 | |
| group-onsemi | 0:098463de4c5d | 292 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| group-onsemi | 0:098463de4c5d | 293 | This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ |
| group-onsemi | 0:098463de4c5d | 294 | |
| group-onsemi | 0:098463de4c5d | 295 | uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
| group-onsemi | 0:098463de4c5d | 296 | valid only with synchronous burst Flash memories. |
| group-onsemi | 0:098463de4c5d | 297 | This parameter can be a value of @ref FMC_Burst_Access_Mode */ |
| group-onsemi | 0:098463de4c5d | 298 | |
| group-onsemi | 0:098463de4c5d | 299 | uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
| group-onsemi | 0:098463de4c5d | 300 | the Flash memory in burst mode. |
| group-onsemi | 0:098463de4c5d | 301 | This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ |
| group-onsemi | 0:098463de4c5d | 302 | |
| group-onsemi | 0:098463de4c5d | 303 | uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
| group-onsemi | 0:098463de4c5d | 304 | clock cycle before the wait state or during the wait state, |
| group-onsemi | 0:098463de4c5d | 305 | valid only when accessing memories in burst mode. |
| group-onsemi | 0:098463de4c5d | 306 | This parameter can be a value of @ref FMC_Wait_Timing */ |
| group-onsemi | 0:098463de4c5d | 307 | |
| group-onsemi | 0:098463de4c5d | 308 | uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. |
| group-onsemi | 0:098463de4c5d | 309 | This parameter can be a value of @ref FMC_Write_Operation */ |
| group-onsemi | 0:098463de4c5d | 310 | |
| group-onsemi | 0:098463de4c5d | 311 | uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait |
| group-onsemi | 0:098463de4c5d | 312 | signal, valid for Flash memory access in burst mode. |
| group-onsemi | 0:098463de4c5d | 313 | This parameter can be a value of @ref FMC_Wait_Signal */ |
| group-onsemi | 0:098463de4c5d | 314 | |
| group-onsemi | 0:098463de4c5d | 315 | uint32_t ExtendedMode; /*!< Enables or disables the extended mode. |
| group-onsemi | 0:098463de4c5d | 316 | This parameter can be a value of @ref FMC_Extended_Mode */ |
| group-onsemi | 0:098463de4c5d | 317 | |
| group-onsemi | 0:098463de4c5d | 318 | uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
| group-onsemi | 0:098463de4c5d | 319 | valid only with asynchronous Flash memories. |
| group-onsemi | 0:098463de4c5d | 320 | This parameter can be a value of @ref FMC_AsynchronousWait */ |
| group-onsemi | 0:098463de4c5d | 321 | |
| group-onsemi | 0:098463de4c5d | 322 | uint32_t WriteBurst; /*!< Enables or disables the write burst operation. |
| group-onsemi | 0:098463de4c5d | 323 | This parameter can be a value of @ref FMC_Write_Burst */ |
| group-onsemi | 0:098463de4c5d | 324 | |
| group-onsemi | 0:098463de4c5d | 325 | uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. |
| group-onsemi | 0:098463de4c5d | 326 | This parameter is only enabled through the FMC_BCR1 register, and don't care |
| group-onsemi | 0:098463de4c5d | 327 | through FMC_BCR2..4 registers. |
| group-onsemi | 0:098463de4c5d | 328 | This parameter can be a value of @ref FMC_Continous_Clock */ |
| group-onsemi | 0:098463de4c5d | 329 | |
| group-onsemi | 0:098463de4c5d | 330 | uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. |
| group-onsemi | 0:098463de4c5d | 331 | This parameter is only enabled through the FMC_BCR1 register, and don't care |
| group-onsemi | 0:098463de4c5d | 332 | through FMC_BCR2..4 registers. |
| group-onsemi | 0:098463de4c5d | 333 | This parameter can be a value of @ref FMC_Write_FIFO. |
| group-onsemi | 0:098463de4c5d | 334 | @note This Parameter is not available for STM32L47x/L48x devices. */ |
| group-onsemi | 0:098463de4c5d | 335 | |
| group-onsemi | 0:098463de4c5d | 336 | uint32_t PageSize; /*!< Specifies the memory page size. |
| group-onsemi | 0:098463de4c5d | 337 | This parameter can be a value of @ref FMC_Page_Size */ |
| group-onsemi | 0:098463de4c5d | 338 | |
| group-onsemi | 0:098463de4c5d | 339 | }FMC_NORSRAM_InitTypeDef; |
| group-onsemi | 0:098463de4c5d | 340 | |
| group-onsemi | 0:098463de4c5d | 341 | /** |
| group-onsemi | 0:098463de4c5d | 342 | * @brief FMC_NORSRAM Timing parameters structure definition |
| group-onsemi | 0:098463de4c5d | 343 | */ |
| group-onsemi | 0:098463de4c5d | 344 | typedef struct |
| group-onsemi | 0:098463de4c5d | 345 | { |
| group-onsemi | 0:098463de4c5d | 346 | uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
| group-onsemi | 0:098463de4c5d | 347 | the duration of the address setup time. |
| group-onsemi | 0:098463de4c5d | 348 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| group-onsemi | 0:098463de4c5d | 349 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| group-onsemi | 0:098463de4c5d | 350 | |
| group-onsemi | 0:098463de4c5d | 351 | uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
| group-onsemi | 0:098463de4c5d | 352 | the duration of the address hold time. |
| group-onsemi | 0:098463de4c5d | 353 | This parameter can be a value between Min_Data = 1 and Max_Data = 15. |
| group-onsemi | 0:098463de4c5d | 354 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| group-onsemi | 0:098463de4c5d | 355 | |
| group-onsemi | 0:098463de4c5d | 356 | uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
| group-onsemi | 0:098463de4c5d | 357 | the duration of the data setup time. |
| group-onsemi | 0:098463de4c5d | 358 | This parameter can be a value between Min_Data = 1 and Max_Data = 255. |
| group-onsemi | 0:098463de4c5d | 359 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
| group-onsemi | 0:098463de4c5d | 360 | NOR Flash memories. */ |
| group-onsemi | 0:098463de4c5d | 361 | |
| group-onsemi | 0:098463de4c5d | 362 | uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
| group-onsemi | 0:098463de4c5d | 363 | the duration of the bus turnaround. |
| group-onsemi | 0:098463de4c5d | 364 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| group-onsemi | 0:098463de4c5d | 365 | @note This parameter is only used for multiplexed NOR Flash memories. */ |
| group-onsemi | 0:098463de4c5d | 366 | |
| group-onsemi | 0:098463de4c5d | 367 | uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of |
| group-onsemi | 0:098463de4c5d | 368 | HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. |
| group-onsemi | 0:098463de4c5d | 369 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM |
| group-onsemi | 0:098463de4c5d | 370 | accesses. */ |
| group-onsemi | 0:098463de4c5d | 371 | |
| group-onsemi | 0:098463de4c5d | 372 | uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue |
| group-onsemi | 0:098463de4c5d | 373 | to the memory before getting the first data. |
| group-onsemi | 0:098463de4c5d | 374 | The parameter value depends on the memory type as shown below: |
| group-onsemi | 0:098463de4c5d | 375 | - It must be set to 0 in case of a CRAM |
| group-onsemi | 0:098463de4c5d | 376 | - It is don't care in asynchronous NOR, SRAM or ROM accesses |
| group-onsemi | 0:098463de4c5d | 377 | - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories |
| group-onsemi | 0:098463de4c5d | 378 | with synchronous burst mode enable */ |
| group-onsemi | 0:098463de4c5d | 379 | |
| group-onsemi | 0:098463de4c5d | 380 | uint32_t AccessMode; /*!< Specifies the asynchronous access mode. |
| group-onsemi | 0:098463de4c5d | 381 | This parameter can be a value of @ref FMC_Access_Mode */ |
| group-onsemi | 0:098463de4c5d | 382 | }FMC_NORSRAM_TimingTypeDef; |
| group-onsemi | 0:098463de4c5d | 383 | |
| group-onsemi | 0:098463de4c5d | 384 | /** |
| group-onsemi | 0:098463de4c5d | 385 | * @brief FMC_NAND Configuration Structure definition |
| group-onsemi | 0:098463de4c5d | 386 | */ |
| group-onsemi | 0:098463de4c5d | 387 | typedef struct |
| group-onsemi | 0:098463de4c5d | 388 | { |
| group-onsemi | 0:098463de4c5d | 389 | uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. |
| group-onsemi | 0:098463de4c5d | 390 | This parameter can be a value of @ref FMC_NAND_Bank */ |
| group-onsemi | 0:098463de4c5d | 391 | |
| group-onsemi | 0:098463de4c5d | 392 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. |
| group-onsemi | 0:098463de4c5d | 393 | This parameter can be any value of @ref FMC_Wait_feature */ |
| group-onsemi | 0:098463de4c5d | 394 | |
| group-onsemi | 0:098463de4c5d | 395 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| group-onsemi | 0:098463de4c5d | 396 | This parameter can be any value of @ref FMC_NAND_Data_Width */ |
| group-onsemi | 0:098463de4c5d | 397 | |
| group-onsemi | 0:098463de4c5d | 398 | uint32_t EccComputation; /*!< Enables or disables the ECC computation. |
| group-onsemi | 0:098463de4c5d | 399 | This parameter can be any value of @ref FMC_ECC */ |
| group-onsemi | 0:098463de4c5d | 400 | |
| group-onsemi | 0:098463de4c5d | 401 | uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. |
| group-onsemi | 0:098463de4c5d | 402 | This parameter can be any value of @ref FMC_ECC_Page_Size */ |
| group-onsemi | 0:098463de4c5d | 403 | |
| group-onsemi | 0:098463de4c5d | 404 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| group-onsemi | 0:098463de4c5d | 405 | delay between CLE low and RE low. |
| group-onsemi | 0:098463de4c5d | 406 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| group-onsemi | 0:098463de4c5d | 407 | |
| group-onsemi | 0:098463de4c5d | 408 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| group-onsemi | 0:098463de4c5d | 409 | delay between ALE low and RE low. |
| group-onsemi | 0:098463de4c5d | 410 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| group-onsemi | 0:098463de4c5d | 411 | }FMC_NAND_InitTypeDef; |
| group-onsemi | 0:098463de4c5d | 412 | |
| group-onsemi | 0:098463de4c5d | 413 | /** |
| group-onsemi | 0:098463de4c5d | 414 | * @brief FMC_NAND Timing parameters structure definition |
| group-onsemi | 0:098463de4c5d | 415 | */ |
| group-onsemi | 0:098463de4c5d | 416 | typedef struct |
| group-onsemi | 0:098463de4c5d | 417 | { |
| group-onsemi | 0:098463de4c5d | 418 | uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before |
| group-onsemi | 0:098463de4c5d | 419 | the command assertion for NAND-Flash read or write access |
| group-onsemi | 0:098463de4c5d | 420 | to common/Attribute or I/O memory space (depending on |
| group-onsemi | 0:098463de4c5d | 421 | the memory space timing to be configured). |
| group-onsemi | 0:098463de4c5d | 422 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| group-onsemi | 0:098463de4c5d | 423 | |
| group-onsemi | 0:098463de4c5d | 424 | uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the |
| group-onsemi | 0:098463de4c5d | 425 | command for NAND-Flash read or write access to |
| group-onsemi | 0:098463de4c5d | 426 | common/Attribute or I/O memory space (depending on the |
| group-onsemi | 0:098463de4c5d | 427 | memory space timing to be configured). |
| group-onsemi | 0:098463de4c5d | 428 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| group-onsemi | 0:098463de4c5d | 429 | |
| group-onsemi | 0:098463de4c5d | 430 | uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address |
| group-onsemi | 0:098463de4c5d | 431 | (and data for write access) after the command de-assertion |
| group-onsemi | 0:098463de4c5d | 432 | for NAND-Flash read or write access to common/Attribute |
| group-onsemi | 0:098463de4c5d | 433 | or I/O memory space (depending on the memory space timing |
| group-onsemi | 0:098463de4c5d | 434 | to be configured). |
| group-onsemi | 0:098463de4c5d | 435 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| group-onsemi | 0:098463de4c5d | 436 | |
| group-onsemi | 0:098463de4c5d | 437 | uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the |
| group-onsemi | 0:098463de4c5d | 438 | data bus is kept in HiZ after the start of a NAND-Flash |
| group-onsemi | 0:098463de4c5d | 439 | write access to common/Attribute or I/O memory space (depending |
| group-onsemi | 0:098463de4c5d | 440 | on the memory space timing to be configured). |
| group-onsemi | 0:098463de4c5d | 441 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| group-onsemi | 0:098463de4c5d | 442 | }FMC_NAND_PCC_TimingTypeDef; |
| group-onsemi | 0:098463de4c5d | 443 | |
| group-onsemi | 0:098463de4c5d | 444 | /** |
| group-onsemi | 0:098463de4c5d | 445 | * @} |
| group-onsemi | 0:098463de4c5d | 446 | */ |
| group-onsemi | 0:098463de4c5d | 447 | |
| group-onsemi | 0:098463de4c5d | 448 | /* Exported constants --------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 449 | /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants |
| group-onsemi | 0:098463de4c5d | 450 | * @{ |
| group-onsemi | 0:098463de4c5d | 451 | */ |
| group-onsemi | 0:098463de4c5d | 452 | |
| group-onsemi | 0:098463de4c5d | 453 | /** @defgroup FMC_NOR_SRAM_Exported_constants FMC NOR/SRAM Exported constants |
| group-onsemi | 0:098463de4c5d | 454 | * @{ |
| group-onsemi | 0:098463de4c5d | 455 | */ |
| group-onsemi | 0:098463de4c5d | 456 | |
| group-onsemi | 0:098463de4c5d | 457 | /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank |
| group-onsemi | 0:098463de4c5d | 458 | * @{ |
| group-onsemi | 0:098463de4c5d | 459 | */ |
| group-onsemi | 0:098463de4c5d | 460 | #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 461 | #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002) |
| group-onsemi | 0:098463de4c5d | 462 | #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004) |
| group-onsemi | 0:098463de4c5d | 463 | #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006) |
| group-onsemi | 0:098463de4c5d | 464 | /** |
| group-onsemi | 0:098463de4c5d | 465 | * @} |
| group-onsemi | 0:098463de4c5d | 466 | */ |
| group-onsemi | 0:098463de4c5d | 467 | |
| group-onsemi | 0:098463de4c5d | 468 | /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing |
| group-onsemi | 0:098463de4c5d | 469 | * @{ |
| group-onsemi | 0:098463de4c5d | 470 | */ |
| group-onsemi | 0:098463de4c5d | 471 | #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 472 | #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FMC_BCRx_MUXEN) |
| group-onsemi | 0:098463de4c5d | 473 | /** |
| group-onsemi | 0:098463de4c5d | 474 | * @} |
| group-onsemi | 0:098463de4c5d | 475 | */ |
| group-onsemi | 0:098463de4c5d | 476 | |
| group-onsemi | 0:098463de4c5d | 477 | /** @defgroup FMC_Memory_Type FMC Memory Type |
| group-onsemi | 0:098463de4c5d | 478 | * @{ |
| group-onsemi | 0:098463de4c5d | 479 | */ |
| group-onsemi | 0:098463de4c5d | 480 | #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 481 | #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)FMC_BCRx_MTYP_0) |
| group-onsemi | 0:098463de4c5d | 482 | #define FMC_MEMORY_TYPE_NOR ((uint32_t)FMC_BCRx_MTYP_1) |
| group-onsemi | 0:098463de4c5d | 483 | /** |
| group-onsemi | 0:098463de4c5d | 484 | * @} |
| group-onsemi | 0:098463de4c5d | 485 | */ |
| group-onsemi | 0:098463de4c5d | 486 | |
| group-onsemi | 0:098463de4c5d | 487 | /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width |
| group-onsemi | 0:098463de4c5d | 488 | * @{ |
| group-onsemi | 0:098463de4c5d | 489 | */ |
| group-onsemi | 0:098463de4c5d | 490 | #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 491 | #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FMC_BCRx_MWID_0) |
| group-onsemi | 0:098463de4c5d | 492 | #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FMC_BCRx_MWID_1) |
| group-onsemi | 0:098463de4c5d | 493 | /** |
| group-onsemi | 0:098463de4c5d | 494 | * @} |
| group-onsemi | 0:098463de4c5d | 495 | */ |
| group-onsemi | 0:098463de4c5d | 496 | |
| group-onsemi | 0:098463de4c5d | 497 | /** @defgroup FMC_NORSRAM_Flash_Access FMC NORSRAM Flash Access |
| group-onsemi | 0:098463de4c5d | 498 | * @{ |
| group-onsemi | 0:098463de4c5d | 499 | */ |
| group-onsemi | 0:098463de4c5d | 500 | #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FMC_BCRx_FACCEN) |
| group-onsemi | 0:098463de4c5d | 501 | #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 502 | /** |
| group-onsemi | 0:098463de4c5d | 503 | * @} |
| group-onsemi | 0:098463de4c5d | 504 | */ |
| group-onsemi | 0:098463de4c5d | 505 | |
| group-onsemi | 0:098463de4c5d | 506 | /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode |
| group-onsemi | 0:098463de4c5d | 507 | * @{ |
| group-onsemi | 0:098463de4c5d | 508 | */ |
| group-onsemi | 0:098463de4c5d | 509 | #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 510 | #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FMC_BCRx_BURSTEN) |
| group-onsemi | 0:098463de4c5d | 511 | /** |
| group-onsemi | 0:098463de4c5d | 512 | * @} |
| group-onsemi | 0:098463de4c5d | 513 | */ |
| group-onsemi | 0:098463de4c5d | 514 | |
| group-onsemi | 0:098463de4c5d | 515 | |
| group-onsemi | 0:098463de4c5d | 516 | /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity |
| group-onsemi | 0:098463de4c5d | 517 | * @{ |
| group-onsemi | 0:098463de4c5d | 518 | */ |
| group-onsemi | 0:098463de4c5d | 519 | #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 520 | #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FMC_BCRx_WAITPOL) |
| group-onsemi | 0:098463de4c5d | 521 | /** |
| group-onsemi | 0:098463de4c5d | 522 | * @} |
| group-onsemi | 0:098463de4c5d | 523 | */ |
| group-onsemi | 0:098463de4c5d | 524 | |
| group-onsemi | 0:098463de4c5d | 525 | /** @defgroup FMC_Wait_Timing FMC Wait Timing |
| group-onsemi | 0:098463de4c5d | 526 | * @{ |
| group-onsemi | 0:098463de4c5d | 527 | */ |
| group-onsemi | 0:098463de4c5d | 528 | #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 529 | #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)FMC_BCRx_WAITCFG) |
| group-onsemi | 0:098463de4c5d | 530 | |
| group-onsemi | 0:098463de4c5d | 531 | /** |
| group-onsemi | 0:098463de4c5d | 532 | * @} |
| group-onsemi | 0:098463de4c5d | 533 | */ |
| group-onsemi | 0:098463de4c5d | 534 | |
| group-onsemi | 0:098463de4c5d | 535 | /** @defgroup FMC_Write_Operation FMC Write Operation |
| group-onsemi | 0:098463de4c5d | 536 | * @{ |
| group-onsemi | 0:098463de4c5d | 537 | */ |
| group-onsemi | 0:098463de4c5d | 538 | #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 539 | #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)FMC_BCRx_WREN) |
| group-onsemi | 0:098463de4c5d | 540 | /** |
| group-onsemi | 0:098463de4c5d | 541 | * @} |
| group-onsemi | 0:098463de4c5d | 542 | */ |
| group-onsemi | 0:098463de4c5d | 543 | |
| group-onsemi | 0:098463de4c5d | 544 | /** @defgroup FMC_Wait_Signal FMC Wait Signal |
| group-onsemi | 0:098463de4c5d | 545 | * @{ |
| group-onsemi | 0:098463de4c5d | 546 | */ |
| group-onsemi | 0:098463de4c5d | 547 | #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 548 | #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)FMC_BCRx_WAITEN) |
| group-onsemi | 0:098463de4c5d | 549 | /** |
| group-onsemi | 0:098463de4c5d | 550 | * @} |
| group-onsemi | 0:098463de4c5d | 551 | */ |
| group-onsemi | 0:098463de4c5d | 552 | |
| group-onsemi | 0:098463de4c5d | 553 | /** @defgroup FMC_Extended_Mode FMC Extended Mode |
| group-onsemi | 0:098463de4c5d | 554 | * @{ |
| group-onsemi | 0:098463de4c5d | 555 | */ |
| group-onsemi | 0:098463de4c5d | 556 | #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 557 | #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)FMC_BCRx_EXTMOD) |
| group-onsemi | 0:098463de4c5d | 558 | /** |
| group-onsemi | 0:098463de4c5d | 559 | * @} |
| group-onsemi | 0:098463de4c5d | 560 | */ |
| group-onsemi | 0:098463de4c5d | 561 | |
| group-onsemi | 0:098463de4c5d | 562 | /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait |
| group-onsemi | 0:098463de4c5d | 563 | * @{ |
| group-onsemi | 0:098463de4c5d | 564 | */ |
| group-onsemi | 0:098463de4c5d | 565 | #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 566 | #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FMC_BCRx_ASYNCWAIT) |
| group-onsemi | 0:098463de4c5d | 567 | /** |
| group-onsemi | 0:098463de4c5d | 568 | * @} |
| group-onsemi | 0:098463de4c5d | 569 | */ |
| group-onsemi | 0:098463de4c5d | 570 | |
| group-onsemi | 0:098463de4c5d | 571 | /** @defgroup FMC_Page_Size FMC Page Size |
| group-onsemi | 0:098463de4c5d | 572 | * @{ |
| group-onsemi | 0:098463de4c5d | 573 | */ |
| group-onsemi | 0:098463de4c5d | 574 | #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 575 | #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0) |
| group-onsemi | 0:098463de4c5d | 576 | #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1) |
| group-onsemi | 0:098463de4c5d | 577 | #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1)) |
| group-onsemi | 0:098463de4c5d | 578 | #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCRx_CPSIZE_2) |
| group-onsemi | 0:098463de4c5d | 579 | /** |
| group-onsemi | 0:098463de4c5d | 580 | * @} |
| group-onsemi | 0:098463de4c5d | 581 | */ |
| group-onsemi | 0:098463de4c5d | 582 | |
| group-onsemi | 0:098463de4c5d | 583 | /** @defgroup FMC_Write_Burst FMC Write Burst |
| group-onsemi | 0:098463de4c5d | 584 | * @{ |
| group-onsemi | 0:098463de4c5d | 585 | */ |
| group-onsemi | 0:098463de4c5d | 586 | #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 587 | #define FMC_WRITE_BURST_ENABLE ((uint32_t)FMC_BCRx_CBURSTRW) |
| group-onsemi | 0:098463de4c5d | 588 | /** |
| group-onsemi | 0:098463de4c5d | 589 | * @} |
| group-onsemi | 0:098463de4c5d | 590 | */ |
| group-onsemi | 0:098463de4c5d | 591 | |
| group-onsemi | 0:098463de4c5d | 592 | /** @defgroup FMC_Continous_Clock FMC Continous Clock |
| group-onsemi | 0:098463de4c5d | 593 | * @{ |
| group-onsemi | 0:098463de4c5d | 594 | */ |
| group-onsemi | 0:098463de4c5d | 595 | #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 596 | #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)FMC_BCR1_CCLKEN) |
| group-onsemi | 0:098463de4c5d | 597 | /** |
| group-onsemi | 0:098463de4c5d | 598 | * @} |
| group-onsemi | 0:098463de4c5d | 599 | */ |
| group-onsemi | 0:098463de4c5d | 600 | |
| group-onsemi | 0:098463de4c5d | 601 | /** @defgroup FMC_Access_Mode FMC Access Mode |
| group-onsemi | 0:098463de4c5d | 602 | * @{ |
| group-onsemi | 0:098463de4c5d | 603 | */ |
| group-onsemi | 0:098463de4c5d | 604 | #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 605 | #define FMC_ACCESS_MODE_B ((uint32_t)FMC_BTRx_ACCMOD_0) |
| group-onsemi | 0:098463de4c5d | 606 | #define FMC_ACCESS_MODE_C ((uint32_t)FMC_BTRx_ACCMOD_1) |
| group-onsemi | 0:098463de4c5d | 607 | #define FMC_ACCESS_MODE_D ((uint32_t)(FMC_BTRx_ACCMOD_0|FMC_BTRx_ACCMOD_1)) |
| group-onsemi | 0:098463de4c5d | 608 | /** |
| group-onsemi | 0:098463de4c5d | 609 | * @} |
| group-onsemi | 0:098463de4c5d | 610 | */ |
| group-onsemi | 0:098463de4c5d | 611 | |
| group-onsemi | 0:098463de4c5d | 612 | /** |
| group-onsemi | 0:098463de4c5d | 613 | * @} |
| group-onsemi | 0:098463de4c5d | 614 | */ |
| group-onsemi | 0:098463de4c5d | 615 | |
| group-onsemi | 0:098463de4c5d | 616 | /** |
| group-onsemi | 0:098463de4c5d | 617 | * @} |
| group-onsemi | 0:098463de4c5d | 618 | */ |
| group-onsemi | 0:098463de4c5d | 619 | |
| group-onsemi | 0:098463de4c5d | 620 | /** @defgroup FMC_NAND_Controller FMC NAND Exported constants |
| group-onsemi | 0:098463de4c5d | 621 | * @{ |
| group-onsemi | 0:098463de4c5d | 622 | */ |
| group-onsemi | 0:098463de4c5d | 623 | |
| group-onsemi | 0:098463de4c5d | 624 | /** @defgroup FMC_NAND_Bank FMC NAND Bank |
| group-onsemi | 0:098463de4c5d | 625 | * @{ |
| group-onsemi | 0:098463de4c5d | 626 | */ |
| group-onsemi | 0:098463de4c5d | 627 | #define FMC_NAND_BANK3 ((uint32_t)0x00000100) |
| group-onsemi | 0:098463de4c5d | 628 | /** |
| group-onsemi | 0:098463de4c5d | 629 | * @} |
| group-onsemi | 0:098463de4c5d | 630 | */ |
| group-onsemi | 0:098463de4c5d | 631 | |
| group-onsemi | 0:098463de4c5d | 632 | /** @defgroup FMC_Wait_feature FMC Wait feature |
| group-onsemi | 0:098463de4c5d | 633 | * @{ |
| group-onsemi | 0:098463de4c5d | 634 | */ |
| group-onsemi | 0:098463de4c5d | 635 | #define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 636 | #define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)FMC_PCR_PWAITEN) |
| group-onsemi | 0:098463de4c5d | 637 | /** |
| group-onsemi | 0:098463de4c5d | 638 | * @} |
| group-onsemi | 0:098463de4c5d | 639 | */ |
| group-onsemi | 0:098463de4c5d | 640 | |
| group-onsemi | 0:098463de4c5d | 641 | /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type |
| group-onsemi | 0:098463de4c5d | 642 | * @{ |
| group-onsemi | 0:098463de4c5d | 643 | */ |
| group-onsemi | 0:098463de4c5d | 644 | #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FMC_PCR_PTYP) |
| group-onsemi | 0:098463de4c5d | 645 | /** |
| group-onsemi | 0:098463de4c5d | 646 | * @} |
| group-onsemi | 0:098463de4c5d | 647 | */ |
| group-onsemi | 0:098463de4c5d | 648 | |
| group-onsemi | 0:098463de4c5d | 649 | /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width |
| group-onsemi | 0:098463de4c5d | 650 | * @{ |
| group-onsemi | 0:098463de4c5d | 651 | */ |
| group-onsemi | 0:098463de4c5d | 652 | #define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 653 | #define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)FMC_PCR_PWID_0) |
| group-onsemi | 0:098463de4c5d | 654 | /** |
| group-onsemi | 0:098463de4c5d | 655 | * @} |
| group-onsemi | 0:098463de4c5d | 656 | */ |
| group-onsemi | 0:098463de4c5d | 657 | |
| group-onsemi | 0:098463de4c5d | 658 | /** @defgroup FMC_ECC FMC NAND ECC |
| group-onsemi | 0:098463de4c5d | 659 | * @{ |
| group-onsemi | 0:098463de4c5d | 660 | */ |
| group-onsemi | 0:098463de4c5d | 661 | #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 662 | #define FMC_NAND_ECC_ENABLE ((uint32_t)FMC_PCR_ECCEN) |
| group-onsemi | 0:098463de4c5d | 663 | /** |
| group-onsemi | 0:098463de4c5d | 664 | * @} |
| group-onsemi | 0:098463de4c5d | 665 | */ |
| group-onsemi | 0:098463de4c5d | 666 | |
| group-onsemi | 0:098463de4c5d | 667 | /** @defgroup FMC_ECC_Page_Size FMC NAND ECC Page Size |
| group-onsemi | 0:098463de4c5d | 668 | * @{ |
| group-onsemi | 0:098463de4c5d | 669 | */ |
| group-onsemi | 0:098463de4c5d | 670 | #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) |
| group-onsemi | 0:098463de4c5d | 671 | #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FMC_PCR_ECCPS_0) |
| group-onsemi | 0:098463de4c5d | 672 | #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FMC_PCR_ECCPS_1) |
| group-onsemi | 0:098463de4c5d | 673 | #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_1) |
| group-onsemi | 0:098463de4c5d | 674 | #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FMC_PCR_ECCPS_2) |
| group-onsemi | 0:098463de4c5d | 675 | #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_2) |
| group-onsemi | 0:098463de4c5d | 676 | /** |
| group-onsemi | 0:098463de4c5d | 677 | * @} |
| group-onsemi | 0:098463de4c5d | 678 | */ |
| group-onsemi | 0:098463de4c5d | 679 | |
| group-onsemi | 0:098463de4c5d | 680 | /** |
| group-onsemi | 0:098463de4c5d | 681 | * @} |
| group-onsemi | 0:098463de4c5d | 682 | */ |
| group-onsemi | 0:098463de4c5d | 683 | |
| group-onsemi | 0:098463de4c5d | 684 | /** |
| group-onsemi | 0:098463de4c5d | 685 | * @} |
| group-onsemi | 0:098463de4c5d | 686 | */ |
| group-onsemi | 0:098463de4c5d | 687 | |
| group-onsemi | 0:098463de4c5d | 688 | /** @defgroup FMC_Interrupt_definition FMC Interrupt definition |
| group-onsemi | 0:098463de4c5d | 689 | * @brief FMC Interrupt definition |
| group-onsemi | 0:098463de4c5d | 690 | * @{ |
| group-onsemi | 0:098463de4c5d | 691 | */ |
| group-onsemi | 0:098463de4c5d | 692 | #define FMC_IT_RISING_EDGE ((uint32_t)FMC_SR_IREN) |
| group-onsemi | 0:098463de4c5d | 693 | #define FMC_IT_LEVEL ((uint32_t)FMC_SR_ILEN) |
| group-onsemi | 0:098463de4c5d | 694 | #define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SR_IFEN) |
| group-onsemi | 0:098463de4c5d | 695 | /** |
| group-onsemi | 0:098463de4c5d | 696 | * @} |
| group-onsemi | 0:098463de4c5d | 697 | */ |
| group-onsemi | 0:098463de4c5d | 698 | |
| group-onsemi | 0:098463de4c5d | 699 | /** @defgroup FMC_Flag_definition FMC Flag definition |
| group-onsemi | 0:098463de4c5d | 700 | * @brief FMC Flag definition |
| group-onsemi | 0:098463de4c5d | 701 | * @{ |
| group-onsemi | 0:098463de4c5d | 702 | */ |
| group-onsemi | 0:098463de4c5d | 703 | #define FMC_FLAG_RISING_EDGE ((uint32_t)FMC_SR_IRS) |
| group-onsemi | 0:098463de4c5d | 704 | #define FMC_FLAG_LEVEL ((uint32_t)FMC_SR_ILS) |
| group-onsemi | 0:098463de4c5d | 705 | #define FMC_FLAG_FALLING_EDGE ((uint32_t)FMC_SR_IFS) |
| group-onsemi | 0:098463de4c5d | 706 | #define FMC_FLAG_FEMPT ((uint32_t)FMC_SR_FEMPT) |
| group-onsemi | 0:098463de4c5d | 707 | /** |
| group-onsemi | 0:098463de4c5d | 708 | * @} |
| group-onsemi | 0:098463de4c5d | 709 | */ |
| group-onsemi | 0:098463de4c5d | 710 | |
| group-onsemi | 0:098463de4c5d | 711 | /* Exported macro ------------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 712 | |
| group-onsemi | 0:098463de4c5d | 713 | /** @defgroup FMC_Exported_Macros FMC Low Layer Exported Macros |
| group-onsemi | 0:098463de4c5d | 714 | * @{ |
| group-onsemi | 0:098463de4c5d | 715 | */ |
| group-onsemi | 0:098463de4c5d | 716 | |
| group-onsemi | 0:098463de4c5d | 717 | /** @defgroup FMC_NOR_Macros FMC NOR/SRAM Exported Macros |
| group-onsemi | 0:098463de4c5d | 718 | * @brief macros to handle NOR device enable/disable and read/write operations |
| group-onsemi | 0:098463de4c5d | 719 | * @{ |
| group-onsemi | 0:098463de4c5d | 720 | */ |
| group-onsemi | 0:098463de4c5d | 721 | |
| group-onsemi | 0:098463de4c5d | 722 | /** |
| group-onsemi | 0:098463de4c5d | 723 | * @brief Enable the NORSRAM device access. |
| group-onsemi | 0:098463de4c5d | 724 | * @param __INSTANCE__: FMC_NORSRAM Instance |
| group-onsemi | 0:098463de4c5d | 725 | * @param __BANK__: FMC_NORSRAM Bank |
| group-onsemi | 0:098463de4c5d | 726 | * @retval none |
| group-onsemi | 0:098463de4c5d | 727 | */ |
| group-onsemi | 0:098463de4c5d | 728 | #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN) |
| group-onsemi | 0:098463de4c5d | 729 | |
| group-onsemi | 0:098463de4c5d | 730 | /** |
| group-onsemi | 0:098463de4c5d | 731 | * @brief Disable the NORSRAM device access. |
| group-onsemi | 0:098463de4c5d | 732 | * @param __INSTANCE__: FMC_NORSRAM Instance |
| group-onsemi | 0:098463de4c5d | 733 | * @param __BANK__: FMC_NORSRAM Bank |
| group-onsemi | 0:098463de4c5d | 734 | * @retval none |
| group-onsemi | 0:098463de4c5d | 735 | */ |
| group-onsemi | 0:098463de4c5d | 736 | #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN) |
| group-onsemi | 0:098463de4c5d | 737 | |
| group-onsemi | 0:098463de4c5d | 738 | /** |
| group-onsemi | 0:098463de4c5d | 739 | * @} |
| group-onsemi | 0:098463de4c5d | 740 | */ |
| group-onsemi | 0:098463de4c5d | 741 | |
| group-onsemi | 0:098463de4c5d | 742 | /** @defgroup FMC_NAND_Macros FMC NAND Macros |
| group-onsemi | 0:098463de4c5d | 743 | * @brief macros to handle NAND device enable/disable |
| group-onsemi | 0:098463de4c5d | 744 | * @{ |
| group-onsemi | 0:098463de4c5d | 745 | */ |
| group-onsemi | 0:098463de4c5d | 746 | |
| group-onsemi | 0:098463de4c5d | 747 | /** |
| group-onsemi | 0:098463de4c5d | 748 | * @brief Enable the NAND device access. |
| group-onsemi | 0:098463de4c5d | 749 | * @param __INSTANCE__: FMC_NAND Instance |
| group-onsemi | 0:098463de4c5d | 750 | * @param __BANK__: FMC_NAND Bank |
| group-onsemi | 0:098463de4c5d | 751 | * @retval none |
| group-onsemi | 0:098463de4c5d | 752 | */ |
| group-onsemi | 0:098463de4c5d | 753 | #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) |
| group-onsemi | 0:098463de4c5d | 754 | |
| group-onsemi | 0:098463de4c5d | 755 | /** |
| group-onsemi | 0:098463de4c5d | 756 | * @brief Disable the NAND device access. |
| group-onsemi | 0:098463de4c5d | 757 | * @param __INSTANCE__: FMC_NAND Instance |
| group-onsemi | 0:098463de4c5d | 758 | * @param __BANK__: FMC_NAND Bank |
| group-onsemi | 0:098463de4c5d | 759 | * @retval None |
| group-onsemi | 0:098463de4c5d | 760 | */ |
| group-onsemi | 0:098463de4c5d | 761 | #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) |
| group-onsemi | 0:098463de4c5d | 762 | |
| group-onsemi | 0:098463de4c5d | 763 | /** |
| group-onsemi | 0:098463de4c5d | 764 | * @} |
| group-onsemi | 0:098463de4c5d | 765 | */ |
| group-onsemi | 0:098463de4c5d | 766 | |
| group-onsemi | 0:098463de4c5d | 767 | /** @defgroup FMC_Interrupt FMC Interrupt |
| group-onsemi | 0:098463de4c5d | 768 | * @brief macros to handle FMC interrupts |
| group-onsemi | 0:098463de4c5d | 769 | * @{ |
| group-onsemi | 0:098463de4c5d | 770 | */ |
| group-onsemi | 0:098463de4c5d | 771 | |
| group-onsemi | 0:098463de4c5d | 772 | /** |
| group-onsemi | 0:098463de4c5d | 773 | * @brief Enable the NAND device interrupt. |
| group-onsemi | 0:098463de4c5d | 774 | * @param __INSTANCE__: FMC_NAND Instance |
| group-onsemi | 0:098463de4c5d | 775 | * @param __BANK__: FMC_NAND Bank |
| group-onsemi | 0:098463de4c5d | 776 | * @param __INTERRUPT__: FMC_NAND interrupt |
| group-onsemi | 0:098463de4c5d | 777 | * This parameter can be any combination of the following values: |
| group-onsemi | 0:098463de4c5d | 778 | * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. |
| group-onsemi | 0:098463de4c5d | 779 | * @arg FMC_IT_LEVEL: Interrupt level. |
| group-onsemi | 0:098463de4c5d | 780 | * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. |
| group-onsemi | 0:098463de4c5d | 781 | * @retval None |
| group-onsemi | 0:098463de4c5d | 782 | */ |
| group-onsemi | 0:098463de4c5d | 783 | #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR, (__INTERRUPT__)) |
| group-onsemi | 0:098463de4c5d | 784 | |
| group-onsemi | 0:098463de4c5d | 785 | /** |
| group-onsemi | 0:098463de4c5d | 786 | * @brief Disable the NAND device interrupt. |
| group-onsemi | 0:098463de4c5d | 787 | * @param __INSTANCE__: FMC_NAND Instance |
| group-onsemi | 0:098463de4c5d | 788 | * @param __BANK__: FMC_NAND Bank |
| group-onsemi | 0:098463de4c5d | 789 | * @param __INTERRUPT__: FMC_NAND interrupt |
| group-onsemi | 0:098463de4c5d | 790 | * This parameter can be any combination of the following values: |
| group-onsemi | 0:098463de4c5d | 791 | * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. |
| group-onsemi | 0:098463de4c5d | 792 | * @arg FMC_IT_LEVEL: Interrupt level. |
| group-onsemi | 0:098463de4c5d | 793 | * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. |
| group-onsemi | 0:098463de4c5d | 794 | * @retval None |
| group-onsemi | 0:098463de4c5d | 795 | */ |
| group-onsemi | 0:098463de4c5d | 796 | #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR, (__INTERRUPT__)) |
| group-onsemi | 0:098463de4c5d | 797 | |
| group-onsemi | 0:098463de4c5d | 798 | /** |
| group-onsemi | 0:098463de4c5d | 799 | * @brief Get flag status of the NAND device. |
| group-onsemi | 0:098463de4c5d | 800 | * @param __INSTANCE__: FMC_NAND Instance |
| group-onsemi | 0:098463de4c5d | 801 | * @param __BANK__: FMC_NAND Bank |
| group-onsemi | 0:098463de4c5d | 802 | * @param __FLAG__: FMC_NAND flag |
| group-onsemi | 0:098463de4c5d | 803 | * This parameter can be any combination of the following values: |
| group-onsemi | 0:098463de4c5d | 804 | * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| group-onsemi | 0:098463de4c5d | 805 | * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. |
| group-onsemi | 0:098463de4c5d | 806 | * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| group-onsemi | 0:098463de4c5d | 807 | * @arg FMC_FLAG_FEMPT: FIFO empty flag. |
| group-onsemi | 0:098463de4c5d | 808 | * @retval The state of FLAG (SET or RESET). |
| group-onsemi | 0:098463de4c5d | 809 | */ |
| group-onsemi | 0:098463de4c5d | 810 | #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) |
| group-onsemi | 0:098463de4c5d | 811 | |
| group-onsemi | 0:098463de4c5d | 812 | /** |
| group-onsemi | 0:098463de4c5d | 813 | * @brief Clear flag status of the NAND device. |
| group-onsemi | 0:098463de4c5d | 814 | * @param __INSTANCE__: FMC_NAND Instance |
| group-onsemi | 0:098463de4c5d | 815 | * @param __BANK__: FMC_NAND Bank |
| group-onsemi | 0:098463de4c5d | 816 | * @param __FLAG__: FMC_NAND flag |
| group-onsemi | 0:098463de4c5d | 817 | * This parameter can be any combination of the following values: |
| group-onsemi | 0:098463de4c5d | 818 | * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| group-onsemi | 0:098463de4c5d | 819 | * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. |
| group-onsemi | 0:098463de4c5d | 820 | * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| group-onsemi | 0:098463de4c5d | 821 | * @arg FMC_FLAG_FEMPT: FIFO empty flag. |
| group-onsemi | 0:098463de4c5d | 822 | * @retval None |
| group-onsemi | 0:098463de4c5d | 823 | */ |
| group-onsemi | 0:098463de4c5d | 824 | #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR, (__FLAG__)) |
| group-onsemi | 0:098463de4c5d | 825 | |
| group-onsemi | 0:098463de4c5d | 826 | |
| group-onsemi | 0:098463de4c5d | 827 | /* Exported functions --------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 828 | /** @addgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions |
| group-onsemi | 0:098463de4c5d | 829 | * @{ |
| group-onsemi | 0:098463de4c5d | 830 | */ |
| group-onsemi | 0:098463de4c5d | 831 | |
| group-onsemi | 0:098463de4c5d | 832 | /* FMC_LL_NORSRAM Controller functions *******************************************/ |
| group-onsemi | 0:098463de4c5d | 833 | /** @addgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions |
| group-onsemi | 0:098463de4c5d | 834 | * @{ |
| group-onsemi | 0:098463de4c5d | 835 | */ |
| group-onsemi | 0:098463de4c5d | 836 | /* Initialization/de-initialization functions */ |
| group-onsemi | 0:098463de4c5d | 837 | HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); |
| group-onsemi | 0:098463de4c5d | 838 | HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); |
| group-onsemi | 0:098463de4c5d | 839 | HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); |
| group-onsemi | 0:098463de4c5d | 840 | HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); |
| group-onsemi | 0:098463de4c5d | 841 | /** |
| group-onsemi | 0:098463de4c5d | 842 | * @} |
| group-onsemi | 0:098463de4c5d | 843 | */ |
| group-onsemi | 0:098463de4c5d | 844 | |
| group-onsemi | 0:098463de4c5d | 845 | /** @addtogroup FMC_LL_NORSRAM_Exported_Functions_Group2 Peripheral Control functions |
| group-onsemi | 0:098463de4c5d | 846 | * @{ |
| group-onsemi | 0:098463de4c5d | 847 | */ |
| group-onsemi | 0:098463de4c5d | 848 | /* FMC_NORSRAM Control functions */ |
| group-onsemi | 0:098463de4c5d | 849 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| group-onsemi | 0:098463de4c5d | 850 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| group-onsemi | 0:098463de4c5d | 851 | /** |
| group-onsemi | 0:098463de4c5d | 852 | * @} |
| group-onsemi | 0:098463de4c5d | 853 | */ |
| group-onsemi | 0:098463de4c5d | 854 | |
| group-onsemi | 0:098463de4c5d | 855 | /* FMC_NAND Controller functions **********************************************/ |
| group-onsemi | 0:098463de4c5d | 856 | /** @addtogroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions |
| group-onsemi | 0:098463de4c5d | 857 | * @{ |
| group-onsemi | 0:098463de4c5d | 858 | */ |
| group-onsemi | 0:098463de4c5d | 859 | /* Initialization/de-initialization functions */ |
| group-onsemi | 0:098463de4c5d | 860 | HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); |
| group-onsemi | 0:098463de4c5d | 861 | HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| group-onsemi | 0:098463de4c5d | 862 | HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| group-onsemi | 0:098463de4c5d | 863 | HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); |
| group-onsemi | 0:098463de4c5d | 864 | /** |
| group-onsemi | 0:098463de4c5d | 865 | * @} |
| group-onsemi | 0:098463de4c5d | 866 | */ |
| group-onsemi | 0:098463de4c5d | 867 | |
| group-onsemi | 0:098463de4c5d | 868 | /** @defgroup FMC_LL_NAND_Exported_Functions_Group2 FMC Low Layer Peripheral Control functions |
| group-onsemi | 0:098463de4c5d | 869 | * @{ |
| group-onsemi | 0:098463de4c5d | 870 | */ |
| group-onsemi | 0:098463de4c5d | 871 | /* FMC_NAND Control functions */ |
| group-onsemi | 0:098463de4c5d | 872 | HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); |
| group-onsemi | 0:098463de4c5d | 873 | HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); |
| group-onsemi | 0:098463de4c5d | 874 | HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); |
| group-onsemi | 0:098463de4c5d | 875 | /** |
| group-onsemi | 0:098463de4c5d | 876 | * @} |
| group-onsemi | 0:098463de4c5d | 877 | */ |
| group-onsemi | 0:098463de4c5d | 878 | |
| group-onsemi | 0:098463de4c5d | 879 | /** |
| group-onsemi | 0:098463de4c5d | 880 | * @} |
| group-onsemi | 0:098463de4c5d | 881 | */ |
| group-onsemi | 0:098463de4c5d | 882 | |
| group-onsemi | 0:098463de4c5d | 883 | /** |
| group-onsemi | 0:098463de4c5d | 884 | * @} |
| group-onsemi | 0:098463de4c5d | 885 | */ |
| group-onsemi | 0:098463de4c5d | 886 | |
| group-onsemi | 0:098463de4c5d | 887 | /** |
| group-onsemi | 0:098463de4c5d | 888 | * @} |
| group-onsemi | 0:098463de4c5d | 889 | */ |
| group-onsemi | 0:098463de4c5d | 890 | |
| group-onsemi | 0:098463de4c5d | 891 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
| group-onsemi | 0:098463de4c5d | 892 | |
| group-onsemi | 0:098463de4c5d | 893 | #ifdef __cplusplus |
| group-onsemi | 0:098463de4c5d | 894 | } |
| group-onsemi | 0:098463de4c5d | 895 | #endif |
| group-onsemi | 0:098463de4c5d | 896 | |
| group-onsemi | 0:098463de4c5d | 897 | #endif /* __STM32L4xx_LL_FMC_H */ |
| group-onsemi | 0:098463de4c5d | 898 | |
| group-onsemi | 0:098463de4c5d | 899 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |