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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_adc.c@0:098463de4c5d, 2017-01-25 (annotated)
- Committer:
- group-onsemi
- Date:
- Wed Jan 25 20:34:15 2017 +0000
- Revision:
- 0:098463de4c5d
Initial commit
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| group-onsemi | 0:098463de4c5d | 1 | /** |
| group-onsemi | 0:098463de4c5d | 2 | ****************************************************************************** |
| group-onsemi | 0:098463de4c5d | 3 | * @file stm32l1xx_ll_adc.c |
| group-onsemi | 0:098463de4c5d | 4 | * @author MCD Application Team |
| group-onsemi | 0:098463de4c5d | 5 | * @version V1.2.0 |
| group-onsemi | 0:098463de4c5d | 6 | * @date 01-July-2016 |
| group-onsemi | 0:098463de4c5d | 7 | * @brief ADC LL module driver |
| group-onsemi | 0:098463de4c5d | 8 | ****************************************************************************** |
| group-onsemi | 0:098463de4c5d | 9 | * @attention |
| group-onsemi | 0:098463de4c5d | 10 | * |
| group-onsemi | 0:098463de4c5d | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| group-onsemi | 0:098463de4c5d | 12 | * |
| group-onsemi | 0:098463de4c5d | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| group-onsemi | 0:098463de4c5d | 14 | * are permitted provided that the following conditions are met: |
| group-onsemi | 0:098463de4c5d | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| group-onsemi | 0:098463de4c5d | 16 | * this list of conditions and the following disclaimer. |
| group-onsemi | 0:098463de4c5d | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| group-onsemi | 0:098463de4c5d | 18 | * this list of conditions and the following disclaimer in the documentation |
| group-onsemi | 0:098463de4c5d | 19 | * and/or other materials provided with the distribution. |
| group-onsemi | 0:098463de4c5d | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| group-onsemi | 0:098463de4c5d | 21 | * may be used to endorse or promote products derived from this software |
| group-onsemi | 0:098463de4c5d | 22 | * without specific prior written permission. |
| group-onsemi | 0:098463de4c5d | 23 | * |
| group-onsemi | 0:098463de4c5d | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| group-onsemi | 0:098463de4c5d | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| group-onsemi | 0:098463de4c5d | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| group-onsemi | 0:098463de4c5d | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| group-onsemi | 0:098463de4c5d | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| group-onsemi | 0:098463de4c5d | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| group-onsemi | 0:098463de4c5d | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| group-onsemi | 0:098463de4c5d | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| group-onsemi | 0:098463de4c5d | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| group-onsemi | 0:098463de4c5d | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| group-onsemi | 0:098463de4c5d | 34 | * |
| group-onsemi | 0:098463de4c5d | 35 | ****************************************************************************** |
| group-onsemi | 0:098463de4c5d | 36 | */ |
| group-onsemi | 0:098463de4c5d | 37 | #if defined(USE_FULL_LL_DRIVER) |
| group-onsemi | 0:098463de4c5d | 38 | |
| group-onsemi | 0:098463de4c5d | 39 | /* Includes ------------------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 40 | #include "stm32l1xx_ll_adc.h" |
| group-onsemi | 0:098463de4c5d | 41 | #include "stm32l1xx_ll_bus.h" |
| group-onsemi | 0:098463de4c5d | 42 | |
| group-onsemi | 0:098463de4c5d | 43 | #ifdef USE_FULL_ASSERT |
| group-onsemi | 0:098463de4c5d | 44 | #include "stm32_assert.h" |
| group-onsemi | 0:098463de4c5d | 45 | #else |
| group-onsemi | 0:098463de4c5d | 46 | #define assert_param(expr) ((void)0U) |
| group-onsemi | 0:098463de4c5d | 47 | #endif |
| group-onsemi | 0:098463de4c5d | 48 | |
| group-onsemi | 0:098463de4c5d | 49 | /** @addtogroup STM32L1xx_LL_Driver |
| group-onsemi | 0:098463de4c5d | 50 | * @{ |
| group-onsemi | 0:098463de4c5d | 51 | */ |
| group-onsemi | 0:098463de4c5d | 52 | |
| group-onsemi | 0:098463de4c5d | 53 | #if defined (ADC1) |
| group-onsemi | 0:098463de4c5d | 54 | |
| group-onsemi | 0:098463de4c5d | 55 | /** @addtogroup ADC_LL ADC |
| group-onsemi | 0:098463de4c5d | 56 | * @{ |
| group-onsemi | 0:098463de4c5d | 57 | */ |
| group-onsemi | 0:098463de4c5d | 58 | |
| group-onsemi | 0:098463de4c5d | 59 | /* Private types -------------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 60 | /* Private variables ---------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 61 | /* Private constants ---------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 62 | /* Private macros ------------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 63 | |
| group-onsemi | 0:098463de4c5d | 64 | /** @addtogroup ADC_LL_Private_Macros |
| group-onsemi | 0:098463de4c5d | 65 | * @{ |
| group-onsemi | 0:098463de4c5d | 66 | */ |
| group-onsemi | 0:098463de4c5d | 67 | |
| group-onsemi | 0:098463de4c5d | 68 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
| group-onsemi | 0:098463de4c5d | 69 | /* common to several ADC instances. */ |
| group-onsemi | 0:098463de4c5d | 70 | #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ |
| group-onsemi | 0:098463de4c5d | 71 | ( ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ |
| group-onsemi | 0:098463de4c5d | 72 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \ |
| group-onsemi | 0:098463de4c5d | 73 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \ |
| group-onsemi | 0:098463de4c5d | 74 | ) |
| group-onsemi | 0:098463de4c5d | 75 | |
| group-onsemi | 0:098463de4c5d | 76 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
| group-onsemi | 0:098463de4c5d | 77 | /* ADC instance. */ |
| group-onsemi | 0:098463de4c5d | 78 | #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ |
| group-onsemi | 0:098463de4c5d | 79 | ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ |
| group-onsemi | 0:098463de4c5d | 80 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ |
| group-onsemi | 0:098463de4c5d | 81 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ |
| group-onsemi | 0:098463de4c5d | 82 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ |
| group-onsemi | 0:098463de4c5d | 83 | ) |
| group-onsemi | 0:098463de4c5d | 84 | |
| group-onsemi | 0:098463de4c5d | 85 | #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ |
| group-onsemi | 0:098463de4c5d | 86 | ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ |
| group-onsemi | 0:098463de4c5d | 87 | || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ |
| group-onsemi | 0:098463de4c5d | 88 | ) |
| group-onsemi | 0:098463de4c5d | 89 | |
| group-onsemi | 0:098463de4c5d | 90 | #define IS_LL_ADC_LOW_POWER_AUTOWAIT(__LOW_POWER__) \ |
| group-onsemi | 0:098463de4c5d | 91 | ( ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_NONE) \ |
| group-onsemi | 0:098463de4c5d | 92 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ |
| group-onsemi | 0:098463de4c5d | 93 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES) \ |
| group-onsemi | 0:098463de4c5d | 94 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES) \ |
| group-onsemi | 0:098463de4c5d | 95 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES) \ |
| group-onsemi | 0:098463de4c5d | 96 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES) \ |
| group-onsemi | 0:098463de4c5d | 97 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES) \ |
| group-onsemi | 0:098463de4c5d | 98 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES) \ |
| group-onsemi | 0:098463de4c5d | 99 | ) |
| group-onsemi | 0:098463de4c5d | 100 | |
| group-onsemi | 0:098463de4c5d | 101 | #define IS_LL_ADC_LOW_POWER_AUTOPOWEROFF(__LOW_POWER__) \ |
| group-onsemi | 0:098463de4c5d | 102 | ( ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_NONE) \ |
| group-onsemi | 0:098463de4c5d | 103 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE) \ |
| group-onsemi | 0:098463de4c5d | 104 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE) \ |
| group-onsemi | 0:098463de4c5d | 105 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES) \ |
| group-onsemi | 0:098463de4c5d | 106 | ) |
| group-onsemi | 0:098463de4c5d | 107 | |
| group-onsemi | 0:098463de4c5d | 108 | #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \ |
| group-onsemi | 0:098463de4c5d | 109 | ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
| group-onsemi | 0:098463de4c5d | 110 | || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
| group-onsemi | 0:098463de4c5d | 111 | ) |
| group-onsemi | 0:098463de4c5d | 112 | |
| group-onsemi | 0:098463de4c5d | 113 | #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \ |
| group-onsemi | 0:098463de4c5d | 114 | ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
| group-onsemi | 0:098463de4c5d | 115 | || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
| group-onsemi | 0:098463de4c5d | 116 | ) |
| group-onsemi | 0:098463de4c5d | 117 | |
| group-onsemi | 0:098463de4c5d | 118 | #define IS_LL_ADC_CHANNELS_BANK(__CHANNELS_BANK__) \ |
| group-onsemi | 0:098463de4c5d | 119 | ( ((__CHANNELS_BANK__) == LL_ADC_CHANNELS_BANK_A) \ |
| group-onsemi | 0:098463de4c5d | 120 | || ((__CHANNELS_BANK__) == LL_ADC_CHANNELS_BANK_B) \ |
| group-onsemi | 0:098463de4c5d | 121 | ) |
| group-onsemi | 0:098463de4c5d | 122 | |
| group-onsemi | 0:098463de4c5d | 123 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
| group-onsemi | 0:098463de4c5d | 124 | /* ADC group regular */ |
| group-onsemi | 0:098463de4c5d | 125 | #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ |
| group-onsemi | 0:098463de4c5d | 126 | ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
| group-onsemi | 0:098463de4c5d | 127 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ |
| group-onsemi | 0:098463de4c5d | 128 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ |
| group-onsemi | 0:098463de4c5d | 129 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ |
| group-onsemi | 0:098463de4c5d | 130 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ |
| group-onsemi | 0:098463de4c5d | 131 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ |
| group-onsemi | 0:098463de4c5d | 132 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH3) \ |
| group-onsemi | 0:098463de4c5d | 133 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ |
| group-onsemi | 0:098463de4c5d | 134 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ |
| group-onsemi | 0:098463de4c5d | 135 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ |
| group-onsemi | 0:098463de4c5d | 136 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM9_CH2) \ |
| group-onsemi | 0:098463de4c5d | 137 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM9_TRGO) \ |
| group-onsemi | 0:098463de4c5d | 138 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ |
| group-onsemi | 0:098463de4c5d | 139 | ) |
| group-onsemi | 0:098463de4c5d | 140 | |
| group-onsemi | 0:098463de4c5d | 141 | #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ |
| group-onsemi | 0:098463de4c5d | 142 | ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ |
| group-onsemi | 0:098463de4c5d | 143 | || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ |
| group-onsemi | 0:098463de4c5d | 144 | ) |
| group-onsemi | 0:098463de4c5d | 145 | |
| group-onsemi | 0:098463de4c5d | 146 | #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ |
| group-onsemi | 0:098463de4c5d | 147 | ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ |
| group-onsemi | 0:098463de4c5d | 148 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ |
| group-onsemi | 0:098463de4c5d | 149 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ |
| group-onsemi | 0:098463de4c5d | 150 | ) |
| group-onsemi | 0:098463de4c5d | 151 | |
| group-onsemi | 0:098463de4c5d | 152 | #define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \ |
| group-onsemi | 0:098463de4c5d | 153 | ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \ |
| group-onsemi | 0:098463de4c5d | 154 | || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \ |
| group-onsemi | 0:098463de4c5d | 155 | ) |
| group-onsemi | 0:098463de4c5d | 156 | |
| group-onsemi | 0:098463de4c5d | 157 | #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ |
| group-onsemi | 0:098463de4c5d | 158 | ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ |
| group-onsemi | 0:098463de4c5d | 159 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ |
| group-onsemi | 0:098463de4c5d | 160 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ |
| group-onsemi | 0:098463de4c5d | 161 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ |
| group-onsemi | 0:098463de4c5d | 162 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ |
| group-onsemi | 0:098463de4c5d | 163 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ |
| group-onsemi | 0:098463de4c5d | 164 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ |
| group-onsemi | 0:098463de4c5d | 165 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ |
| group-onsemi | 0:098463de4c5d | 166 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ |
| group-onsemi | 0:098463de4c5d | 167 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ |
| group-onsemi | 0:098463de4c5d | 168 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ |
| group-onsemi | 0:098463de4c5d | 169 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ |
| group-onsemi | 0:098463de4c5d | 170 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ |
| group-onsemi | 0:098463de4c5d | 171 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ |
| group-onsemi | 0:098463de4c5d | 172 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ |
| group-onsemi | 0:098463de4c5d | 173 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ |
| group-onsemi | 0:098463de4c5d | 174 | ) |
| group-onsemi | 0:098463de4c5d | 175 | |
| group-onsemi | 0:098463de4c5d | 176 | #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ |
| group-onsemi | 0:098463de4c5d | 177 | ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ |
| group-onsemi | 0:098463de4c5d | 178 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ |
| group-onsemi | 0:098463de4c5d | 179 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ |
| group-onsemi | 0:098463de4c5d | 180 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ |
| group-onsemi | 0:098463de4c5d | 181 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ |
| group-onsemi | 0:098463de4c5d | 182 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ |
| group-onsemi | 0:098463de4c5d | 183 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ |
| group-onsemi | 0:098463de4c5d | 184 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ |
| group-onsemi | 0:098463de4c5d | 185 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ |
| group-onsemi | 0:098463de4c5d | 186 | ) |
| group-onsemi | 0:098463de4c5d | 187 | |
| group-onsemi | 0:098463de4c5d | 188 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
| group-onsemi | 0:098463de4c5d | 189 | /* ADC group injected */ |
| group-onsemi | 0:098463de4c5d | 190 | #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ |
| group-onsemi | 0:098463de4c5d | 191 | ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
| group-onsemi | 0:098463de4c5d | 192 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_CH1) \ |
| group-onsemi | 0:098463de4c5d | 193 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_TRGO) \ |
| group-onsemi | 0:098463de4c5d | 194 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ |
| group-onsemi | 0:098463de4c5d | 195 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ |
| group-onsemi | 0:098463de4c5d | 196 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ |
| group-onsemi | 0:098463de4c5d | 197 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ |
| group-onsemi | 0:098463de4c5d | 198 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \ |
| group-onsemi | 0:098463de4c5d | 199 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \ |
| group-onsemi | 0:098463de4c5d | 200 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ |
| group-onsemi | 0:098463de4c5d | 201 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM10_CH1) \ |
| group-onsemi | 0:098463de4c5d | 202 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ |
| group-onsemi | 0:098463de4c5d | 203 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ |
| group-onsemi | 0:098463de4c5d | 204 | ) |
| group-onsemi | 0:098463de4c5d | 205 | |
| group-onsemi | 0:098463de4c5d | 206 | #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ |
| group-onsemi | 0:098463de4c5d | 207 | ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ |
| group-onsemi | 0:098463de4c5d | 208 | || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ |
| group-onsemi | 0:098463de4c5d | 209 | || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ |
| group-onsemi | 0:098463de4c5d | 210 | ) |
| group-onsemi | 0:098463de4c5d | 211 | |
| group-onsemi | 0:098463de4c5d | 212 | #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ |
| group-onsemi | 0:098463de4c5d | 213 | ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ |
| group-onsemi | 0:098463de4c5d | 214 | || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ |
| group-onsemi | 0:098463de4c5d | 215 | ) |
| group-onsemi | 0:098463de4c5d | 216 | |
| group-onsemi | 0:098463de4c5d | 217 | #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ |
| group-onsemi | 0:098463de4c5d | 218 | ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ |
| group-onsemi | 0:098463de4c5d | 219 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ |
| group-onsemi | 0:098463de4c5d | 220 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ |
| group-onsemi | 0:098463de4c5d | 221 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ |
| group-onsemi | 0:098463de4c5d | 222 | ) |
| group-onsemi | 0:098463de4c5d | 223 | |
| group-onsemi | 0:098463de4c5d | 224 | #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ |
| group-onsemi | 0:098463de4c5d | 225 | ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ |
| group-onsemi | 0:098463de4c5d | 226 | || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ |
| group-onsemi | 0:098463de4c5d | 227 | ) |
| group-onsemi | 0:098463de4c5d | 228 | |
| group-onsemi | 0:098463de4c5d | 229 | /** |
| group-onsemi | 0:098463de4c5d | 230 | * @} |
| group-onsemi | 0:098463de4c5d | 231 | */ |
| group-onsemi | 0:098463de4c5d | 232 | |
| group-onsemi | 0:098463de4c5d | 233 | |
| group-onsemi | 0:098463de4c5d | 234 | /* Private function prototypes -----------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 235 | |
| group-onsemi | 0:098463de4c5d | 236 | /* Exported functions --------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 237 | /** @addtogroup ADC_LL_Exported_Functions |
| group-onsemi | 0:098463de4c5d | 238 | * @{ |
| group-onsemi | 0:098463de4c5d | 239 | */ |
| group-onsemi | 0:098463de4c5d | 240 | |
| group-onsemi | 0:098463de4c5d | 241 | /** @addtogroup ADC_LL_EF_Init |
| group-onsemi | 0:098463de4c5d | 242 | * @{ |
| group-onsemi | 0:098463de4c5d | 243 | */ |
| group-onsemi | 0:098463de4c5d | 244 | |
| group-onsemi | 0:098463de4c5d | 245 | /** |
| group-onsemi | 0:098463de4c5d | 246 | * @brief De-initialize registers of all ADC instances belonging to |
| group-onsemi | 0:098463de4c5d | 247 | * the same ADC common instance to their default reset values. |
| group-onsemi | 0:098463de4c5d | 248 | * @param ADCxy_COMMON ADC common instance |
| group-onsemi | 0:098463de4c5d | 249 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
| group-onsemi | 0:098463de4c5d | 250 | * @retval An ErrorStatus enumeration value: |
| group-onsemi | 0:098463de4c5d | 251 | * - SUCCESS: ADC common registers are de-initialized |
| group-onsemi | 0:098463de4c5d | 252 | * - ERROR: not applicable |
| group-onsemi | 0:098463de4c5d | 253 | */ |
| group-onsemi | 0:098463de4c5d | 254 | ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) |
| group-onsemi | 0:098463de4c5d | 255 | { |
| group-onsemi | 0:098463de4c5d | 256 | /* Check the parameters */ |
| group-onsemi | 0:098463de4c5d | 257 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
| group-onsemi | 0:098463de4c5d | 258 | |
| group-onsemi | 0:098463de4c5d | 259 | /* Force reset of ADC clock (core clock) */ |
| group-onsemi | 0:098463de4c5d | 260 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1); |
| group-onsemi | 0:098463de4c5d | 261 | |
| group-onsemi | 0:098463de4c5d | 262 | /* Release reset of ADC clock (core clock) */ |
| group-onsemi | 0:098463de4c5d | 263 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1); |
| group-onsemi | 0:098463de4c5d | 264 | |
| group-onsemi | 0:098463de4c5d | 265 | return SUCCESS; |
| group-onsemi | 0:098463de4c5d | 266 | } |
| group-onsemi | 0:098463de4c5d | 267 | |
| group-onsemi | 0:098463de4c5d | 268 | /** |
| group-onsemi | 0:098463de4c5d | 269 | * @brief Initialize some features of ADC common parameters |
| group-onsemi | 0:098463de4c5d | 270 | * (all ADC instances belonging to the same ADC common instance) |
| group-onsemi | 0:098463de4c5d | 271 | * and multimode (for devices with several ADC instances available). |
| group-onsemi | 0:098463de4c5d | 272 | * @note The setting of ADC common parameters is conditioned to |
| group-onsemi | 0:098463de4c5d | 273 | * ADC instances state: |
| group-onsemi | 0:098463de4c5d | 274 | * All ADC instances belonging to the same ADC common instance |
| group-onsemi | 0:098463de4c5d | 275 | * must be disabled. |
| group-onsemi | 0:098463de4c5d | 276 | * @param ADCxy_COMMON ADC common instance |
| group-onsemi | 0:098463de4c5d | 277 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
| group-onsemi | 0:098463de4c5d | 278 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
| group-onsemi | 0:098463de4c5d | 279 | * @retval An ErrorStatus enumeration value: |
| group-onsemi | 0:098463de4c5d | 280 | * - SUCCESS: ADC common registers are initialized |
| group-onsemi | 0:098463de4c5d | 281 | * - ERROR: ADC common registers are not initialized |
| group-onsemi | 0:098463de4c5d | 282 | */ |
| group-onsemi | 0:098463de4c5d | 283 | ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
| group-onsemi | 0:098463de4c5d | 284 | { |
| group-onsemi | 0:098463de4c5d | 285 | ErrorStatus status = SUCCESS; |
| group-onsemi | 0:098463de4c5d | 286 | |
| group-onsemi | 0:098463de4c5d | 287 | /* Check the parameters */ |
| group-onsemi | 0:098463de4c5d | 288 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
| group-onsemi | 0:098463de4c5d | 289 | assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); |
| group-onsemi | 0:098463de4c5d | 290 | |
| group-onsemi | 0:098463de4c5d | 291 | /* Note: Hardware constraint (refer to description of functions */ |
| group-onsemi | 0:098463de4c5d | 292 | /* "LL_ADC_SetCommonXXX()": */ |
| group-onsemi | 0:098463de4c5d | 293 | /* On this STM32 serie, setting of these features is conditioned to */ |
| group-onsemi | 0:098463de4c5d | 294 | /* ADC state: */ |
| group-onsemi | 0:098463de4c5d | 295 | /* All ADC instances of the ADC common group must be disabled. */ |
| group-onsemi | 0:098463de4c5d | 296 | if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) |
| group-onsemi | 0:098463de4c5d | 297 | { |
| group-onsemi | 0:098463de4c5d | 298 | /* Configuration of ADC hierarchical scope: */ |
| group-onsemi | 0:098463de4c5d | 299 | /* - common to several ADC */ |
| group-onsemi | 0:098463de4c5d | 300 | /* (all ADC instances belonging to the same ADC common instance) */ |
| group-onsemi | 0:098463de4c5d | 301 | /* - Set ADC clock (conversion clock) */ |
| group-onsemi | 0:098463de4c5d | 302 | LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); |
| group-onsemi | 0:098463de4c5d | 303 | } |
| group-onsemi | 0:098463de4c5d | 304 | else |
| group-onsemi | 0:098463de4c5d | 305 | { |
| group-onsemi | 0:098463de4c5d | 306 | /* Initialization error: One or several ADC instances belonging to */ |
| group-onsemi | 0:098463de4c5d | 307 | /* the same ADC common instance are not disabled. */ |
| group-onsemi | 0:098463de4c5d | 308 | status = ERROR; |
| group-onsemi | 0:098463de4c5d | 309 | } |
| group-onsemi | 0:098463de4c5d | 310 | |
| group-onsemi | 0:098463de4c5d | 311 | return status; |
| group-onsemi | 0:098463de4c5d | 312 | } |
| group-onsemi | 0:098463de4c5d | 313 | |
| group-onsemi | 0:098463de4c5d | 314 | /** |
| group-onsemi | 0:098463de4c5d | 315 | * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. |
| group-onsemi | 0:098463de4c5d | 316 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
| group-onsemi | 0:098463de4c5d | 317 | * whose fields will be set to default values. |
| group-onsemi | 0:098463de4c5d | 318 | * @retval None |
| group-onsemi | 0:098463de4c5d | 319 | */ |
| group-onsemi | 0:098463de4c5d | 320 | void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
| group-onsemi | 0:098463de4c5d | 321 | { |
| group-onsemi | 0:098463de4c5d | 322 | /* Set ADC_CommonInitStruct fields to default values */ |
| group-onsemi | 0:098463de4c5d | 323 | /* Set fields of ADC common */ |
| group-onsemi | 0:098463de4c5d | 324 | /* (all ADC instances belonging to the same ADC common instance) */ |
| group-onsemi | 0:098463de4c5d | 325 | ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2; |
| group-onsemi | 0:098463de4c5d | 326 | |
| group-onsemi | 0:098463de4c5d | 327 | } |
| group-onsemi | 0:098463de4c5d | 328 | |
| group-onsemi | 0:098463de4c5d | 329 | /** |
| group-onsemi | 0:098463de4c5d | 330 | * @brief De-initialize registers of the selected ADC instance |
| group-onsemi | 0:098463de4c5d | 331 | * to their default reset values. |
| group-onsemi | 0:098463de4c5d | 332 | * @note To reset all ADC instances quickly (perform a hard reset), |
| group-onsemi | 0:098463de4c5d | 333 | * use function @ref LL_ADC_CommonDeInit(). |
| group-onsemi | 0:098463de4c5d | 334 | * @param ADCx ADC instance |
| group-onsemi | 0:098463de4c5d | 335 | * @retval An ErrorStatus enumeration value: |
| group-onsemi | 0:098463de4c5d | 336 | * - SUCCESS: ADC registers are de-initialized |
| group-onsemi | 0:098463de4c5d | 337 | * - ERROR: ADC registers are not de-initialized |
| group-onsemi | 0:098463de4c5d | 338 | */ |
| group-onsemi | 0:098463de4c5d | 339 | ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) |
| group-onsemi | 0:098463de4c5d | 340 | { |
| group-onsemi | 0:098463de4c5d | 341 | ErrorStatus status = SUCCESS; |
| group-onsemi | 0:098463de4c5d | 342 | |
| group-onsemi | 0:098463de4c5d | 343 | /* Check the parameters */ |
| group-onsemi | 0:098463de4c5d | 344 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
| group-onsemi | 0:098463de4c5d | 345 | |
| group-onsemi | 0:098463de4c5d | 346 | /* Disable ADC instance if not already disabled. */ |
| group-onsemi | 0:098463de4c5d | 347 | if(LL_ADC_IsEnabled(ADCx) == 1U) |
| group-onsemi | 0:098463de4c5d | 348 | { |
| group-onsemi | 0:098463de4c5d | 349 | /* Set ADC group regular trigger source to SW start to ensure to not */ |
| group-onsemi | 0:098463de4c5d | 350 | /* have an external trigger event occurring during the conversion stop */ |
| group-onsemi | 0:098463de4c5d | 351 | /* ADC disable process. */ |
| group-onsemi | 0:098463de4c5d | 352 | LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); |
| group-onsemi | 0:098463de4c5d | 353 | |
| group-onsemi | 0:098463de4c5d | 354 | /* Set ADC group injected trigger source to SW start to ensure to not */ |
| group-onsemi | 0:098463de4c5d | 355 | /* have an external trigger event occurring during the conversion stop */ |
| group-onsemi | 0:098463de4c5d | 356 | /* ADC disable process. */ |
| group-onsemi | 0:098463de4c5d | 357 | LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); |
| group-onsemi | 0:098463de4c5d | 358 | |
| group-onsemi | 0:098463de4c5d | 359 | /* Disable the ADC instance */ |
| group-onsemi | 0:098463de4c5d | 360 | LL_ADC_Disable(ADCx); |
| group-onsemi | 0:098463de4c5d | 361 | } |
| group-onsemi | 0:098463de4c5d | 362 | |
| group-onsemi | 0:098463de4c5d | 363 | /* Check whether ADC state is compliant with expected state */ |
| group-onsemi | 0:098463de4c5d | 364 | /* (hardware requirements of bits state to reset registers below) */ |
| group-onsemi | 0:098463de4c5d | 365 | if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U) |
| group-onsemi | 0:098463de4c5d | 366 | { |
| group-onsemi | 0:098463de4c5d | 367 | /* ========== Reset ADC registers ========== */ |
| group-onsemi | 0:098463de4c5d | 368 | /* Reset register SR */ |
| group-onsemi | 0:098463de4c5d | 369 | CLEAR_BIT(ADCx->SR, |
| group-onsemi | 0:098463de4c5d | 370 | ( LL_ADC_FLAG_STRT |
| group-onsemi | 0:098463de4c5d | 371 | | LL_ADC_FLAG_JSTRT |
| group-onsemi | 0:098463de4c5d | 372 | | LL_ADC_FLAG_EOCS |
| group-onsemi | 0:098463de4c5d | 373 | | LL_ADC_FLAG_OVR |
| group-onsemi | 0:098463de4c5d | 374 | | LL_ADC_FLAG_JEOS |
| group-onsemi | 0:098463de4c5d | 375 | | LL_ADC_FLAG_AWD1 ) |
| group-onsemi | 0:098463de4c5d | 376 | ); |
| group-onsemi | 0:098463de4c5d | 377 | |
| group-onsemi | 0:098463de4c5d | 378 | /* Reset register CR1 */ |
| group-onsemi | 0:098463de4c5d | 379 | CLEAR_BIT(ADCx->CR1, |
| group-onsemi | 0:098463de4c5d | 380 | ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN |
| group-onsemi | 0:098463de4c5d | 381 | | ADC_CR1_JAWDEN | ADC_CR1_PDI | ADC_CR1_PDD |
| group-onsemi | 0:098463de4c5d | 382 | | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN |
| group-onsemi | 0:098463de4c5d | 383 | | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN |
| group-onsemi | 0:098463de4c5d | 384 | | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE |
| group-onsemi | 0:098463de4c5d | 385 | | ADC_CR1_AWDCH ) |
| group-onsemi | 0:098463de4c5d | 386 | ); |
| group-onsemi | 0:098463de4c5d | 387 | |
| group-onsemi | 0:098463de4c5d | 388 | /* Reset register CR2 */ |
| group-onsemi | 0:098463de4c5d | 389 | #if defined(ADC_CR2_CFG) |
| group-onsemi | 0:098463de4c5d | 390 | CLEAR_BIT(ADCx->CR2, |
| group-onsemi | 0:098463de4c5d | 391 | ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL |
| group-onsemi | 0:098463de4c5d | 392 | | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL |
| group-onsemi | 0:098463de4c5d | 393 | | ADC_CR2_ALIGN | ADC_CR2_EOCS |
| group-onsemi | 0:098463de4c5d | 394 | | ADC_CR2_DDS | ADC_CR2_DMA | ADC_CR2_DELS |
| group-onsemi | 0:098463de4c5d | 395 | | ADC_CR2_CFG | ADC_CR2_CONT | ADC_CR2_ADON ) |
| group-onsemi | 0:098463de4c5d | 396 | ); |
| group-onsemi | 0:098463de4c5d | 397 | #else |
| group-onsemi | 0:098463de4c5d | 398 | CLEAR_BIT(ADCx->CR2, |
| group-onsemi | 0:098463de4c5d | 399 | ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL |
| group-onsemi | 0:098463de4c5d | 400 | | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL |
| group-onsemi | 0:098463de4c5d | 401 | | ADC_CR2_ALIGN | ADC_CR2_EOCS |
| group-onsemi | 0:098463de4c5d | 402 | | ADC_CR2_DDS | ADC_CR2_DMA | ADC_CR2_DELS |
| group-onsemi | 0:098463de4c5d | 403 | | ADC_CR2_CONT | ADC_CR2_ADON ) |
| group-onsemi | 0:098463de4c5d | 404 | ); |
| group-onsemi | 0:098463de4c5d | 405 | #endif /* ADC_CR2_CFG */ |
| group-onsemi | 0:098463de4c5d | 406 | |
| group-onsemi | 0:098463de4c5d | 407 | /* Reset register SMPR1 */ |
| group-onsemi | 0:098463de4c5d | 408 | /* Note: On STM32L1, ADC channels 27, 28, 29, 30, 31 are not available */ |
| group-onsemi | 0:098463de4c5d | 409 | /* on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
| group-onsemi | 0:098463de4c5d | 410 | #if defined(ADC_SMPR0_SMP31) |
| group-onsemi | 0:098463de4c5d | 411 | CLEAR_BIT(ADCx->SMPR1, |
| group-onsemi | 0:098463de4c5d | 412 | ( ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27 |
| group-onsemi | 0:098463de4c5d | 413 | | ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 |
| group-onsemi | 0:098463de4c5d | 414 | | ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 |
| group-onsemi | 0:098463de4c5d | 415 | | ADC_SMPR1_SMP20 ) |
| group-onsemi | 0:098463de4c5d | 416 | ); |
| group-onsemi | 0:098463de4c5d | 417 | #else |
| group-onsemi | 0:098463de4c5d | 418 | CLEAR_BIT(ADCx->SMPR1, |
| group-onsemi | 0:098463de4c5d | 419 | ( ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 |
| group-onsemi | 0:098463de4c5d | 420 | | ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 |
| group-onsemi | 0:098463de4c5d | 421 | | ADC_SMPR1_SMP20 ) |
| group-onsemi | 0:098463de4c5d | 422 | ); |
| group-onsemi | 0:098463de4c5d | 423 | #endif /* ADC_SMPR0_SMP31 */ |
| group-onsemi | 0:098463de4c5d | 424 | |
| group-onsemi | 0:098463de4c5d | 425 | /* Reset register SMPR2 */ |
| group-onsemi | 0:098463de4c5d | 426 | CLEAR_BIT(ADCx->SMPR2, |
| group-onsemi | 0:098463de4c5d | 427 | ( ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 |
| group-onsemi | 0:098463de4c5d | 428 | | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 |
| group-onsemi | 0:098463de4c5d | 429 | | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 |
| group-onsemi | 0:098463de4c5d | 430 | | ADC_SMPR2_SMP10 ) |
| group-onsemi | 0:098463de4c5d | 431 | ); |
| group-onsemi | 0:098463de4c5d | 432 | |
| group-onsemi | 0:098463de4c5d | 433 | /* Reset register SMPR3 */ |
| group-onsemi | 0:098463de4c5d | 434 | CLEAR_BIT(ADCx->SMPR3, |
| group-onsemi | 0:098463de4c5d | 435 | ( ADC_SMPR3_SMP9 | ADC_SMPR3_SMP8 | ADC_SMPR3_SMP7 |
| group-onsemi | 0:098463de4c5d | 436 | | ADC_SMPR3_SMP6 | ADC_SMPR3_SMP5 | ADC_SMPR3_SMP4 |
| group-onsemi | 0:098463de4c5d | 437 | | ADC_SMPR3_SMP3 | ADC_SMPR3_SMP2 | ADC_SMPR3_SMP1 |
| group-onsemi | 0:098463de4c5d | 438 | | ADC_SMPR3_SMP0 ) |
| group-onsemi | 0:098463de4c5d | 439 | ); |
| group-onsemi | 0:098463de4c5d | 440 | |
| group-onsemi | 0:098463de4c5d | 441 | #if defined(ADC_SMPR0_SMP31) |
| group-onsemi | 0:098463de4c5d | 442 | /* Reset register SMPR0 */ |
| group-onsemi | 0:098463de4c5d | 443 | CLEAR_BIT(ADCx->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30)); |
| group-onsemi | 0:098463de4c5d | 444 | #endif /* ADC_SMPR0_SMP31 */ |
| group-onsemi | 0:098463de4c5d | 445 | |
| group-onsemi | 0:098463de4c5d | 446 | /* Reset register JOFR1 */ |
| group-onsemi | 0:098463de4c5d | 447 | CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1); |
| group-onsemi | 0:098463de4c5d | 448 | /* Reset register JOFR2 */ |
| group-onsemi | 0:098463de4c5d | 449 | CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2); |
| group-onsemi | 0:098463de4c5d | 450 | /* Reset register JOFR3 */ |
| group-onsemi | 0:098463de4c5d | 451 | CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3); |
| group-onsemi | 0:098463de4c5d | 452 | /* Reset register JOFR4 */ |
| group-onsemi | 0:098463de4c5d | 453 | CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4); |
| group-onsemi | 0:098463de4c5d | 454 | |
| group-onsemi | 0:098463de4c5d | 455 | /* Reset register HTR */ |
| group-onsemi | 0:098463de4c5d | 456 | SET_BIT(ADCx->HTR, ADC_HTR_HT); |
| group-onsemi | 0:098463de4c5d | 457 | /* Reset register LTR */ |
| group-onsemi | 0:098463de4c5d | 458 | CLEAR_BIT(ADCx->LTR, ADC_LTR_LT); |
| group-onsemi | 0:098463de4c5d | 459 | |
| group-onsemi | 0:098463de4c5d | 460 | /* Reset register SQR1 */ |
| group-onsemi | 0:098463de4c5d | 461 | CLEAR_BIT(ADCx->SQR1, |
| group-onsemi | 0:098463de4c5d | 462 | ( ADC_SQR1_L |
| group-onsemi | 0:098463de4c5d | 463 | #if defined(ADC_SQR1_SQ28) |
| group-onsemi | 0:098463de4c5d | 464 | | ADC_SQR1_SQ28 | ADC_SQR1_SQ27 |
| group-onsemi | 0:098463de4c5d | 465 | #endif |
| group-onsemi | 0:098463de4c5d | 466 | | ADC_SQR1_SQ26 | ADC_SQR1_SQ25) |
| group-onsemi | 0:098463de4c5d | 467 | ); |
| group-onsemi | 0:098463de4c5d | 468 | |
| group-onsemi | 0:098463de4c5d | 469 | /* Reset register SQR2 */ |
| group-onsemi | 0:098463de4c5d | 470 | CLEAR_BIT(ADCx->SQR2, |
| group-onsemi | 0:098463de4c5d | 471 | ( ADC_SQR2_SQ24 | ADC_SQR2_SQ23 | ADC_SQR2_SQ22 |
| group-onsemi | 0:098463de4c5d | 472 | | ADC_SQR2_SQ21 | ADC_SQR2_SQ20 | ADC_SQR2_SQ19) |
| group-onsemi | 0:098463de4c5d | 473 | ); |
| group-onsemi | 0:098463de4c5d | 474 | |
| group-onsemi | 0:098463de4c5d | 475 | /* Reset register SQR3 */ |
| group-onsemi | 0:098463de4c5d | 476 | CLEAR_BIT(ADCx->SQR3, |
| group-onsemi | 0:098463de4c5d | 477 | ( ADC_SQR3_SQ18 | ADC_SQR3_SQ17 | ADC_SQR3_SQ16 |
| group-onsemi | 0:098463de4c5d | 478 | | ADC_SQR3_SQ15 | ADC_SQR3_SQ14 | ADC_SQR3_SQ13) |
| group-onsemi | 0:098463de4c5d | 479 | ); |
| group-onsemi | 0:098463de4c5d | 480 | |
| group-onsemi | 0:098463de4c5d | 481 | /* Reset register SQR4 */ |
| group-onsemi | 0:098463de4c5d | 482 | CLEAR_BIT(ADCx->SQR4, |
| group-onsemi | 0:098463de4c5d | 483 | ( ADC_SQR4_SQ12 | ADC_SQR4_SQ11 | ADC_SQR4_SQ10 |
| group-onsemi | 0:098463de4c5d | 484 | | ADC_SQR4_SQ9 | ADC_SQR4_SQ8 | ADC_SQR4_SQ7 ) |
| group-onsemi | 0:098463de4c5d | 485 | ); |
| group-onsemi | 0:098463de4c5d | 486 | |
| group-onsemi | 0:098463de4c5d | 487 | /* Reset register SQR5 */ |
| group-onsemi | 0:098463de4c5d | 488 | CLEAR_BIT(ADCx->SQR5, |
| group-onsemi | 0:098463de4c5d | 489 | ( ADC_SQR5_SQ6 | ADC_SQR5_SQ5 | ADC_SQR5_SQ4 |
| group-onsemi | 0:098463de4c5d | 490 | | ADC_SQR5_SQ3 | ADC_SQR5_SQ2 | ADC_SQR5_SQ1 ) |
| group-onsemi | 0:098463de4c5d | 491 | ); |
| group-onsemi | 0:098463de4c5d | 492 | |
| group-onsemi | 0:098463de4c5d | 493 | |
| group-onsemi | 0:098463de4c5d | 494 | /* Reset register JSQR */ |
| group-onsemi | 0:098463de4c5d | 495 | CLEAR_BIT(ADCx->JSQR, |
| group-onsemi | 0:098463de4c5d | 496 | ( ADC_JSQR_JL |
| group-onsemi | 0:098463de4c5d | 497 | | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
| group-onsemi | 0:098463de4c5d | 498 | | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) |
| group-onsemi | 0:098463de4c5d | 499 | ); |
| group-onsemi | 0:098463de4c5d | 500 | |
| group-onsemi | 0:098463de4c5d | 501 | /* Reset register DR */ |
| group-onsemi | 0:098463de4c5d | 502 | /* bits in access mode read only, no direct reset applicable */ |
| group-onsemi | 0:098463de4c5d | 503 | |
| group-onsemi | 0:098463de4c5d | 504 | /* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
| group-onsemi | 0:098463de4c5d | 505 | /* bits in access mode read only, no direct reset applicable */ |
| group-onsemi | 0:098463de4c5d | 506 | |
| group-onsemi | 0:098463de4c5d | 507 | /* Reset register CCR */ |
| group-onsemi | 0:098463de4c5d | 508 | CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE); |
| group-onsemi | 0:098463de4c5d | 509 | } |
| group-onsemi | 0:098463de4c5d | 510 | |
| group-onsemi | 0:098463de4c5d | 511 | return status; |
| group-onsemi | 0:098463de4c5d | 512 | } |
| group-onsemi | 0:098463de4c5d | 513 | |
| group-onsemi | 0:098463de4c5d | 514 | /** |
| group-onsemi | 0:098463de4c5d | 515 | * @brief Initialize some features of ADC instance. |
| group-onsemi | 0:098463de4c5d | 516 | * @note These parameters have an impact on ADC scope: ADC instance. |
| group-onsemi | 0:098463de4c5d | 517 | * Affects both group regular and group injected (availability |
| group-onsemi | 0:098463de4c5d | 518 | * of ADC group injected depends on STM32 families). |
| group-onsemi | 0:098463de4c5d | 519 | * Refer to corresponding unitary functions into |
| group-onsemi | 0:098463de4c5d | 520 | * @ref ADC_LL_EF_Configuration_ADC_Instance . |
| group-onsemi | 0:098463de4c5d | 521 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
| group-onsemi | 0:098463de4c5d | 522 | * is conditioned to ADC state: |
| group-onsemi | 0:098463de4c5d | 523 | * ADC instance must be disabled. |
| group-onsemi | 0:098463de4c5d | 524 | * This condition is applied to all ADC features, for efficiency |
| group-onsemi | 0:098463de4c5d | 525 | * and compatibility over all STM32 families. However, the different |
| group-onsemi | 0:098463de4c5d | 526 | * features can be set under different ADC state conditions |
| group-onsemi | 0:098463de4c5d | 527 | * (setting possible with ADC enabled without conversion on going, |
| group-onsemi | 0:098463de4c5d | 528 | * ADC enabled with conversion on going, ...) |
| group-onsemi | 0:098463de4c5d | 529 | * Each feature can be updated afterwards with a unitary function |
| group-onsemi | 0:098463de4c5d | 530 | * and potentially with ADC in a different state than disabled, |
| group-onsemi | 0:098463de4c5d | 531 | * refer to description of each function for setting |
| group-onsemi | 0:098463de4c5d | 532 | * conditioned to ADC state. |
| group-onsemi | 0:098463de4c5d | 533 | * @note After using this function, some other features must be configured |
| group-onsemi | 0:098463de4c5d | 534 | * using LL unitary functions. |
| group-onsemi | 0:098463de4c5d | 535 | * The minimum configuration remaining to be done is: |
| group-onsemi | 0:098463de4c5d | 536 | * - Set ADC group regular or group injected sequencer: |
| group-onsemi | 0:098463de4c5d | 537 | * map channel on the selected sequencer rank. |
| group-onsemi | 0:098463de4c5d | 538 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
| group-onsemi | 0:098463de4c5d | 539 | * - Set ADC channel sampling time |
| group-onsemi | 0:098463de4c5d | 540 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
| group-onsemi | 0:098463de4c5d | 541 | * @param ADCx ADC instance |
| group-onsemi | 0:098463de4c5d | 542 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
| group-onsemi | 0:098463de4c5d | 543 | * @retval An ErrorStatus enumeration value: |
| group-onsemi | 0:098463de4c5d | 544 | * - SUCCESS: ADC registers are initialized |
| group-onsemi | 0:098463de4c5d | 545 | * - ERROR: ADC registers are not initialized |
| group-onsemi | 0:098463de4c5d | 546 | */ |
| group-onsemi | 0:098463de4c5d | 547 | ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) |
| group-onsemi | 0:098463de4c5d | 548 | { |
| group-onsemi | 0:098463de4c5d | 549 | ErrorStatus status = SUCCESS; |
| group-onsemi | 0:098463de4c5d | 550 | |
| group-onsemi | 0:098463de4c5d | 551 | /* Check the parameters */ |
| group-onsemi | 0:098463de4c5d | 552 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
| group-onsemi | 0:098463de4c5d | 553 | |
| group-onsemi | 0:098463de4c5d | 554 | assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); |
| group-onsemi | 0:098463de4c5d | 555 | assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); |
| group-onsemi | 0:098463de4c5d | 556 | /* Note: On STM32L1, low power feature is set by concatenating */ |
| group-onsemi | 0:098463de4c5d | 557 | /* values of @ref ADC_LL_EC_LP_MODE_AUTOWAIT */ |
| group-onsemi | 0:098463de4c5d | 558 | /* and @ref ADC_LL_EC_LP_MODE_AUTOPOWEROFF. */ |
| group-onsemi | 0:098463de4c5d | 559 | /* Check of the parameter is done for each of group of values, */ |
| group-onsemi | 0:098463de4c5d | 560 | /* by excluding the other group of values. */ |
| group-onsemi | 0:098463de4c5d | 561 | assert_param(IS_LL_ADC_LOW_POWER_AUTOWAIT(ADC_InitStruct->LowPowerMode & ~(ADC_CR1_PDI | ADC_CR1_PDD))); |
| group-onsemi | 0:098463de4c5d | 562 | assert_param(IS_LL_ADC_LOW_POWER_AUTOPOWEROFF(ADC_InitStruct->LowPowerMode & ~(ADC_CR2_DELS))); |
| group-onsemi | 0:098463de4c5d | 563 | assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode)); |
| group-onsemi | 0:098463de4c5d | 564 | |
| group-onsemi | 0:098463de4c5d | 565 | /* Note: Hardware constraint (refer to description of this function): */ |
| group-onsemi | 0:098463de4c5d | 566 | /* ADC instance must be disabled. */ |
| group-onsemi | 0:098463de4c5d | 567 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
| group-onsemi | 0:098463de4c5d | 568 | { |
| group-onsemi | 0:098463de4c5d | 569 | /* Configuration of ADC hierarchical scope: */ |
| group-onsemi | 0:098463de4c5d | 570 | /* - ADC instance */ |
| group-onsemi | 0:098463de4c5d | 571 | /* - Set ADC data resolution */ |
| group-onsemi | 0:098463de4c5d | 572 | /* - Set ADC conversion data alignment */ |
| group-onsemi | 0:098463de4c5d | 573 | /* - Set ADC low power mode */ |
| group-onsemi | 0:098463de4c5d | 574 | MODIFY_REG(ADCx->CR1, |
| group-onsemi | 0:098463de4c5d | 575 | ADC_CR1_RES |
| group-onsemi | 0:098463de4c5d | 576 | | ADC_CR1_PDI |
| group-onsemi | 0:098463de4c5d | 577 | | ADC_CR1_PDD |
| group-onsemi | 0:098463de4c5d | 578 | | ADC_CR1_SCAN |
| group-onsemi | 0:098463de4c5d | 579 | , |
| group-onsemi | 0:098463de4c5d | 580 | ADC_InitStruct->Resolution |
| group-onsemi | 0:098463de4c5d | 581 | | (ADC_InitStruct->LowPowerMode & (ADC_CR1_PDI | ADC_CR1_PDD)) |
| group-onsemi | 0:098463de4c5d | 582 | | ADC_InitStruct->SequencersScanMode |
| group-onsemi | 0:098463de4c5d | 583 | ); |
| group-onsemi | 0:098463de4c5d | 584 | |
| group-onsemi | 0:098463de4c5d | 585 | MODIFY_REG(ADCx->CR2, |
| group-onsemi | 0:098463de4c5d | 586 | ADC_CR2_ALIGN |
| group-onsemi | 0:098463de4c5d | 587 | | ADC_CR2_DELS |
| group-onsemi | 0:098463de4c5d | 588 | , |
| group-onsemi | 0:098463de4c5d | 589 | ADC_InitStruct->DataAlignment |
| group-onsemi | 0:098463de4c5d | 590 | | (ADC_InitStruct->LowPowerMode & ADC_CR2_DELS) |
| group-onsemi | 0:098463de4c5d | 591 | ); |
| group-onsemi | 0:098463de4c5d | 592 | |
| group-onsemi | 0:098463de4c5d | 593 | } |
| group-onsemi | 0:098463de4c5d | 594 | else |
| group-onsemi | 0:098463de4c5d | 595 | { |
| group-onsemi | 0:098463de4c5d | 596 | /* Initialization error: ADC instance is not disabled. */ |
| group-onsemi | 0:098463de4c5d | 597 | status = ERROR; |
| group-onsemi | 0:098463de4c5d | 598 | } |
| group-onsemi | 0:098463de4c5d | 599 | return status; |
| group-onsemi | 0:098463de4c5d | 600 | } |
| group-onsemi | 0:098463de4c5d | 601 | |
| group-onsemi | 0:098463de4c5d | 602 | /** |
| group-onsemi | 0:098463de4c5d | 603 | * @brief Set each @ref LL_ADC_InitTypeDef field to default value. |
| group-onsemi | 0:098463de4c5d | 604 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure |
| group-onsemi | 0:098463de4c5d | 605 | * whose fields will be set to default values. |
| group-onsemi | 0:098463de4c5d | 606 | * @retval None |
| group-onsemi | 0:098463de4c5d | 607 | */ |
| group-onsemi | 0:098463de4c5d | 608 | void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) |
| group-onsemi | 0:098463de4c5d | 609 | { |
| group-onsemi | 0:098463de4c5d | 610 | /* Set ADC_InitStruct fields to default values */ |
| group-onsemi | 0:098463de4c5d | 611 | /* Set fields of ADC instance */ |
| group-onsemi | 0:098463de4c5d | 612 | ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; |
| group-onsemi | 0:098463de4c5d | 613 | ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; |
| group-onsemi | 0:098463de4c5d | 614 | ADC_InitStruct->LowPowerMode = (LL_ADC_LP_AUTOWAIT_NONE | LL_ADC_LP_AUTOPOWEROFF_NONE); |
| group-onsemi | 0:098463de4c5d | 615 | |
| group-onsemi | 0:098463de4c5d | 616 | /* Enable scan mode to have a generic behavior with ADC of other */ |
| group-onsemi | 0:098463de4c5d | 617 | /* STM32 families, without this setting available: */ |
| group-onsemi | 0:098463de4c5d | 618 | /* ADC group regular sequencer and ADC group injected sequencer depend */ |
| group-onsemi | 0:098463de4c5d | 619 | /* only of their own configuration. */ |
| group-onsemi | 0:098463de4c5d | 620 | ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE; |
| group-onsemi | 0:098463de4c5d | 621 | |
| group-onsemi | 0:098463de4c5d | 622 | } |
| group-onsemi | 0:098463de4c5d | 623 | |
| group-onsemi | 0:098463de4c5d | 624 | /** |
| group-onsemi | 0:098463de4c5d | 625 | * @brief Initialize some features of ADC group regular. |
| group-onsemi | 0:098463de4c5d | 626 | * @note These parameters have an impact on ADC scope: ADC group regular. |
| group-onsemi | 0:098463de4c5d | 627 | * Refer to corresponding unitary functions into |
| group-onsemi | 0:098463de4c5d | 628 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
| group-onsemi | 0:098463de4c5d | 629 | * (functions with prefix "REG"). |
| group-onsemi | 0:098463de4c5d | 630 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
| group-onsemi | 0:098463de4c5d | 631 | * is conditioned to ADC state: |
| group-onsemi | 0:098463de4c5d | 632 | * ADC instance must be disabled. |
| group-onsemi | 0:098463de4c5d | 633 | * This condition is applied to all ADC features, for efficiency |
| group-onsemi | 0:098463de4c5d | 634 | * and compatibility over all STM32 families. However, the different |
| group-onsemi | 0:098463de4c5d | 635 | * features can be set under different ADC state conditions |
| group-onsemi | 0:098463de4c5d | 636 | * (setting possible with ADC enabled without conversion on going, |
| group-onsemi | 0:098463de4c5d | 637 | * ADC enabled with conversion on going, ...) |
| group-onsemi | 0:098463de4c5d | 638 | * Each feature can be updated afterwards with a unitary function |
| group-onsemi | 0:098463de4c5d | 639 | * and potentially with ADC in a different state than disabled, |
| group-onsemi | 0:098463de4c5d | 640 | * refer to description of each function for setting |
| group-onsemi | 0:098463de4c5d | 641 | * conditioned to ADC state. |
| group-onsemi | 0:098463de4c5d | 642 | * @note After using this function, other features must be configured |
| group-onsemi | 0:098463de4c5d | 643 | * using LL unitary functions. |
| group-onsemi | 0:098463de4c5d | 644 | * The minimum configuration remaining to be done is: |
| group-onsemi | 0:098463de4c5d | 645 | * - Set ADC group regular or group injected sequencer: |
| group-onsemi | 0:098463de4c5d | 646 | * map channel on the selected sequencer rank. |
| group-onsemi | 0:098463de4c5d | 647 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
| group-onsemi | 0:098463de4c5d | 648 | * - Set ADC channel sampling time |
| group-onsemi | 0:098463de4c5d | 649 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
| group-onsemi | 0:098463de4c5d | 650 | * @param ADCx ADC instance |
| group-onsemi | 0:098463de4c5d | 651 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
| group-onsemi | 0:098463de4c5d | 652 | * @retval An ErrorStatus enumeration value: |
| group-onsemi | 0:098463de4c5d | 653 | * - SUCCESS: ADC registers are initialized |
| group-onsemi | 0:098463de4c5d | 654 | * - ERROR: ADC registers are not initialized |
| group-onsemi | 0:098463de4c5d | 655 | */ |
| group-onsemi | 0:098463de4c5d | 656 | ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
| group-onsemi | 0:098463de4c5d | 657 | { |
| group-onsemi | 0:098463de4c5d | 658 | ErrorStatus status = SUCCESS; |
| group-onsemi | 0:098463de4c5d | 659 | |
| group-onsemi | 0:098463de4c5d | 660 | /* Check the parameters */ |
| group-onsemi | 0:098463de4c5d | 661 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
| group-onsemi | 0:098463de4c5d | 662 | assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); |
| group-onsemi | 0:098463de4c5d | 663 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); |
| group-onsemi | 0:098463de4c5d | 664 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
| group-onsemi | 0:098463de4c5d | 665 | { |
| group-onsemi | 0:098463de4c5d | 666 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); |
| group-onsemi | 0:098463de4c5d | 667 | } |
| group-onsemi | 0:098463de4c5d | 668 | assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); |
| group-onsemi | 0:098463de4c5d | 669 | assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); |
| group-onsemi | 0:098463de4c5d | 670 | |
| group-onsemi | 0:098463de4c5d | 671 | /* Note: Hardware constraint (refer to description of this function): */ |
| group-onsemi | 0:098463de4c5d | 672 | /* ADC instance must be disabled. */ |
| group-onsemi | 0:098463de4c5d | 673 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
| group-onsemi | 0:098463de4c5d | 674 | { |
| group-onsemi | 0:098463de4c5d | 675 | /* Configuration of ADC hierarchical scope: */ |
| group-onsemi | 0:098463de4c5d | 676 | /* - ADC group regular */ |
| group-onsemi | 0:098463de4c5d | 677 | /* - Set ADC group regular trigger source */ |
| group-onsemi | 0:098463de4c5d | 678 | /* - Set ADC group regular sequencer length */ |
| group-onsemi | 0:098463de4c5d | 679 | /* - Set ADC group regular sequencer discontinuous mode */ |
| group-onsemi | 0:098463de4c5d | 680 | /* - Set ADC group regular continuous mode */ |
| group-onsemi | 0:098463de4c5d | 681 | /* - Set ADC group regular conversion data transfer: no transfer or */ |
| group-onsemi | 0:098463de4c5d | 682 | /* transfer by DMA, and DMA requests mode */ |
| group-onsemi | 0:098463de4c5d | 683 | /* Note: On this STM32 serie, ADC trigger edge is set when starting */ |
| group-onsemi | 0:098463de4c5d | 684 | /* ADC conversion. */ |
| group-onsemi | 0:098463de4c5d | 685 | /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
| group-onsemi | 0:098463de4c5d | 686 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
| group-onsemi | 0:098463de4c5d | 687 | { |
| group-onsemi | 0:098463de4c5d | 688 | MODIFY_REG(ADCx->CR1, |
| group-onsemi | 0:098463de4c5d | 689 | ADC_CR1_DISCEN |
| group-onsemi | 0:098463de4c5d | 690 | | ADC_CR1_DISCNUM |
| group-onsemi | 0:098463de4c5d | 691 | , |
| group-onsemi | 0:098463de4c5d | 692 | ADC_REG_InitStruct->SequencerLength |
| group-onsemi | 0:098463de4c5d | 693 | | ADC_REG_InitStruct->SequencerDiscont |
| group-onsemi | 0:098463de4c5d | 694 | ); |
| group-onsemi | 0:098463de4c5d | 695 | } |
| group-onsemi | 0:098463de4c5d | 696 | else |
| group-onsemi | 0:098463de4c5d | 697 | { |
| group-onsemi | 0:098463de4c5d | 698 | MODIFY_REG(ADCx->CR1, |
| group-onsemi | 0:098463de4c5d | 699 | ADC_CR1_DISCEN |
| group-onsemi | 0:098463de4c5d | 700 | | ADC_CR1_DISCNUM |
| group-onsemi | 0:098463de4c5d | 701 | , |
| group-onsemi | 0:098463de4c5d | 702 | ADC_REG_InitStruct->SequencerLength |
| group-onsemi | 0:098463de4c5d | 703 | | LL_ADC_REG_SEQ_DISCONT_DISABLE |
| group-onsemi | 0:098463de4c5d | 704 | ); |
| group-onsemi | 0:098463de4c5d | 705 | } |
| group-onsemi | 0:098463de4c5d | 706 | |
| group-onsemi | 0:098463de4c5d | 707 | MODIFY_REG(ADCx->CR2, |
| group-onsemi | 0:098463de4c5d | 708 | ADC_CR2_EXTSEL |
| group-onsemi | 0:098463de4c5d | 709 | | ADC_CR2_EXTEN |
| group-onsemi | 0:098463de4c5d | 710 | | ADC_CR2_CONT |
| group-onsemi | 0:098463de4c5d | 711 | | ADC_CR2_DMA |
| group-onsemi | 0:098463de4c5d | 712 | | ADC_CR2_DDS |
| group-onsemi | 0:098463de4c5d | 713 | , |
| group-onsemi | 0:098463de4c5d | 714 | (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) |
| group-onsemi | 0:098463de4c5d | 715 | | ADC_REG_InitStruct->ContinuousMode |
| group-onsemi | 0:098463de4c5d | 716 | | ADC_REG_InitStruct->DMATransfer |
| group-onsemi | 0:098463de4c5d | 717 | ); |
| group-onsemi | 0:098463de4c5d | 718 | |
| group-onsemi | 0:098463de4c5d | 719 | /* Set ADC group regular sequencer length and scan direction */ |
| group-onsemi | 0:098463de4c5d | 720 | /* Note: Hardware constraint (refer to description of this function): */ |
| group-onsemi | 0:098463de4c5d | 721 | /* Note: If ADC instance feature scan mode is disabled */ |
| group-onsemi | 0:098463de4c5d | 722 | /* (refer to ADC instance initialization structure */ |
| group-onsemi | 0:098463de4c5d | 723 | /* parameter @ref SequencersScanMode */ |
| group-onsemi | 0:098463de4c5d | 724 | /* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
| group-onsemi | 0:098463de4c5d | 725 | /* this parameter is discarded. */ |
| group-onsemi | 0:098463de4c5d | 726 | LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); |
| group-onsemi | 0:098463de4c5d | 727 | } |
| group-onsemi | 0:098463de4c5d | 728 | else |
| group-onsemi | 0:098463de4c5d | 729 | { |
| group-onsemi | 0:098463de4c5d | 730 | /* Initialization error: ADC instance is not disabled. */ |
| group-onsemi | 0:098463de4c5d | 731 | status = ERROR; |
| group-onsemi | 0:098463de4c5d | 732 | } |
| group-onsemi | 0:098463de4c5d | 733 | return status; |
| group-onsemi | 0:098463de4c5d | 734 | } |
| group-onsemi | 0:098463de4c5d | 735 | |
| group-onsemi | 0:098463de4c5d | 736 | /** |
| group-onsemi | 0:098463de4c5d | 737 | * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. |
| group-onsemi | 0:098463de4c5d | 738 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
| group-onsemi | 0:098463de4c5d | 739 | * whose fields will be set to default values. |
| group-onsemi | 0:098463de4c5d | 740 | * @retval None |
| group-onsemi | 0:098463de4c5d | 741 | */ |
| group-onsemi | 0:098463de4c5d | 742 | void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
| group-onsemi | 0:098463de4c5d | 743 | { |
| group-onsemi | 0:098463de4c5d | 744 | /* Set ADC_REG_InitStruct fields to default values */ |
| group-onsemi | 0:098463de4c5d | 745 | /* Set fields of ADC group regular */ |
| group-onsemi | 0:098463de4c5d | 746 | /* Note: On this STM32 serie, ADC trigger edge is set when starting */ |
| group-onsemi | 0:098463de4c5d | 747 | /* ADC conversion. */ |
| group-onsemi | 0:098463de4c5d | 748 | /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
| group-onsemi | 0:098463de4c5d | 749 | ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; |
| group-onsemi | 0:098463de4c5d | 750 | ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; |
| group-onsemi | 0:098463de4c5d | 751 | ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; |
| group-onsemi | 0:098463de4c5d | 752 | ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; |
| group-onsemi | 0:098463de4c5d | 753 | ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; |
| group-onsemi | 0:098463de4c5d | 754 | } |
| group-onsemi | 0:098463de4c5d | 755 | |
| group-onsemi | 0:098463de4c5d | 756 | /** |
| group-onsemi | 0:098463de4c5d | 757 | * @brief Initialize some features of ADC group injected. |
| group-onsemi | 0:098463de4c5d | 758 | * @note These parameters have an impact on ADC scope: ADC group injected. |
| group-onsemi | 0:098463de4c5d | 759 | * Refer to corresponding unitary functions into |
| group-onsemi | 0:098463de4c5d | 760 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
| group-onsemi | 0:098463de4c5d | 761 | * (functions with prefix "INJ"). |
| group-onsemi | 0:098463de4c5d | 762 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
| group-onsemi | 0:098463de4c5d | 763 | * is conditioned to ADC state: |
| group-onsemi | 0:098463de4c5d | 764 | * ADC instance must be disabled. |
| group-onsemi | 0:098463de4c5d | 765 | * This condition is applied to all ADC features, for efficiency |
| group-onsemi | 0:098463de4c5d | 766 | * and compatibility over all STM32 families. However, the different |
| group-onsemi | 0:098463de4c5d | 767 | * features can be set under different ADC state conditions |
| group-onsemi | 0:098463de4c5d | 768 | * (setting possible with ADC enabled without conversion on going, |
| group-onsemi | 0:098463de4c5d | 769 | * ADC enabled with conversion on going, ...) |
| group-onsemi | 0:098463de4c5d | 770 | * Each feature can be updated afterwards with a unitary function |
| group-onsemi | 0:098463de4c5d | 771 | * and potentially with ADC in a different state than disabled, |
| group-onsemi | 0:098463de4c5d | 772 | * refer to description of each function for setting |
| group-onsemi | 0:098463de4c5d | 773 | * conditioned to ADC state. |
| group-onsemi | 0:098463de4c5d | 774 | * @note After using this function, other features must be configured |
| group-onsemi | 0:098463de4c5d | 775 | * using LL unitary functions. |
| group-onsemi | 0:098463de4c5d | 776 | * The minimum configuration remaining to be done is: |
| group-onsemi | 0:098463de4c5d | 777 | * - Set ADC group injected sequencer: |
| group-onsemi | 0:098463de4c5d | 778 | * map channel on the selected sequencer rank. |
| group-onsemi | 0:098463de4c5d | 779 | * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). |
| group-onsemi | 0:098463de4c5d | 780 | * - Set ADC channel sampling time |
| group-onsemi | 0:098463de4c5d | 781 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
| group-onsemi | 0:098463de4c5d | 782 | * @param ADCx ADC instance |
| group-onsemi | 0:098463de4c5d | 783 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
| group-onsemi | 0:098463de4c5d | 784 | * @retval An ErrorStatus enumeration value: |
| group-onsemi | 0:098463de4c5d | 785 | * - SUCCESS: ADC registers are initialized |
| group-onsemi | 0:098463de4c5d | 786 | * - ERROR: ADC registers are not initialized |
| group-onsemi | 0:098463de4c5d | 787 | */ |
| group-onsemi | 0:098463de4c5d | 788 | ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
| group-onsemi | 0:098463de4c5d | 789 | { |
| group-onsemi | 0:098463de4c5d | 790 | ErrorStatus status = SUCCESS; |
| group-onsemi | 0:098463de4c5d | 791 | |
| group-onsemi | 0:098463de4c5d | 792 | /* Check the parameters */ |
| group-onsemi | 0:098463de4c5d | 793 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
| group-onsemi | 0:098463de4c5d | 794 | assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); |
| group-onsemi | 0:098463de4c5d | 795 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); |
| group-onsemi | 0:098463de4c5d | 796 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) |
| group-onsemi | 0:098463de4c5d | 797 | { |
| group-onsemi | 0:098463de4c5d | 798 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); |
| group-onsemi | 0:098463de4c5d | 799 | } |
| group-onsemi | 0:098463de4c5d | 800 | assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); |
| group-onsemi | 0:098463de4c5d | 801 | |
| group-onsemi | 0:098463de4c5d | 802 | /* Note: Hardware constraint (refer to description of this function): */ |
| group-onsemi | 0:098463de4c5d | 803 | /* ADC instance must be disabled. */ |
| group-onsemi | 0:098463de4c5d | 804 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
| group-onsemi | 0:098463de4c5d | 805 | { |
| group-onsemi | 0:098463de4c5d | 806 | /* Configuration of ADC hierarchical scope: */ |
| group-onsemi | 0:098463de4c5d | 807 | /* - ADC group injected */ |
| group-onsemi | 0:098463de4c5d | 808 | /* - Set ADC group injected trigger source */ |
| group-onsemi | 0:098463de4c5d | 809 | /* - Set ADC group injected sequencer length */ |
| group-onsemi | 0:098463de4c5d | 810 | /* - Set ADC group injected sequencer discontinuous mode */ |
| group-onsemi | 0:098463de4c5d | 811 | /* - Set ADC group injected conversion trigger: independent or */ |
| group-onsemi | 0:098463de4c5d | 812 | /* from ADC group regular */ |
| group-onsemi | 0:098463de4c5d | 813 | /* Note: On this STM32 serie, ADC trigger edge is set when starting */ |
| group-onsemi | 0:098463de4c5d | 814 | /* ADC conversion. */ |
| group-onsemi | 0:098463de4c5d | 815 | /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ |
| group-onsemi | 0:098463de4c5d | 816 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
| group-onsemi | 0:098463de4c5d | 817 | { |
| group-onsemi | 0:098463de4c5d | 818 | MODIFY_REG(ADCx->CR1, |
| group-onsemi | 0:098463de4c5d | 819 | ADC_CR1_JDISCEN |
| group-onsemi | 0:098463de4c5d | 820 | | ADC_CR1_JAUTO |
| group-onsemi | 0:098463de4c5d | 821 | , |
| group-onsemi | 0:098463de4c5d | 822 | ADC_INJ_InitStruct->SequencerDiscont |
| group-onsemi | 0:098463de4c5d | 823 | | ADC_INJ_InitStruct->TrigAuto |
| group-onsemi | 0:098463de4c5d | 824 | ); |
| group-onsemi | 0:098463de4c5d | 825 | } |
| group-onsemi | 0:098463de4c5d | 826 | else |
| group-onsemi | 0:098463de4c5d | 827 | { |
| group-onsemi | 0:098463de4c5d | 828 | MODIFY_REG(ADCx->CR1, |
| group-onsemi | 0:098463de4c5d | 829 | ADC_CR1_JDISCEN |
| group-onsemi | 0:098463de4c5d | 830 | | ADC_CR1_JAUTO |
| group-onsemi | 0:098463de4c5d | 831 | , |
| group-onsemi | 0:098463de4c5d | 832 | LL_ADC_REG_SEQ_DISCONT_DISABLE |
| group-onsemi | 0:098463de4c5d | 833 | | ADC_INJ_InitStruct->TrigAuto |
| group-onsemi | 0:098463de4c5d | 834 | ); |
| group-onsemi | 0:098463de4c5d | 835 | } |
| group-onsemi | 0:098463de4c5d | 836 | |
| group-onsemi | 0:098463de4c5d | 837 | MODIFY_REG(ADCx->CR2, |
| group-onsemi | 0:098463de4c5d | 838 | ADC_CR2_JEXTSEL |
| group-onsemi | 0:098463de4c5d | 839 | | ADC_CR2_JEXTEN |
| group-onsemi | 0:098463de4c5d | 840 | , |
| group-onsemi | 0:098463de4c5d | 841 | (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) |
| group-onsemi | 0:098463de4c5d | 842 | ); |
| group-onsemi | 0:098463de4c5d | 843 | |
| group-onsemi | 0:098463de4c5d | 844 | /* Note: Hardware constraint (refer to description of this function): */ |
| group-onsemi | 0:098463de4c5d | 845 | /* Note: If ADC instance feature scan mode is disabled */ |
| group-onsemi | 0:098463de4c5d | 846 | /* (refer to ADC instance initialization structure */ |
| group-onsemi | 0:098463de4c5d | 847 | /* parameter @ref SequencersScanMode */ |
| group-onsemi | 0:098463de4c5d | 848 | /* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
| group-onsemi | 0:098463de4c5d | 849 | /* this parameter is discarded. */ |
| group-onsemi | 0:098463de4c5d | 850 | LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength); |
| group-onsemi | 0:098463de4c5d | 851 | } |
| group-onsemi | 0:098463de4c5d | 852 | else |
| group-onsemi | 0:098463de4c5d | 853 | { |
| group-onsemi | 0:098463de4c5d | 854 | /* Initialization error: ADC instance is not disabled. */ |
| group-onsemi | 0:098463de4c5d | 855 | status = ERROR; |
| group-onsemi | 0:098463de4c5d | 856 | } |
| group-onsemi | 0:098463de4c5d | 857 | return status; |
| group-onsemi | 0:098463de4c5d | 858 | } |
| group-onsemi | 0:098463de4c5d | 859 | |
| group-onsemi | 0:098463de4c5d | 860 | /** |
| group-onsemi | 0:098463de4c5d | 861 | * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. |
| group-onsemi | 0:098463de4c5d | 862 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
| group-onsemi | 0:098463de4c5d | 863 | * whose fields will be set to default values. |
| group-onsemi | 0:098463de4c5d | 864 | * @retval None |
| group-onsemi | 0:098463de4c5d | 865 | */ |
| group-onsemi | 0:098463de4c5d | 866 | void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
| group-onsemi | 0:098463de4c5d | 867 | { |
| group-onsemi | 0:098463de4c5d | 868 | /* Set ADC_INJ_InitStruct fields to default values */ |
| group-onsemi | 0:098463de4c5d | 869 | /* Set fields of ADC group injected */ |
| group-onsemi | 0:098463de4c5d | 870 | ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; |
| group-onsemi | 0:098463de4c5d | 871 | ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; |
| group-onsemi | 0:098463de4c5d | 872 | ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; |
| group-onsemi | 0:098463de4c5d | 873 | ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; |
| group-onsemi | 0:098463de4c5d | 874 | } |
| group-onsemi | 0:098463de4c5d | 875 | |
| group-onsemi | 0:098463de4c5d | 876 | /** |
| group-onsemi | 0:098463de4c5d | 877 | * @} |
| group-onsemi | 0:098463de4c5d | 878 | */ |
| group-onsemi | 0:098463de4c5d | 879 | |
| group-onsemi | 0:098463de4c5d | 880 | /** |
| group-onsemi | 0:098463de4c5d | 881 | * @} |
| group-onsemi | 0:098463de4c5d | 882 | */ |
| group-onsemi | 0:098463de4c5d | 883 | |
| group-onsemi | 0:098463de4c5d | 884 | /** |
| group-onsemi | 0:098463de4c5d | 885 | * @} |
| group-onsemi | 0:098463de4c5d | 886 | */ |
| group-onsemi | 0:098463de4c5d | 887 | |
| group-onsemi | 0:098463de4c5d | 888 | #endif /* ADC1 */ |
| group-onsemi | 0:098463de4c5d | 889 | |
| group-onsemi | 0:098463de4c5d | 890 | /** |
| group-onsemi | 0:098463de4c5d | 891 | * @} |
| group-onsemi | 0:098463de4c5d | 892 | */ |
| group-onsemi | 0:098463de4c5d | 893 | |
| group-onsemi | 0:098463de4c5d | 894 | #endif /* USE_FULL_LL_DRIVER */ |
| group-onsemi | 0:098463de4c5d | 895 | |
| group-onsemi | 0:098463de4c5d | 896 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |