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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_STM/TARGET_STM32L0/serial_api.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 *******************************************************************************
group-onsemi 0:098463de4c5d 3 * Copyright (c) 2015, STMicroelectronics
group-onsemi 0:098463de4c5d 4 * All rights reserved.
group-onsemi 0:098463de4c5d 5 *
group-onsemi 0:098463de4c5d 6 * Redistribution and use in source and binary forms, with or without
group-onsemi 0:098463de4c5d 7 * modification, are permitted provided that the following conditions are met:
group-onsemi 0:098463de4c5d 8 *
group-onsemi 0:098463de4c5d 9 * 1. Redistributions of source code must retain the above copyright notice,
group-onsemi 0:098463de4c5d 10 * this list of conditions and the following disclaimer.
group-onsemi 0:098463de4c5d 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
group-onsemi 0:098463de4c5d 12 * this list of conditions and the following disclaimer in the documentation
group-onsemi 0:098463de4c5d 13 * and/or other materials provided with the distribution.
group-onsemi 0:098463de4c5d 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
group-onsemi 0:098463de4c5d 15 * may be used to endorse or promote products derived from this software
group-onsemi 0:098463de4c5d 16 * without specific prior written permission.
group-onsemi 0:098463de4c5d 17 *
group-onsemi 0:098463de4c5d 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
group-onsemi 0:098463de4c5d 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
group-onsemi 0:098463de4c5d 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
group-onsemi 0:098463de4c5d 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
group-onsemi 0:098463de4c5d 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
group-onsemi 0:098463de4c5d 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
group-onsemi 0:098463de4c5d 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
group-onsemi 0:098463de4c5d 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
group-onsemi 0:098463de4c5d 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
group-onsemi 0:098463de4c5d 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
group-onsemi 0:098463de4c5d 28 *******************************************************************************
group-onsemi 0:098463de4c5d 29 */
group-onsemi 0:098463de4c5d 30 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 31 #include "serial_api.h"
group-onsemi 0:098463de4c5d 32
group-onsemi 0:098463de4c5d 33 #if DEVICE_SERIAL
group-onsemi 0:098463de4c5d 34
group-onsemi 0:098463de4c5d 35 #include "cmsis.h"
group-onsemi 0:098463de4c5d 36 #include "pinmap.h"
group-onsemi 0:098463de4c5d 37 #include <string.h>
group-onsemi 0:098463de4c5d 38 #include "PeripheralPins.h"
group-onsemi 0:098463de4c5d 39 #include "mbed_error.h"
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 #define UART_NUM (5)
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 static uint32_t serial_irq_ids[UART_NUM] = {0};
group-onsemi 0:098463de4c5d 44 static UART_HandleTypeDef uart_handlers[UART_NUM];
group-onsemi 0:098463de4c5d 45
group-onsemi 0:098463de4c5d 46 static uart_irq_handler irq_handler;
group-onsemi 0:098463de4c5d 47
group-onsemi 0:098463de4c5d 48 int stdio_uart_inited = 0;
group-onsemi 0:098463de4c5d 49 serial_t stdio_uart;
group-onsemi 0:098463de4c5d 50
group-onsemi 0:098463de4c5d 51 #if DEVICE_SERIAL_ASYNCH
group-onsemi 0:098463de4c5d 52 #define SERIAL_S(obj) (&((obj)->serial))
group-onsemi 0:098463de4c5d 53 #else
group-onsemi 0:098463de4c5d 54 #define SERIAL_S(obj) (obj)
group-onsemi 0:098463de4c5d 55 #endif
group-onsemi 0:098463de4c5d 56
group-onsemi 0:098463de4c5d 57 static void init_uart(serial_t *obj)
group-onsemi 0:098463de4c5d 58 {
group-onsemi 0:098463de4c5d 59 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 60 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 61 huart->Instance = (USART_TypeDef *)(obj_s->uart);
group-onsemi 0:098463de4c5d 62
group-onsemi 0:098463de4c5d 63 huart->Init.BaudRate = obj_s->baudrate;
group-onsemi 0:098463de4c5d 64 huart->Init.WordLength = obj_s->databits;
group-onsemi 0:098463de4c5d 65 huart->Init.StopBits = obj_s->stopbits;
group-onsemi 0:098463de4c5d 66 huart->Init.Parity = obj_s->parity;
group-onsemi 0:098463de4c5d 67 huart->Init.Parity = obj_s->parity;
group-onsemi 0:098463de4c5d 68 #if DEVICE_SERIAL_FC
group-onsemi 0:098463de4c5d 69 huart->Init.HwFlowCtl = obj_s->hw_flow_ctl;
group-onsemi 0:098463de4c5d 70 #else
group-onsemi 0:098463de4c5d 71 huart->Init.HwFlowCtl = UART_HWCONTROL_NONE;
group-onsemi 0:098463de4c5d 72 #endif
group-onsemi 0:098463de4c5d 73 huart->TxXferCount = 0;
group-onsemi 0:098463de4c5d 74 huart->TxXferSize = 0;
group-onsemi 0:098463de4c5d 75 huart->RxXferCount = 0;
group-onsemi 0:098463de4c5d 76 huart->RxXferSize = 0;
group-onsemi 0:098463de4c5d 77
group-onsemi 0:098463de4c5d 78 if (obj_s->pin_rx == NC) {
group-onsemi 0:098463de4c5d 79 huart->Init.Mode = UART_MODE_TX;
group-onsemi 0:098463de4c5d 80 } else if (obj_s->pin_tx == NC) {
group-onsemi 0:098463de4c5d 81 huart->Init.Mode = UART_MODE_RX;
group-onsemi 0:098463de4c5d 82 } else {
group-onsemi 0:098463de4c5d 83 huart->Init.Mode = UART_MODE_TX_RX;
group-onsemi 0:098463de4c5d 84 }
group-onsemi 0:098463de4c5d 85
group-onsemi 0:098463de4c5d 86 if (HAL_UART_Init(huart) != HAL_OK) {
group-onsemi 0:098463de4c5d 87 error("Cannot initialize UART\n");
group-onsemi 0:098463de4c5d 88 }
group-onsemi 0:098463de4c5d 89 }
group-onsemi 0:098463de4c5d 90
group-onsemi 0:098463de4c5d 91 void serial_init(serial_t *obj, PinName tx, PinName rx)
group-onsemi 0:098463de4c5d 92 {
group-onsemi 0:098463de4c5d 93 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 94
group-onsemi 0:098463de4c5d 95 // Determine the UART to use (UART_1, UART_2, ...)
group-onsemi 0:098463de4c5d 96 UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
group-onsemi 0:098463de4c5d 97 UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
group-onsemi 0:098463de4c5d 98
group-onsemi 0:098463de4c5d 99 // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
group-onsemi 0:098463de4c5d 100 obj_s->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
group-onsemi 0:098463de4c5d 101 MBED_ASSERT(obj_s->uart != (UARTName)NC);
group-onsemi 0:098463de4c5d 102
group-onsemi 0:098463de4c5d 103 // Enable UART clock
group-onsemi 0:098463de4c5d 104 #if defined(USART1_BASE)
group-onsemi 0:098463de4c5d 105 if (obj_s->uart == UART_1) {
group-onsemi 0:098463de4c5d 106 __HAL_RCC_USART1_FORCE_RESET();
group-onsemi 0:098463de4c5d 107 __HAL_RCC_USART1_RELEASE_RESET();
group-onsemi 0:098463de4c5d 108 __HAL_RCC_USART1_CLK_ENABLE();
group-onsemi 0:098463de4c5d 109 obj_s->index = 0;
group-onsemi 0:098463de4c5d 110 }
group-onsemi 0:098463de4c5d 111 #endif
group-onsemi 0:098463de4c5d 112
group-onsemi 0:098463de4c5d 113 if (obj_s->uart == UART_2) {
group-onsemi 0:098463de4c5d 114 __HAL_RCC_USART2_FORCE_RESET();
group-onsemi 0:098463de4c5d 115 __HAL_RCC_USART2_RELEASE_RESET();
group-onsemi 0:098463de4c5d 116 __HAL_RCC_USART2_CLK_ENABLE();
group-onsemi 0:098463de4c5d 117 obj_s->index = 1;
group-onsemi 0:098463de4c5d 118 }
group-onsemi 0:098463de4c5d 119
group-onsemi 0:098463de4c5d 120 if (obj_s->uart == LPUART_1) {
group-onsemi 0:098463de4c5d 121 __HAL_RCC_LPUART1_FORCE_RESET();
group-onsemi 0:098463de4c5d 122 __HAL_RCC_LPUART1_RELEASE_RESET();
group-onsemi 0:098463de4c5d 123 __HAL_RCC_LPUART1_CLK_ENABLE();
group-onsemi 0:098463de4c5d 124 obj_s->index = 2;
group-onsemi 0:098463de4c5d 125 }
group-onsemi 0:098463de4c5d 126
group-onsemi 0:098463de4c5d 127 #if defined(USART4_BASE)
group-onsemi 0:098463de4c5d 128 if (obj_s->uart == UART_4) {
group-onsemi 0:098463de4c5d 129 __HAL_RCC_USART4_FORCE_RESET();
group-onsemi 0:098463de4c5d 130 __HAL_RCC_USART4_RELEASE_RESET();
group-onsemi 0:098463de4c5d 131 __HAL_RCC_USART4_CLK_ENABLE();
group-onsemi 0:098463de4c5d 132 obj_s->index = 3;
group-onsemi 0:098463de4c5d 133 }
group-onsemi 0:098463de4c5d 134 #endif
group-onsemi 0:098463de4c5d 135
group-onsemi 0:098463de4c5d 136 #if defined(USART5_BASE)
group-onsemi 0:098463de4c5d 137 if (obj_s->uart == UART_5) {
group-onsemi 0:098463de4c5d 138 __HAL_RCC_USART5_FORCE_RESET();
group-onsemi 0:098463de4c5d 139 __HAL_RCC_USART5_RELEASE_RESET();
group-onsemi 0:098463de4c5d 140 __HAL_RCC_USART5_CLK_ENABLE();
group-onsemi 0:098463de4c5d 141 obj_s->index = 4;
group-onsemi 0:098463de4c5d 142 }
group-onsemi 0:098463de4c5d 143 #endif
group-onsemi 0:098463de4c5d 144
group-onsemi 0:098463de4c5d 145 // Configure the UART pins
group-onsemi 0:098463de4c5d 146 pinmap_pinout(tx, PinMap_UART_TX);
group-onsemi 0:098463de4c5d 147 pinmap_pinout(rx, PinMap_UART_RX);
group-onsemi 0:098463de4c5d 148
group-onsemi 0:098463de4c5d 149 if (tx != NC) {
group-onsemi 0:098463de4c5d 150 pin_mode(tx, PullUp);
group-onsemi 0:098463de4c5d 151 }
group-onsemi 0:098463de4c5d 152 if (rx != NC) {
group-onsemi 0:098463de4c5d 153 pin_mode(rx, PullUp);
group-onsemi 0:098463de4c5d 154 }
group-onsemi 0:098463de4c5d 155
group-onsemi 0:098463de4c5d 156 // Configure UART
group-onsemi 0:098463de4c5d 157 obj_s->baudrate = 9600;
group-onsemi 0:098463de4c5d 158 obj_s->databits = UART_WORDLENGTH_8B;
group-onsemi 0:098463de4c5d 159 obj_s->stopbits = UART_STOPBITS_1;
group-onsemi 0:098463de4c5d 160 obj_s->parity = UART_PARITY_NONE;
group-onsemi 0:098463de4c5d 161
group-onsemi 0:098463de4c5d 162 #if DEVICE_SERIAL_FC
group-onsemi 0:098463de4c5d 163 obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
group-onsemi 0:098463de4c5d 164 #endif
group-onsemi 0:098463de4c5d 165
group-onsemi 0:098463de4c5d 166 obj_s->pin_tx = tx;
group-onsemi 0:098463de4c5d 167 obj_s->pin_rx = rx;
group-onsemi 0:098463de4c5d 168
group-onsemi 0:098463de4c5d 169 init_uart(obj);
group-onsemi 0:098463de4c5d 170
group-onsemi 0:098463de4c5d 171 // For stdio management
group-onsemi 0:098463de4c5d 172 if (obj_s->uart == STDIO_UART) {
group-onsemi 0:098463de4c5d 173 stdio_uart_inited = 1;
group-onsemi 0:098463de4c5d 174 memcpy(&stdio_uart, obj, sizeof(serial_t));
group-onsemi 0:098463de4c5d 175 }
group-onsemi 0:098463de4c5d 176 }
group-onsemi 0:098463de4c5d 177
group-onsemi 0:098463de4c5d 178 void serial_free(serial_t *obj)
group-onsemi 0:098463de4c5d 179 {
group-onsemi 0:098463de4c5d 180 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 181
group-onsemi 0:098463de4c5d 182 // Reset UART and disable clock
group-onsemi 0:098463de4c5d 183 #if defined(USART1_BASE)
group-onsemi 0:098463de4c5d 184 if (obj_s->uart == UART_1) {
group-onsemi 0:098463de4c5d 185 __HAL_RCC_USART1_FORCE_RESET();
group-onsemi 0:098463de4c5d 186 __HAL_RCC_USART1_RELEASE_RESET();
group-onsemi 0:098463de4c5d 187 __HAL_RCC_USART1_CLK_DISABLE();
group-onsemi 0:098463de4c5d 188 }
group-onsemi 0:098463de4c5d 189 #endif
group-onsemi 0:098463de4c5d 190
group-onsemi 0:098463de4c5d 191 if (obj_s->uart == UART_2) {
group-onsemi 0:098463de4c5d 192 __HAL_RCC_USART2_FORCE_RESET();
group-onsemi 0:098463de4c5d 193 __HAL_RCC_USART2_RELEASE_RESET();
group-onsemi 0:098463de4c5d 194 __HAL_RCC_USART2_CLK_DISABLE();
group-onsemi 0:098463de4c5d 195 }
group-onsemi 0:098463de4c5d 196
group-onsemi 0:098463de4c5d 197 if (obj_s->uart == LPUART_1) {
group-onsemi 0:098463de4c5d 198 __HAL_RCC_LPUART1_FORCE_RESET();
group-onsemi 0:098463de4c5d 199 __HAL_RCC_LPUART1_RELEASE_RESET();
group-onsemi 0:098463de4c5d 200 __HAL_RCC_LPUART1_CLK_DISABLE();
group-onsemi 0:098463de4c5d 201 }
group-onsemi 0:098463de4c5d 202
group-onsemi 0:098463de4c5d 203 #if defined(USART4_BASE)
group-onsemi 0:098463de4c5d 204 if (obj_s->uart == UART_4) {
group-onsemi 0:098463de4c5d 205 __HAL_RCC_USART4_FORCE_RESET();
group-onsemi 0:098463de4c5d 206 __HAL_RCC_USART4_RELEASE_RESET();
group-onsemi 0:098463de4c5d 207 __HAL_RCC_USART4_CLK_DISABLE();
group-onsemi 0:098463de4c5d 208 }
group-onsemi 0:098463de4c5d 209 #endif
group-onsemi 0:098463de4c5d 210
group-onsemi 0:098463de4c5d 211 #if defined(USART5_BASE)
group-onsemi 0:098463de4c5d 212 if (obj_s->uart == UART_5) {
group-onsemi 0:098463de4c5d 213 __HAL_RCC_USART5_FORCE_RESET();
group-onsemi 0:098463de4c5d 214 __HAL_RCC_USART5_RELEASE_RESET();
group-onsemi 0:098463de4c5d 215 __HAL_RCC_USART5_CLK_DISABLE();
group-onsemi 0:098463de4c5d 216 }
group-onsemi 0:098463de4c5d 217 #endif
group-onsemi 0:098463de4c5d 218
group-onsemi 0:098463de4c5d 219 // Configure GPIOs
group-onsemi 0:098463de4c5d 220 pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
group-onsemi 0:098463de4c5d 221 pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
group-onsemi 0:098463de4c5d 222
group-onsemi 0:098463de4c5d 223 serial_irq_ids[obj_s->index] = 0;
group-onsemi 0:098463de4c5d 224 }
group-onsemi 0:098463de4c5d 225
group-onsemi 0:098463de4c5d 226 void serial_baud(serial_t *obj, int baudrate)
group-onsemi 0:098463de4c5d 227 {
group-onsemi 0:098463de4c5d 228 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 229
group-onsemi 0:098463de4c5d 230 obj_s->baudrate = baudrate;
group-onsemi 0:098463de4c5d 231 init_uart(obj);
group-onsemi 0:098463de4c5d 232 }
group-onsemi 0:098463de4c5d 233
group-onsemi 0:098463de4c5d 234 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
group-onsemi 0:098463de4c5d 235 {
group-onsemi 0:098463de4c5d 236 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 237
group-onsemi 0:098463de4c5d 238 if (data_bits == 9) {
group-onsemi 0:098463de4c5d 239 obj_s->databits = UART_WORDLENGTH_9B;
group-onsemi 0:098463de4c5d 240 } else {
group-onsemi 0:098463de4c5d 241 obj_s->databits = UART_WORDLENGTH_8B;
group-onsemi 0:098463de4c5d 242 }
group-onsemi 0:098463de4c5d 243
group-onsemi 0:098463de4c5d 244 switch (parity) {
group-onsemi 0:098463de4c5d 245 case ParityOdd:
group-onsemi 0:098463de4c5d 246 obj_s->parity = UART_PARITY_ODD;
group-onsemi 0:098463de4c5d 247 break;
group-onsemi 0:098463de4c5d 248 case ParityEven:
group-onsemi 0:098463de4c5d 249 obj_s->parity = UART_PARITY_EVEN;
group-onsemi 0:098463de4c5d 250 break;
group-onsemi 0:098463de4c5d 251 default: // ParityNone
group-onsemi 0:098463de4c5d 252 case ParityForced0: // unsupported!
group-onsemi 0:098463de4c5d 253 case ParityForced1: // unsupported!
group-onsemi 0:098463de4c5d 254 obj_s->parity = UART_PARITY_NONE;
group-onsemi 0:098463de4c5d 255 break;
group-onsemi 0:098463de4c5d 256 }
group-onsemi 0:098463de4c5d 257
group-onsemi 0:098463de4c5d 258 if (stop_bits == 2) {
group-onsemi 0:098463de4c5d 259 obj_s->stopbits = UART_STOPBITS_2;
group-onsemi 0:098463de4c5d 260 } else {
group-onsemi 0:098463de4c5d 261 obj_s->stopbits = UART_STOPBITS_1;
group-onsemi 0:098463de4c5d 262 }
group-onsemi 0:098463de4c5d 263
group-onsemi 0:098463de4c5d 264 init_uart(obj);
group-onsemi 0:098463de4c5d 265 }
group-onsemi 0:098463de4c5d 266
group-onsemi 0:098463de4c5d 267 /******************************************************************************
group-onsemi 0:098463de4c5d 268 * INTERRUPTS HANDLING
group-onsemi 0:098463de4c5d 269 ******************************************************************************/
group-onsemi 0:098463de4c5d 270
group-onsemi 0:098463de4c5d 271 static void uart_irq(int id)
group-onsemi 0:098463de4c5d 272 {
group-onsemi 0:098463de4c5d 273 UART_HandleTypeDef * huart = &uart_handlers[id];
group-onsemi 0:098463de4c5d 274
group-onsemi 0:098463de4c5d 275 if (serial_irq_ids[id] != 0) {
group-onsemi 0:098463de4c5d 276 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
group-onsemi 0:098463de4c5d 277 if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
group-onsemi 0:098463de4c5d 278 irq_handler(serial_irq_ids[id], TxIrq);
group-onsemi 0:098463de4c5d 279 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
group-onsemi 0:098463de4c5d 280 }
group-onsemi 0:098463de4c5d 281 }
group-onsemi 0:098463de4c5d 282 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) {
group-onsemi 0:098463de4c5d 283 if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET) {
group-onsemi 0:098463de4c5d 284 irq_handler(serial_irq_ids[id], RxIrq);
group-onsemi 0:098463de4c5d 285 volatile uint32_t tmpval = huart->Instance->RDR; // Clear RXNE flag
group-onsemi 0:098463de4c5d 286 }
group-onsemi 0:098463de4c5d 287 }
group-onsemi 0:098463de4c5d 288 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
group-onsemi 0:098463de4c5d 289 if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ORE) != RESET) {
group-onsemi 0:098463de4c5d 290 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
group-onsemi 0:098463de4c5d 291 }
group-onsemi 0:098463de4c5d 292 }
group-onsemi 0:098463de4c5d 293 }
group-onsemi 0:098463de4c5d 294 }
group-onsemi 0:098463de4c5d 295
group-onsemi 0:098463de4c5d 296 #if defined(USART1_BASE)
group-onsemi 0:098463de4c5d 297 static void uart1_irq(void)
group-onsemi 0:098463de4c5d 298 {
group-onsemi 0:098463de4c5d 299 uart_irq(0);
group-onsemi 0:098463de4c5d 300 }
group-onsemi 0:098463de4c5d 301 #endif
group-onsemi 0:098463de4c5d 302
group-onsemi 0:098463de4c5d 303 static void uart2_irq(void)
group-onsemi 0:098463de4c5d 304 {
group-onsemi 0:098463de4c5d 305 uart_irq(1);
group-onsemi 0:098463de4c5d 306 }
group-onsemi 0:098463de4c5d 307
group-onsemi 0:098463de4c5d 308 static void lpuart1_irq(void)
group-onsemi 0:098463de4c5d 309 {
group-onsemi 0:098463de4c5d 310 uart_irq(2);
group-onsemi 0:098463de4c5d 311 }
group-onsemi 0:098463de4c5d 312
group-onsemi 0:098463de4c5d 313 #if defined(USART4_BASE)
group-onsemi 0:098463de4c5d 314 static void uart4_irq(void)
group-onsemi 0:098463de4c5d 315 {
group-onsemi 0:098463de4c5d 316 uart_irq(3);
group-onsemi 0:098463de4c5d 317 }
group-onsemi 0:098463de4c5d 318 #endif
group-onsemi 0:098463de4c5d 319
group-onsemi 0:098463de4c5d 320 #if defined(USART5_BASE)
group-onsemi 0:098463de4c5d 321 static void uart5_irq(void)
group-onsemi 0:098463de4c5d 322 {
group-onsemi 0:098463de4c5d 323 uart_irq(4);
group-onsemi 0:098463de4c5d 324 }
group-onsemi 0:098463de4c5d 325 #endif
group-onsemi 0:098463de4c5d 326
group-onsemi 0:098463de4c5d 327 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
group-onsemi 0:098463de4c5d 328 {
group-onsemi 0:098463de4c5d 329 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 330
group-onsemi 0:098463de4c5d 331 irq_handler = handler;
group-onsemi 0:098463de4c5d 332 serial_irq_ids[obj_s->index] = id;
group-onsemi 0:098463de4c5d 333 }
group-onsemi 0:098463de4c5d 334
group-onsemi 0:098463de4c5d 335 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
group-onsemi 0:098463de4c5d 336 {
group-onsemi 0:098463de4c5d 337 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 338 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 339 IRQn_Type irq_n = (IRQn_Type)0;
group-onsemi 0:098463de4c5d 340 uint32_t vector = 0;
group-onsemi 0:098463de4c5d 341
group-onsemi 0:098463de4c5d 342 #if defined(USART1_BASE)
group-onsemi 0:098463de4c5d 343 if (obj_s->uart == UART_1) {
group-onsemi 0:098463de4c5d 344 irq_n = USART1_IRQn;
group-onsemi 0:098463de4c5d 345 vector = (uint32_t)&uart1_irq;
group-onsemi 0:098463de4c5d 346 }
group-onsemi 0:098463de4c5d 347 #endif
group-onsemi 0:098463de4c5d 348
group-onsemi 0:098463de4c5d 349 if (obj_s->uart == UART_2) {
group-onsemi 0:098463de4c5d 350 irq_n = USART2_IRQn;
group-onsemi 0:098463de4c5d 351 vector = (uint32_t)&uart2_irq;
group-onsemi 0:098463de4c5d 352 }
group-onsemi 0:098463de4c5d 353
group-onsemi 0:098463de4c5d 354 if (obj_s->uart == LPUART_1) {
group-onsemi 0:098463de4c5d 355 irq_n = RNG_LPUART1_IRQn;
group-onsemi 0:098463de4c5d 356 vector = (uint32_t)&lpuart1_irq;
group-onsemi 0:098463de4c5d 357 }
group-onsemi 0:098463de4c5d 358
group-onsemi 0:098463de4c5d 359 #if defined(USART4_BASE)
group-onsemi 0:098463de4c5d 360 if (obj_s->uart == UART_4) {
group-onsemi 0:098463de4c5d 361 irq_n = USART4_5_IRQn;
group-onsemi 0:098463de4c5d 362 vector = (uint32_t)&uart4_irq;
group-onsemi 0:098463de4c5d 363 }
group-onsemi 0:098463de4c5d 364 #endif
group-onsemi 0:098463de4c5d 365
group-onsemi 0:098463de4c5d 366 #if defined(USART5_BASE)
group-onsemi 0:098463de4c5d 367 if (obj_s->uart == UART_5) {
group-onsemi 0:098463de4c5d 368 irq_n = USART4_5_IRQn;
group-onsemi 0:098463de4c5d 369 vector = (uint32_t)&uart5_irq;
group-onsemi 0:098463de4c5d 370 }
group-onsemi 0:098463de4c5d 371 #endif
group-onsemi 0:098463de4c5d 372
group-onsemi 0:098463de4c5d 373 if (enable) {
group-onsemi 0:098463de4c5d 374 if (irq == RxIrq) {
group-onsemi 0:098463de4c5d 375 __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
group-onsemi 0:098463de4c5d 376 } else { // TxIrq
group-onsemi 0:098463de4c5d 377 __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
group-onsemi 0:098463de4c5d 378 }
group-onsemi 0:098463de4c5d 379 NVIC_SetVector(irq_n, vector);
group-onsemi 0:098463de4c5d 380 NVIC_EnableIRQ(irq_n);
group-onsemi 0:098463de4c5d 381
group-onsemi 0:098463de4c5d 382 } else { // disable
group-onsemi 0:098463de4c5d 383 int all_disabled = 0;
group-onsemi 0:098463de4c5d 384 if (irq == RxIrq) {
group-onsemi 0:098463de4c5d 385 __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
group-onsemi 0:098463de4c5d 386 // Check if TxIrq is disabled too
group-onsemi 0:098463de4c5d 387 if ((huart->Instance->CR1 & USART_CR1_TXEIE) == 0) {
group-onsemi 0:098463de4c5d 388 all_disabled = 1;
group-onsemi 0:098463de4c5d 389 }
group-onsemi 0:098463de4c5d 390 } else { // TxIrq
group-onsemi 0:098463de4c5d 391 __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
group-onsemi 0:098463de4c5d 392 // Check if RxIrq is disabled too
group-onsemi 0:098463de4c5d 393 if ((huart->Instance->CR1 & USART_CR1_RXNEIE) == 0) {
group-onsemi 0:098463de4c5d 394 all_disabled = 1;
group-onsemi 0:098463de4c5d 395 }
group-onsemi 0:098463de4c5d 396 }
group-onsemi 0:098463de4c5d 397
group-onsemi 0:098463de4c5d 398 if (all_disabled) {
group-onsemi 0:098463de4c5d 399 NVIC_DisableIRQ(irq_n);
group-onsemi 0:098463de4c5d 400 }
group-onsemi 0:098463de4c5d 401 }
group-onsemi 0:098463de4c5d 402 }
group-onsemi 0:098463de4c5d 403
group-onsemi 0:098463de4c5d 404 /******************************************************************************
group-onsemi 0:098463de4c5d 405 * READ/WRITE
group-onsemi 0:098463de4c5d 406 ******************************************************************************/
group-onsemi 0:098463de4c5d 407
group-onsemi 0:098463de4c5d 408 int serial_getc(serial_t *obj)
group-onsemi 0:098463de4c5d 409 {
group-onsemi 0:098463de4c5d 410 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 411 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 412
group-onsemi 0:098463de4c5d 413 while (!serial_readable(obj));
group-onsemi 0:098463de4c5d 414 return (int)(huart->Instance->RDR & (uint16_t)0xFF);
group-onsemi 0:098463de4c5d 415 }
group-onsemi 0:098463de4c5d 416
group-onsemi 0:098463de4c5d 417 void serial_putc(serial_t *obj, int c)
group-onsemi 0:098463de4c5d 418 {
group-onsemi 0:098463de4c5d 419 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 420 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 421
group-onsemi 0:098463de4c5d 422 while (!serial_writable(obj));
group-onsemi 0:098463de4c5d 423 huart->Instance->TDR = (uint32_t)(c & (uint16_t)0xFF);
group-onsemi 0:098463de4c5d 424 }
group-onsemi 0:098463de4c5d 425
group-onsemi 0:098463de4c5d 426 int serial_readable(serial_t *obj)
group-onsemi 0:098463de4c5d 427 {
group-onsemi 0:098463de4c5d 428 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 429 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 430
group-onsemi 0:098463de4c5d 431 // Check if data is received
group-onsemi 0:098463de4c5d 432 return (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) ? 1 : 0;
group-onsemi 0:098463de4c5d 433 }
group-onsemi 0:098463de4c5d 434
group-onsemi 0:098463de4c5d 435 int serial_writable(serial_t *obj)
group-onsemi 0:098463de4c5d 436 {
group-onsemi 0:098463de4c5d 437 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 438 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 439
group-onsemi 0:098463de4c5d 440 // Check if data is transmitted
group-onsemi 0:098463de4c5d 441 return (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) ? 1 : 0;
group-onsemi 0:098463de4c5d 442 }
group-onsemi 0:098463de4c5d 443
group-onsemi 0:098463de4c5d 444 void serial_clear(serial_t *obj)
group-onsemi 0:098463de4c5d 445 {
group-onsemi 0:098463de4c5d 446 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 447 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 448
group-onsemi 0:098463de4c5d 449 huart->TxXferCount = 0;
group-onsemi 0:098463de4c5d 450 huart->RxXferCount = 0;
group-onsemi 0:098463de4c5d 451 }
group-onsemi 0:098463de4c5d 452
group-onsemi 0:098463de4c5d 453 void serial_pinout_tx(PinName tx)
group-onsemi 0:098463de4c5d 454 {
group-onsemi 0:098463de4c5d 455 pinmap_pinout(tx, PinMap_UART_TX);
group-onsemi 0:098463de4c5d 456 }
group-onsemi 0:098463de4c5d 457
group-onsemi 0:098463de4c5d 458 void serial_break_set(serial_t *obj)
group-onsemi 0:098463de4c5d 459 {
group-onsemi 0:098463de4c5d 460 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 461 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 462
group-onsemi 0:098463de4c5d 463 __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
group-onsemi 0:098463de4c5d 464 }
group-onsemi 0:098463de4c5d 465
group-onsemi 0:098463de4c5d 466 void serial_break_clear(serial_t *obj)
group-onsemi 0:098463de4c5d 467 {
group-onsemi 0:098463de4c5d 468 (void)obj;
group-onsemi 0:098463de4c5d 469 }
group-onsemi 0:098463de4c5d 470
group-onsemi 0:098463de4c5d 471 #if DEVICE_SERIAL_ASYNCH
group-onsemi 0:098463de4c5d 472
group-onsemi 0:098463de4c5d 473 /******************************************************************************
group-onsemi 0:098463de4c5d 474 * LOCAL HELPER FUNCTIONS
group-onsemi 0:098463de4c5d 475 ******************************************************************************/
group-onsemi 0:098463de4c5d 476
group-onsemi 0:098463de4c5d 477 /**
group-onsemi 0:098463de4c5d 478 * Configure the TX buffer for an asynchronous write serial transaction
group-onsemi 0:098463de4c5d 479 *
group-onsemi 0:098463de4c5d 480 * @param obj The serial object.
group-onsemi 0:098463de4c5d 481 * @param tx The buffer for sending.
group-onsemi 0:098463de4c5d 482 * @param tx_length The number of words to transmit.
group-onsemi 0:098463de4c5d 483 */
group-onsemi 0:098463de4c5d 484 static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t width)
group-onsemi 0:098463de4c5d 485 {
group-onsemi 0:098463de4c5d 486 (void)width;
group-onsemi 0:098463de4c5d 487
group-onsemi 0:098463de4c5d 488 // Exit if a transmit is already on-going
group-onsemi 0:098463de4c5d 489 if (serial_tx_active(obj)) {
group-onsemi 0:098463de4c5d 490 return;
group-onsemi 0:098463de4c5d 491 }
group-onsemi 0:098463de4c5d 492
group-onsemi 0:098463de4c5d 493 obj->tx_buff.buffer = tx;
group-onsemi 0:098463de4c5d 494 obj->tx_buff.length = tx_length;
group-onsemi 0:098463de4c5d 495 obj->tx_buff.pos = 0;
group-onsemi 0:098463de4c5d 496 }
group-onsemi 0:098463de4c5d 497
group-onsemi 0:098463de4c5d 498 /**
group-onsemi 0:098463de4c5d 499 * Configure the RX buffer for an asynchronous write serial transaction
group-onsemi 0:098463de4c5d 500 *
group-onsemi 0:098463de4c5d 501 * @param obj The serial object.
group-onsemi 0:098463de4c5d 502 * @param tx The buffer for sending.
group-onsemi 0:098463de4c5d 503 * @param tx_length The number of words to transmit.
group-onsemi 0:098463de4c5d 504 */
group-onsemi 0:098463de4c5d 505 static void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t width)
group-onsemi 0:098463de4c5d 506 {
group-onsemi 0:098463de4c5d 507 (void)width;
group-onsemi 0:098463de4c5d 508
group-onsemi 0:098463de4c5d 509 // Exit if a reception is already on-going
group-onsemi 0:098463de4c5d 510 if (serial_rx_active(obj)) {
group-onsemi 0:098463de4c5d 511 return;
group-onsemi 0:098463de4c5d 512 }
group-onsemi 0:098463de4c5d 513
group-onsemi 0:098463de4c5d 514 obj->rx_buff.buffer = rx;
group-onsemi 0:098463de4c5d 515 obj->rx_buff.length = rx_length;
group-onsemi 0:098463de4c5d 516 obj->rx_buff.pos = 0;
group-onsemi 0:098463de4c5d 517 }
group-onsemi 0:098463de4c5d 518
group-onsemi 0:098463de4c5d 519 /**
group-onsemi 0:098463de4c5d 520 * Configure events
group-onsemi 0:098463de4c5d 521 *
group-onsemi 0:098463de4c5d 522 * @param obj The serial object
group-onsemi 0:098463de4c5d 523 * @param event The logical OR of the events to configure
group-onsemi 0:098463de4c5d 524 * @param enable Set to non-zero to enable events, or zero to disable them
group-onsemi 0:098463de4c5d 525 */
group-onsemi 0:098463de4c5d 526 static void serial_enable_event(serial_t *obj, int event, uint8_t enable)
group-onsemi 0:098463de4c5d 527 {
group-onsemi 0:098463de4c5d 528 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 529
group-onsemi 0:098463de4c5d 530 // Shouldn't have to enable interrupt here, just need to keep track of the requested events.
group-onsemi 0:098463de4c5d 531 if (enable) {
group-onsemi 0:098463de4c5d 532 obj_s->events |= event;
group-onsemi 0:098463de4c5d 533 } else {
group-onsemi 0:098463de4c5d 534 obj_s->events &= ~event;
group-onsemi 0:098463de4c5d 535 }
group-onsemi 0:098463de4c5d 536 }
group-onsemi 0:098463de4c5d 537
group-onsemi 0:098463de4c5d 538
group-onsemi 0:098463de4c5d 539 /**
group-onsemi 0:098463de4c5d 540 * Get index of serial object TX IRQ, relating it to the physical peripheral.
group-onsemi 0:098463de4c5d 541 *
group-onsemi 0:098463de4c5d 542 * @param obj pointer to serial object
group-onsemi 0:098463de4c5d 543 * @return internal NVIC TX IRQ index of U(S)ART peripheral
group-onsemi 0:098463de4c5d 544 */
group-onsemi 0:098463de4c5d 545 static IRQn_Type serial_get_irq_n(serial_t *obj)
group-onsemi 0:098463de4c5d 546 {
group-onsemi 0:098463de4c5d 547 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 548 IRQn_Type irq_n;
group-onsemi 0:098463de4c5d 549
group-onsemi 0:098463de4c5d 550 switch (obj_s->index) {
group-onsemi 0:098463de4c5d 551 #if defined(USART1_BASE)
group-onsemi 0:098463de4c5d 552 case 0:
group-onsemi 0:098463de4c5d 553 irq_n = USART1_IRQn;
group-onsemi 0:098463de4c5d 554 break;
group-onsemi 0:098463de4c5d 555 #endif
group-onsemi 0:098463de4c5d 556 case 1:
group-onsemi 0:098463de4c5d 557 irq_n = USART2_IRQn;
group-onsemi 0:098463de4c5d 558 break;
group-onsemi 0:098463de4c5d 559
group-onsemi 0:098463de4c5d 560 case 2:
group-onsemi 0:098463de4c5d 561 irq_n = RNG_LPUART1_IRQn;
group-onsemi 0:098463de4c5d 562 break;
group-onsemi 0:098463de4c5d 563 #if defined(USART4_BASE)
group-onsemi 0:098463de4c5d 564 case 3:
group-onsemi 0:098463de4c5d 565 irq_n = USART4_5_IRQn;
group-onsemi 0:098463de4c5d 566 break;
group-onsemi 0:098463de4c5d 567 #endif
group-onsemi 0:098463de4c5d 568 #if defined(USART5_BASE)
group-onsemi 0:098463de4c5d 569 case 4:
group-onsemi 0:098463de4c5d 570 irq_n = USART4_5_IRQn;
group-onsemi 0:098463de4c5d 571 break;
group-onsemi 0:098463de4c5d 572 #endif
group-onsemi 0:098463de4c5d 573 default:
group-onsemi 0:098463de4c5d 574 irq_n = (IRQn_Type)0;
group-onsemi 0:098463de4c5d 575 }
group-onsemi 0:098463de4c5d 576
group-onsemi 0:098463de4c5d 577 return irq_n;
group-onsemi 0:098463de4c5d 578 }
group-onsemi 0:098463de4c5d 579
group-onsemi 0:098463de4c5d 580
group-onsemi 0:098463de4c5d 581 /******************************************************************************
group-onsemi 0:098463de4c5d 582 * MBED API FUNCTIONS
group-onsemi 0:098463de4c5d 583 ******************************************************************************/
group-onsemi 0:098463de4c5d 584
group-onsemi 0:098463de4c5d 585 /**
group-onsemi 0:098463de4c5d 586 * Begin asynchronous TX transfer. The used buffer is specified in the serial
group-onsemi 0:098463de4c5d 587 * object, tx_buff
group-onsemi 0:098463de4c5d 588 *
group-onsemi 0:098463de4c5d 589 * @param obj The serial object
group-onsemi 0:098463de4c5d 590 * @param tx The buffer for sending
group-onsemi 0:098463de4c5d 591 * @param tx_length The number of words to transmit
group-onsemi 0:098463de4c5d 592 * @param tx_width The bit width of buffer word
group-onsemi 0:098463de4c5d 593 * @param handler The serial handler
group-onsemi 0:098463de4c5d 594 * @param event The logical OR of events to be registered
group-onsemi 0:098463de4c5d 595 * @param hint A suggestion for how to use DMA with this transfer
group-onsemi 0:098463de4c5d 596 * @return Returns number of data transfered, or 0 otherwise
group-onsemi 0:098463de4c5d 597 */
group-onsemi 0:098463de4c5d 598 int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
group-onsemi 0:098463de4c5d 599 {
group-onsemi 0:098463de4c5d 600 // TODO: DMA usage is currently ignored
group-onsemi 0:098463de4c5d 601 (void) hint;
group-onsemi 0:098463de4c5d 602
group-onsemi 0:098463de4c5d 603 // Check buffer is ok
group-onsemi 0:098463de4c5d 604 MBED_ASSERT(tx != (void*)0);
group-onsemi 0:098463de4c5d 605 MBED_ASSERT(tx_width == 8); // support only 8b width
group-onsemi 0:098463de4c5d 606
group-onsemi 0:098463de4c5d 607 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 608 UART_HandleTypeDef * huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 609
group-onsemi 0:098463de4c5d 610 if (tx_length == 0) {
group-onsemi 0:098463de4c5d 611 return 0;
group-onsemi 0:098463de4c5d 612 }
group-onsemi 0:098463de4c5d 613
group-onsemi 0:098463de4c5d 614 // Set up buffer
group-onsemi 0:098463de4c5d 615 serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width);
group-onsemi 0:098463de4c5d 616
group-onsemi 0:098463de4c5d 617 // Set up events
group-onsemi 0:098463de4c5d 618 serial_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events
group-onsemi 0:098463de4c5d 619 serial_enable_event(obj, event, 1); // Set only the wanted events
group-onsemi 0:098463de4c5d 620
group-onsemi 0:098463de4c5d 621 // Enable interrupt
group-onsemi 0:098463de4c5d 622 IRQn_Type irq_n = serial_get_irq_n(obj);
group-onsemi 0:098463de4c5d 623 NVIC_ClearPendingIRQ(irq_n);
group-onsemi 0:098463de4c5d 624 NVIC_DisableIRQ(irq_n);
group-onsemi 0:098463de4c5d 625 NVIC_SetPriority(irq_n, 1);
group-onsemi 0:098463de4c5d 626 NVIC_SetVector(irq_n, (uint32_t)handler);
group-onsemi 0:098463de4c5d 627 NVIC_EnableIRQ(irq_n);
group-onsemi 0:098463de4c5d 628
group-onsemi 0:098463de4c5d 629 // the following function will enable UART_IT_TXE and error interrupts
group-onsemi 0:098463de4c5d 630 if (HAL_UART_Transmit_IT(huart, (uint8_t*)tx, tx_length) != HAL_OK) {
group-onsemi 0:098463de4c5d 631 return 0;
group-onsemi 0:098463de4c5d 632 }
group-onsemi 0:098463de4c5d 633
group-onsemi 0:098463de4c5d 634 return tx_length;
group-onsemi 0:098463de4c5d 635 }
group-onsemi 0:098463de4c5d 636
group-onsemi 0:098463de4c5d 637 /**
group-onsemi 0:098463de4c5d 638 * Begin asynchronous RX transfer (enable interrupt for data collecting)
group-onsemi 0:098463de4c5d 639 * The used buffer is specified in the serial object, rx_buff
group-onsemi 0:098463de4c5d 640 *
group-onsemi 0:098463de4c5d 641 * @param obj The serial object
group-onsemi 0:098463de4c5d 642 * @param rx The buffer for sending
group-onsemi 0:098463de4c5d 643 * @param rx_length The number of words to transmit
group-onsemi 0:098463de4c5d 644 * @param rx_width The bit width of buffer word
group-onsemi 0:098463de4c5d 645 * @param handler The serial handler
group-onsemi 0:098463de4c5d 646 * @param event The logical OR of events to be registered
group-onsemi 0:098463de4c5d 647 * @param handler The serial handler
group-onsemi 0:098463de4c5d 648 * @param char_match A character in range 0-254 to be matched
group-onsemi 0:098463de4c5d 649 * @param hint A suggestion for how to use DMA with this transfer
group-onsemi 0:098463de4c5d 650 */
group-onsemi 0:098463de4c5d 651 void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
group-onsemi 0:098463de4c5d 652 {
group-onsemi 0:098463de4c5d 653 // TODO: DMA usage is currently ignored
group-onsemi 0:098463de4c5d 654 (void) hint;
group-onsemi 0:098463de4c5d 655
group-onsemi 0:098463de4c5d 656 /* Sanity check arguments */
group-onsemi 0:098463de4c5d 657 MBED_ASSERT(obj);
group-onsemi 0:098463de4c5d 658 MBED_ASSERT(rx != (void*)0);
group-onsemi 0:098463de4c5d 659 MBED_ASSERT(rx_width == 8); // support only 8b width
group-onsemi 0:098463de4c5d 660
group-onsemi 0:098463de4c5d 661 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 662 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 663
group-onsemi 0:098463de4c5d 664 serial_enable_event(obj, SERIAL_EVENT_RX_ALL, 0);
group-onsemi 0:098463de4c5d 665 serial_enable_event(obj, event, 1);
group-onsemi 0:098463de4c5d 666
group-onsemi 0:098463de4c5d 667 // set CharMatch
group-onsemi 0:098463de4c5d 668 obj->char_match = char_match;
group-onsemi 0:098463de4c5d 669
group-onsemi 0:098463de4c5d 670 serial_rx_buffer_set(obj, rx, rx_length, rx_width);
group-onsemi 0:098463de4c5d 671
group-onsemi 0:098463de4c5d 672 IRQn_Type irq_n = serial_get_irq_n(obj);
group-onsemi 0:098463de4c5d 673 NVIC_ClearPendingIRQ(irq_n);
group-onsemi 0:098463de4c5d 674 NVIC_DisableIRQ(irq_n);
group-onsemi 0:098463de4c5d 675 NVIC_SetPriority(irq_n, 0);
group-onsemi 0:098463de4c5d 676 NVIC_SetVector(irq_n, (uint32_t)handler);
group-onsemi 0:098463de4c5d 677 NVIC_EnableIRQ(irq_n);
group-onsemi 0:098463de4c5d 678
group-onsemi 0:098463de4c5d 679 // following HAL function will enable the RXNE interrupt + error interrupts
group-onsemi 0:098463de4c5d 680 HAL_UART_Receive_IT(huart, (uint8_t*)rx, rx_length);
group-onsemi 0:098463de4c5d 681 }
group-onsemi 0:098463de4c5d 682
group-onsemi 0:098463de4c5d 683 /**
group-onsemi 0:098463de4c5d 684 * Attempts to determine if the serial peripheral is already in use for TX
group-onsemi 0:098463de4c5d 685 *
group-onsemi 0:098463de4c5d 686 * @param obj The serial object
group-onsemi 0:098463de4c5d 687 * @return Non-zero if the TX transaction is ongoing, 0 otherwise
group-onsemi 0:098463de4c5d 688 */
group-onsemi 0:098463de4c5d 689 uint8_t serial_tx_active(serial_t *obj)
group-onsemi 0:098463de4c5d 690 {
group-onsemi 0:098463de4c5d 691 MBED_ASSERT(obj);
group-onsemi 0:098463de4c5d 692
group-onsemi 0:098463de4c5d 693 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 694 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 695
group-onsemi 0:098463de4c5d 696 return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_TX) ? 1 : 0);
group-onsemi 0:098463de4c5d 697 }
group-onsemi 0:098463de4c5d 698
group-onsemi 0:098463de4c5d 699 /**
group-onsemi 0:098463de4c5d 700 * Attempts to determine if the serial peripheral is already in use for RX
group-onsemi 0:098463de4c5d 701 *
group-onsemi 0:098463de4c5d 702 * @param obj The serial object
group-onsemi 0:098463de4c5d 703 * @return Non-zero if the RX transaction is ongoing, 0 otherwise
group-onsemi 0:098463de4c5d 704 */
group-onsemi 0:098463de4c5d 705 uint8_t serial_rx_active(serial_t *obj)
group-onsemi 0:098463de4c5d 706 {
group-onsemi 0:098463de4c5d 707 MBED_ASSERT(obj);
group-onsemi 0:098463de4c5d 708
group-onsemi 0:098463de4c5d 709 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 710 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 711
group-onsemi 0:098463de4c5d 712 return ((HAL_UART_GetState(huart) == HAL_UART_STATE_BUSY_RX) ? 1 : 0);
group-onsemi 0:098463de4c5d 713 }
group-onsemi 0:098463de4c5d 714
group-onsemi 0:098463de4c5d 715 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
group-onsemi 0:098463de4c5d 716 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
group-onsemi 0:098463de4c5d 717 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
group-onsemi 0:098463de4c5d 718 }
group-onsemi 0:098463de4c5d 719 }
group-onsemi 0:098463de4c5d 720
group-onsemi 0:098463de4c5d 721 /**
group-onsemi 0:098463de4c5d 722 * The asynchronous TX and RX handler.
group-onsemi 0:098463de4c5d 723 *
group-onsemi 0:098463de4c5d 724 * @param obj The serial object
group-onsemi 0:098463de4c5d 725 * @return Returns event flags if a TX/RX transfer termination condition was met or 0 otherwise
group-onsemi 0:098463de4c5d 726 */
group-onsemi 0:098463de4c5d 727 int serial_irq_handler_asynch(serial_t *obj)
group-onsemi 0:098463de4c5d 728 {
group-onsemi 0:098463de4c5d 729 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 730 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 731
group-onsemi 0:098463de4c5d 732 volatile int return_event = 0;
group-onsemi 0:098463de4c5d 733 uint8_t *buf = (uint8_t*)(obj->rx_buff.buffer);
group-onsemi 0:098463de4c5d 734 uint8_t i = 0;
group-onsemi 0:098463de4c5d 735
group-onsemi 0:098463de4c5d 736 // TX PART:
group-onsemi 0:098463de4c5d 737 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) {
group-onsemi 0:098463de4c5d 738 if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET) {
group-onsemi 0:098463de4c5d 739 // Return event SERIAL_EVENT_TX_COMPLETE if requested
group-onsemi 0:098463de4c5d 740 if ((obj_s->events & SERIAL_EVENT_TX_COMPLETE ) != 0) {
group-onsemi 0:098463de4c5d 741 return_event |= (SERIAL_EVENT_TX_COMPLETE & obj_s->events);
group-onsemi 0:098463de4c5d 742 }
group-onsemi 0:098463de4c5d 743 }
group-onsemi 0:098463de4c5d 744 }
group-onsemi 0:098463de4c5d 745
group-onsemi 0:098463de4c5d 746 // Handle error events
group-onsemi 0:098463de4c5d 747 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
group-onsemi 0:098463de4c5d 748 if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
group-onsemi 0:098463de4c5d 749 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
group-onsemi 0:098463de4c5d 750 return_event |= (SERIAL_EVENT_RX_PARITY_ERROR & obj_s->events);
group-onsemi 0:098463de4c5d 751 }
group-onsemi 0:098463de4c5d 752 }
group-onsemi 0:098463de4c5d 753
group-onsemi 0:098463de4c5d 754 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
group-onsemi 0:098463de4c5d 755 if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
group-onsemi 0:098463de4c5d 756 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
group-onsemi 0:098463de4c5d 757 return_event |= (SERIAL_EVENT_RX_FRAMING_ERROR & obj_s->events);
group-onsemi 0:098463de4c5d 758 }
group-onsemi 0:098463de4c5d 759 }
group-onsemi 0:098463de4c5d 760
group-onsemi 0:098463de4c5d 761 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_NE) != RESET) {
group-onsemi 0:098463de4c5d 762 if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
group-onsemi 0:098463de4c5d 763 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
group-onsemi 0:098463de4c5d 764 }
group-onsemi 0:098463de4c5d 765 }
group-onsemi 0:098463de4c5d 766
group-onsemi 0:098463de4c5d 767 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
group-onsemi 0:098463de4c5d 768 if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
group-onsemi 0:098463de4c5d 769 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
group-onsemi 0:098463de4c5d 770 return_event |= (SERIAL_EVENT_RX_OVERRUN_ERROR & obj_s->events);
group-onsemi 0:098463de4c5d 771 }
group-onsemi 0:098463de4c5d 772 }
group-onsemi 0:098463de4c5d 773
group-onsemi 0:098463de4c5d 774 HAL_UART_IRQHandler(huart);
group-onsemi 0:098463de4c5d 775
group-onsemi 0:098463de4c5d 776 // Abort if an error occurs
group-onsemi 0:098463de4c5d 777 if (return_event & SERIAL_EVENT_RX_PARITY_ERROR ||
group-onsemi 0:098463de4c5d 778 return_event & SERIAL_EVENT_RX_FRAMING_ERROR ||
group-onsemi 0:098463de4c5d 779 return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
group-onsemi 0:098463de4c5d 780 return return_event;
group-onsemi 0:098463de4c5d 781 }
group-onsemi 0:098463de4c5d 782
group-onsemi 0:098463de4c5d 783 //RX PART
group-onsemi 0:098463de4c5d 784 if (huart->RxXferSize != 0) {
group-onsemi 0:098463de4c5d 785 obj->rx_buff.pos = huart->RxXferSize - huart->RxXferCount;
group-onsemi 0:098463de4c5d 786 }
group-onsemi 0:098463de4c5d 787 if ((huart->RxXferCount == 0) && (obj->rx_buff.pos >= (obj->rx_buff.length - 1))) {
group-onsemi 0:098463de4c5d 788 return_event |= (SERIAL_EVENT_RX_COMPLETE & obj_s->events);
group-onsemi 0:098463de4c5d 789 }
group-onsemi 0:098463de4c5d 790
group-onsemi 0:098463de4c5d 791 // Check if char_match is present
group-onsemi 0:098463de4c5d 792 if (obj_s->events & SERIAL_EVENT_RX_CHARACTER_MATCH) {
group-onsemi 0:098463de4c5d 793 if (buf != NULL) {
group-onsemi 0:098463de4c5d 794 for (i = 0; i < obj->rx_buff.pos; i++) {
group-onsemi 0:098463de4c5d 795 if (buf[i] == obj->char_match) {
group-onsemi 0:098463de4c5d 796 obj->rx_buff.pos = i;
group-onsemi 0:098463de4c5d 797 return_event |= (SERIAL_EVENT_RX_CHARACTER_MATCH & obj_s->events);
group-onsemi 0:098463de4c5d 798 serial_rx_abort_asynch(obj);
group-onsemi 0:098463de4c5d 799 break;
group-onsemi 0:098463de4c5d 800 }
group-onsemi 0:098463de4c5d 801 }
group-onsemi 0:098463de4c5d 802 }
group-onsemi 0:098463de4c5d 803 }
group-onsemi 0:098463de4c5d 804
group-onsemi 0:098463de4c5d 805 return return_event;
group-onsemi 0:098463de4c5d 806 }
group-onsemi 0:098463de4c5d 807
group-onsemi 0:098463de4c5d 808 /**
group-onsemi 0:098463de4c5d 809 * Abort the ongoing TX transaction. It disables the enabled interupt for TX and
group-onsemi 0:098463de4c5d 810 * flush TX hardware buffer if TX FIFO is used
group-onsemi 0:098463de4c5d 811 *
group-onsemi 0:098463de4c5d 812 * @param obj The serial object
group-onsemi 0:098463de4c5d 813 */
group-onsemi 0:098463de4c5d 814 void serial_tx_abort_asynch(serial_t *obj)
group-onsemi 0:098463de4c5d 815 {
group-onsemi 0:098463de4c5d 816 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 817 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 818
group-onsemi 0:098463de4c5d 819 __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
group-onsemi 0:098463de4c5d 820 __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
group-onsemi 0:098463de4c5d 821
group-onsemi 0:098463de4c5d 822 // clear flags
group-onsemi 0:098463de4c5d 823 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
group-onsemi 0:098463de4c5d 824
group-onsemi 0:098463de4c5d 825 // reset states
group-onsemi 0:098463de4c5d 826 huart->TxXferCount = 0;
group-onsemi 0:098463de4c5d 827 // update handle state
group-onsemi 0:098463de4c5d 828 if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) {
group-onsemi 0:098463de4c5d 829 huart->gState = HAL_UART_STATE_BUSY_RX;
group-onsemi 0:098463de4c5d 830 } else {
group-onsemi 0:098463de4c5d 831 huart->gState = HAL_UART_STATE_READY;
group-onsemi 0:098463de4c5d 832 }
group-onsemi 0:098463de4c5d 833 }
group-onsemi 0:098463de4c5d 834
group-onsemi 0:098463de4c5d 835 /**
group-onsemi 0:098463de4c5d 836 * Abort the ongoing RX transaction It disables the enabled interrupt for RX and
group-onsemi 0:098463de4c5d 837 * flush RX hardware buffer if RX FIFO is used
group-onsemi 0:098463de4c5d 838 *
group-onsemi 0:098463de4c5d 839 * @param obj The serial object
group-onsemi 0:098463de4c5d 840 */
group-onsemi 0:098463de4c5d 841 void serial_rx_abort_asynch(serial_t *obj)
group-onsemi 0:098463de4c5d 842 {
group-onsemi 0:098463de4c5d 843 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 844 UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
group-onsemi 0:098463de4c5d 845
group-onsemi 0:098463de4c5d 846 // disable interrupts
group-onsemi 0:098463de4c5d 847 __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
group-onsemi 0:098463de4c5d 848 __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
group-onsemi 0:098463de4c5d 849 __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
group-onsemi 0:098463de4c5d 850
group-onsemi 0:098463de4c5d 851 // clear flags
group-onsemi 0:098463de4c5d 852 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF | UART_CLEAR_FEF | UART_CLEAR_OREF);
group-onsemi 0:098463de4c5d 853 volatile uint32_t tmpval = huart->Instance->RDR; // Clear RXNE flag
group-onsemi 0:098463de4c5d 854
group-onsemi 0:098463de4c5d 855 // reset states
group-onsemi 0:098463de4c5d 856 huart->RxXferCount = 0;
group-onsemi 0:098463de4c5d 857 // update handle state
group-onsemi 0:098463de4c5d 858 if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) {
group-onsemi 0:098463de4c5d 859 huart->RxState = HAL_UART_STATE_BUSY_TX;
group-onsemi 0:098463de4c5d 860 } else {
group-onsemi 0:098463de4c5d 861 huart->RxState = HAL_UART_STATE_READY;
group-onsemi 0:098463de4c5d 862 }
group-onsemi 0:098463de4c5d 863 }
group-onsemi 0:098463de4c5d 864
group-onsemi 0:098463de4c5d 865 #endif
group-onsemi 0:098463de4c5d 866
group-onsemi 0:098463de4c5d 867 #if DEVICE_SERIAL_FC
group-onsemi 0:098463de4c5d 868
group-onsemi 0:098463de4c5d 869 /**
group-onsemi 0:098463de4c5d 870 * Set HW Control Flow
group-onsemi 0:098463de4c5d 871 * @param obj The serial object
group-onsemi 0:098463de4c5d 872 * @param type The Control Flow type (FlowControlNone, FlowControlRTS, FlowControlCTS, FlowControlRTSCTS)
group-onsemi 0:098463de4c5d 873 * @param rxflow Pin for the rxflow
group-onsemi 0:098463de4c5d 874 * @param txflow Pin for the txflow
group-onsemi 0:098463de4c5d 875 */
group-onsemi 0:098463de4c5d 876 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
group-onsemi 0:098463de4c5d 877 {
group-onsemi 0:098463de4c5d 878 struct serial_s *obj_s = SERIAL_S(obj);
group-onsemi 0:098463de4c5d 879
group-onsemi 0:098463de4c5d 880 // Determine the UART to use (UART_1, UART_2, ...)
group-onsemi 0:098463de4c5d 881 UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
group-onsemi 0:098463de4c5d 882 UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
group-onsemi 0:098463de4c5d 883
group-onsemi 0:098463de4c5d 884 // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
group-onsemi 0:098463de4c5d 885 obj_s->uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
group-onsemi 0:098463de4c5d 886 MBED_ASSERT(obj_s->uart != (UARTName)NC);
group-onsemi 0:098463de4c5d 887
group-onsemi 0:098463de4c5d 888 if(type == FlowControlNone) {
group-onsemi 0:098463de4c5d 889 // Disable hardware flow control
group-onsemi 0:098463de4c5d 890 obj_s->hw_flow_ctl = UART_HWCONTROL_NONE;
group-onsemi 0:098463de4c5d 891 }
group-onsemi 0:098463de4c5d 892 if (type == FlowControlRTS) {
group-onsemi 0:098463de4c5d 893 // Enable RTS
group-onsemi 0:098463de4c5d 894 MBED_ASSERT(uart_rts != (UARTName)NC);
group-onsemi 0:098463de4c5d 895 obj_s->hw_flow_ctl = UART_HWCONTROL_RTS;
group-onsemi 0:098463de4c5d 896 obj_s->pin_rts = rxflow;
group-onsemi 0:098463de4c5d 897 // Enable the pin for RTS function
group-onsemi 0:098463de4c5d 898 pinmap_pinout(rxflow, PinMap_UART_RTS);
group-onsemi 0:098463de4c5d 899 }
group-onsemi 0:098463de4c5d 900 if (type == FlowControlCTS) {
group-onsemi 0:098463de4c5d 901 // Enable CTS
group-onsemi 0:098463de4c5d 902 MBED_ASSERT(uart_cts != (UARTName)NC);
group-onsemi 0:098463de4c5d 903 obj_s->hw_flow_ctl = UART_HWCONTROL_CTS;
group-onsemi 0:098463de4c5d 904 obj_s->pin_cts = txflow;
group-onsemi 0:098463de4c5d 905 // Enable the pin for CTS function
group-onsemi 0:098463de4c5d 906 pinmap_pinout(txflow, PinMap_UART_CTS);
group-onsemi 0:098463de4c5d 907 }
group-onsemi 0:098463de4c5d 908 if (type == FlowControlRTSCTS) {
group-onsemi 0:098463de4c5d 909 // Enable CTS & RTS
group-onsemi 0:098463de4c5d 910 MBED_ASSERT(uart_rts != (UARTName)NC);
group-onsemi 0:098463de4c5d 911 MBED_ASSERT(uart_cts != (UARTName)NC);
group-onsemi 0:098463de4c5d 912 obj_s->hw_flow_ctl = UART_HWCONTROL_RTS_CTS;
group-onsemi 0:098463de4c5d 913 obj_s->pin_rts = rxflow;
group-onsemi 0:098463de4c5d 914 obj_s->pin_cts = txflow;
group-onsemi 0:098463de4c5d 915 // Enable the pin for CTS function
group-onsemi 0:098463de4c5d 916 pinmap_pinout(txflow, PinMap_UART_CTS);
group-onsemi 0:098463de4c5d 917 // Enable the pin for RTS function
group-onsemi 0:098463de4c5d 918 pinmap_pinout(rxflow, PinMap_UART_RTS);
group-onsemi 0:098463de4c5d 919 }
group-onsemi 0:098463de4c5d 920
group-onsemi 0:098463de4c5d 921 init_uart(obj);
group-onsemi 0:098463de4c5d 922 }
group-onsemi 0:098463de4c5d 923
group-onsemi 0:098463de4c5d 924 #endif
group-onsemi 0:098463de4c5d 925
group-onsemi 0:098463de4c5d 926 #endif