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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /**
group-onsemi 0:098463de4c5d 2 ******************************************************************************
group-onsemi 0:098463de4c5d 3 * @file stm32f7xx_hal_tim.c
group-onsemi 0:098463de4c5d 4 * @author MCD Application Team
group-onsemi 0:098463de4c5d 5 * @version V1.1.2
group-onsemi 0:098463de4c5d 6 * @date 23-September-2016
group-onsemi 0:098463de4c5d 7 * @brief TIM HAL module driver.
group-onsemi 0:098463de4c5d 8 * This file provides firmware functions to manage the following
group-onsemi 0:098463de4c5d 9 * functionalities of the Timer (TIM) peripheral:
group-onsemi 0:098463de4c5d 10 * + Time Base Initialization
group-onsemi 0:098463de4c5d 11 * + Time Base Start
group-onsemi 0:098463de4c5d 12 * + Time Base Start Interruption
group-onsemi 0:098463de4c5d 13 * + Time Base Start DMA
group-onsemi 0:098463de4c5d 14 * + Time Output Compare/PWM Initialization
group-onsemi 0:098463de4c5d 15 * + Time Output Compare/PWM Channel Configuration
group-onsemi 0:098463de4c5d 16 * + Time Output Compare/PWM Start
group-onsemi 0:098463de4c5d 17 * + Time Output Compare/PWM Start Interruption
group-onsemi 0:098463de4c5d 18 * + Time Output Compare/PWM Start DMA
group-onsemi 0:098463de4c5d 19 * + Time Input Capture Initialization
group-onsemi 0:098463de4c5d 20 * + Time Input Capture Channel Configuration
group-onsemi 0:098463de4c5d 21 * + Time Input Capture Start
group-onsemi 0:098463de4c5d 22 * + Time Input Capture Start Interruption
group-onsemi 0:098463de4c5d 23 * + Time Input Capture Start DMA
group-onsemi 0:098463de4c5d 24 * + Time One Pulse Initialization
group-onsemi 0:098463de4c5d 25 * + Time One Pulse Channel Configuration
group-onsemi 0:098463de4c5d 26 * + Time One Pulse Start
group-onsemi 0:098463de4c5d 27 * + Time Encoder Interface Initialization
group-onsemi 0:098463de4c5d 28 * + Time Encoder Interface Start
group-onsemi 0:098463de4c5d 29 * + Time Encoder Interface Start Interruption
group-onsemi 0:098463de4c5d 30 * + Time Encoder Interface Start DMA
group-onsemi 0:098463de4c5d 31 * + Commutation Event configuration with Interruption and DMA
group-onsemi 0:098463de4c5d 32 * + Time OCRef clear configuration
group-onsemi 0:098463de4c5d 33 * + Time External Clock configuration
group-onsemi 0:098463de4c5d 34 @verbatim
group-onsemi 0:098463de4c5d 35 ==============================================================================
group-onsemi 0:098463de4c5d 36 ##### TIMER Generic features #####
group-onsemi 0:098463de4c5d 37 ==============================================================================
group-onsemi 0:098463de4c5d 38 [..] The Timer features include:
group-onsemi 0:098463de4c5d 39 (#) 16-bit up, down, up/down auto-reload counter.
group-onsemi 0:098463de4c5d 40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
group-onsemi 0:098463de4c5d 41 counter clock frequency either by any factor between 1 and 65536.
group-onsemi 0:098463de4c5d 42 (#) Up to 4 independent channels for:
group-onsemi 0:098463de4c5d 43 (++) Input Capture
group-onsemi 0:098463de4c5d 44 (++) Output Compare
group-onsemi 0:098463de4c5d 45 (++) PWM generation (Edge and Center-aligned Mode)
group-onsemi 0:098463de4c5d 46 (++) One-pulse mode output
group-onsemi 0:098463de4c5d 47
group-onsemi 0:098463de4c5d 48 ##### How to use this driver #####
group-onsemi 0:098463de4c5d 49 ==============================================================================
group-onsemi 0:098463de4c5d 50 [..]
group-onsemi 0:098463de4c5d 51 (#) Initialize the TIM low level resources by implementing the following functions
group-onsemi 0:098463de4c5d 52 depending from feature used :
group-onsemi 0:098463de4c5d 53 (++) Time Base : HAL_TIM_Base_MspInit()
group-onsemi 0:098463de4c5d 54 (++) Input Capture : HAL_TIM_IC_MspInit()
group-onsemi 0:098463de4c5d 55 (++) Output Compare : HAL_TIM_OC_MspInit()
group-onsemi 0:098463de4c5d 56 (++) PWM generation : HAL_TIM_PWM_MspInit()
group-onsemi 0:098463de4c5d 57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
group-onsemi 0:098463de4c5d 58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
group-onsemi 0:098463de4c5d 59
group-onsemi 0:098463de4c5d 60 (#) Initialize the TIM low level resources :
group-onsemi 0:098463de4c5d 61 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
group-onsemi 0:098463de4c5d 62 (##) TIM pins configuration
group-onsemi 0:098463de4c5d 63 (+++) Enable the clock for the TIM GPIOs using the following function:
group-onsemi 0:098463de4c5d 64 __HAL_RCC_GPIOx_CLK_ENABLE();
group-onsemi 0:098463de4c5d 65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
group-onsemi 0:098463de4c5d 66
group-onsemi 0:098463de4c5d 67 (#) The external Clock can be configured, if needed (the default clock is the
group-onsemi 0:098463de4c5d 68 internal clock from the APBx), using the following function:
group-onsemi 0:098463de4c5d 69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
group-onsemi 0:098463de4c5d 70 any start function.
group-onsemi 0:098463de4c5d 71
group-onsemi 0:098463de4c5d 72 (#) Configure the TIM in the desired functioning mode using one of the
group-onsemi 0:098463de4c5d 73 initialization function of this driver:
group-onsemi 0:098463de4c5d 74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
group-onsemi 0:098463de4c5d 75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
group-onsemi 0:098463de4c5d 76 Output Compare signal.
group-onsemi 0:098463de4c5d 77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
group-onsemi 0:098463de4c5d 78 PWM signal.
group-onsemi 0:098463de4c5d 79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
group-onsemi 0:098463de4c5d 80 external signal.
group-onsemi 0:098463de4c5d 81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
group-onsemi 0:098463de4c5d 82 in One Pulse Mode.
group-onsemi 0:098463de4c5d 83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
group-onsemi 0:098463de4c5d 84
group-onsemi 0:098463de4c5d 85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
group-onsemi 0:098463de4c5d 86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
group-onsemi 0:098463de4c5d 87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
group-onsemi 0:098463de4c5d 88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
group-onsemi 0:098463de4c5d 89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
group-onsemi 0:098463de4c5d 90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
group-onsemi 0:098463de4c5d 91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
group-onsemi 0:098463de4c5d 92
group-onsemi 0:098463de4c5d 93 (#) The DMA Burst is managed with the two following functions:
group-onsemi 0:098463de4c5d 94 HAL_TIM_DMABurst_WriteStart()
group-onsemi 0:098463de4c5d 95 HAL_TIM_DMABurst_ReadStart()
group-onsemi 0:098463de4c5d 96
group-onsemi 0:098463de4c5d 97 @endverbatim
group-onsemi 0:098463de4c5d 98 ******************************************************************************
group-onsemi 0:098463de4c5d 99 * @attention
group-onsemi 0:098463de4c5d 100 *
group-onsemi 0:098463de4c5d 101 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
group-onsemi 0:098463de4c5d 102 *
group-onsemi 0:098463de4c5d 103 * Redistribution and use in source and binary forms, with or without modification,
group-onsemi 0:098463de4c5d 104 * are permitted provided that the following conditions are met:
group-onsemi 0:098463de4c5d 105 * 1. Redistributions of source code must retain the above copyright notice,
group-onsemi 0:098463de4c5d 106 * this list of conditions and the following disclaimer.
group-onsemi 0:098463de4c5d 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
group-onsemi 0:098463de4c5d 108 * this list of conditions and the following disclaimer in the documentation
group-onsemi 0:098463de4c5d 109 * and/or other materials provided with the distribution.
group-onsemi 0:098463de4c5d 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
group-onsemi 0:098463de4c5d 111 * may be used to endorse or promote products derived from this software
group-onsemi 0:098463de4c5d 112 * without specific prior written permission.
group-onsemi 0:098463de4c5d 113 *
group-onsemi 0:098463de4c5d 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
group-onsemi 0:098463de4c5d 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
group-onsemi 0:098463de4c5d 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
group-onsemi 0:098463de4c5d 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
group-onsemi 0:098463de4c5d 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
group-onsemi 0:098463de4c5d 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
group-onsemi 0:098463de4c5d 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
group-onsemi 0:098463de4c5d 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
group-onsemi 0:098463de4c5d 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
group-onsemi 0:098463de4c5d 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
group-onsemi 0:098463de4c5d 124 *
group-onsemi 0:098463de4c5d 125 ******************************************************************************
group-onsemi 0:098463de4c5d 126 */
group-onsemi 0:098463de4c5d 127
group-onsemi 0:098463de4c5d 128 /* Includes ------------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 129 #include "stm32f7xx_hal.h"
group-onsemi 0:098463de4c5d 130
group-onsemi 0:098463de4c5d 131 /** @addtogroup STM32F7xx_HAL_Driver
group-onsemi 0:098463de4c5d 132 * @{
group-onsemi 0:098463de4c5d 133 */
group-onsemi 0:098463de4c5d 134
group-onsemi 0:098463de4c5d 135 /** @defgroup TIM TIM
group-onsemi 0:098463de4c5d 136 * @brief TIM HAL module driver
group-onsemi 0:098463de4c5d 137 * @{
group-onsemi 0:098463de4c5d 138 */
group-onsemi 0:098463de4c5d 139
group-onsemi 0:098463de4c5d 140 #ifdef HAL_TIM_MODULE_ENABLED
group-onsemi 0:098463de4c5d 141
group-onsemi 0:098463de4c5d 142 /* Private typedef -----------------------------------------------------------*/
group-onsemi 0:098463de4c5d 143 /* Private define ------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 144 /* Private macro -------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 145 /* Private variables ---------------------------------------------------------*/
group-onsemi 0:098463de4c5d 146 /** @addtogroup TIM_Private_Functions
group-onsemi 0:098463de4c5d 147 * @{
group-onsemi 0:098463de4c5d 148 */
group-onsemi 0:098463de4c5d 149 /* Private function prototypes -----------------------------------------------*/
group-onsemi 0:098463de4c5d 150 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
group-onsemi 0:098463de4c5d 151 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
group-onsemi 0:098463de4c5d 152 uint32_t TIM_ICFilter);
group-onsemi 0:098463de4c5d 153 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
group-onsemi 0:098463de4c5d 154 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
group-onsemi 0:098463de4c5d 155 uint32_t TIM_ICFilter);
group-onsemi 0:098463de4c5d 156 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
group-onsemi 0:098463de4c5d 157 uint32_t TIM_ICFilter);
group-onsemi 0:098463de4c5d 158
group-onsemi 0:098463de4c5d 159 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
group-onsemi 0:098463de4c5d 160 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
group-onsemi 0:098463de4c5d 161 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
group-onsemi 0:098463de4c5d 162 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
group-onsemi 0:098463de4c5d 163 TIM_SlaveConfigTypeDef * sSlaveConfig);
group-onsemi 0:098463de4c5d 164 /**
group-onsemi 0:098463de4c5d 165 * @}
group-onsemi 0:098463de4c5d 166 */
group-onsemi 0:098463de4c5d 167
group-onsemi 0:098463de4c5d 168 /* Exported functions --------------------------------------------------------*/
group-onsemi 0:098463de4c5d 169 /** @defgroup TIM_Exported_Functions TIM Exported Functions
group-onsemi 0:098463de4c5d 170 * @{
group-onsemi 0:098463de4c5d 171 */
group-onsemi 0:098463de4c5d 172
group-onsemi 0:098463de4c5d 173 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
group-onsemi 0:098463de4c5d 174 * @brief Time Base functions
group-onsemi 0:098463de4c5d 175 *
group-onsemi 0:098463de4c5d 176 @verbatim
group-onsemi 0:098463de4c5d 177 ==============================================================================
group-onsemi 0:098463de4c5d 178 ##### Time Base functions #####
group-onsemi 0:098463de4c5d 179 ==============================================================================
group-onsemi 0:098463de4c5d 180 [..]
group-onsemi 0:098463de4c5d 181 This section provides functions allowing to:
group-onsemi 0:098463de4c5d 182 (+) Initialize and configure the TIM base.
group-onsemi 0:098463de4c5d 183 (+) De-initialize the TIM base.
group-onsemi 0:098463de4c5d 184 (+) Start the Time Base.
group-onsemi 0:098463de4c5d 185 (+) Stop the Time Base.
group-onsemi 0:098463de4c5d 186 (+) Start the Time Base and enable interrupt.
group-onsemi 0:098463de4c5d 187 (+) Stop the Time Base and disable interrupt.
group-onsemi 0:098463de4c5d 188 (+) Start the Time Base and enable DMA transfer.
group-onsemi 0:098463de4c5d 189 (+) Stop the Time Base and disable DMA transfer.
group-onsemi 0:098463de4c5d 190
group-onsemi 0:098463de4c5d 191 @endverbatim
group-onsemi 0:098463de4c5d 192 * @{
group-onsemi 0:098463de4c5d 193 */
group-onsemi 0:098463de4c5d 194 /**
group-onsemi 0:098463de4c5d 195 * @brief Initializes the TIM Time base Unit according to the specified
group-onsemi 0:098463de4c5d 196 * parameters in the TIM_HandleTypeDef and create the associated handle.
group-onsemi 0:098463de4c5d 197 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 198 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 199 * @retval HAL status
group-onsemi 0:098463de4c5d 200 */
group-onsemi 0:098463de4c5d 201 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 202 {
group-onsemi 0:098463de4c5d 203 /* Check the TIM handle allocation */
group-onsemi 0:098463de4c5d 204 if(htim == NULL)
group-onsemi 0:098463de4c5d 205 {
group-onsemi 0:098463de4c5d 206 return HAL_ERROR;
group-onsemi 0:098463de4c5d 207 }
group-onsemi 0:098463de4c5d 208
group-onsemi 0:098463de4c5d 209 /* Check the parameters */
group-onsemi 0:098463de4c5d 210 assert_param(IS_TIM_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 211 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
group-onsemi 0:098463de4c5d 212 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
group-onsemi 0:098463de4c5d 213
group-onsemi 0:098463de4c5d 214 if(htim->State == HAL_TIM_STATE_RESET)
group-onsemi 0:098463de4c5d 215 {
group-onsemi 0:098463de4c5d 216 /* Init the low level hardware : GPIO, CLOCK, NVIC */
group-onsemi 0:098463de4c5d 217 HAL_TIM_Base_MspInit(htim);
group-onsemi 0:098463de4c5d 218 }
group-onsemi 0:098463de4c5d 219
group-onsemi 0:098463de4c5d 220 /* Set the TIM state */
group-onsemi 0:098463de4c5d 221 htim->State= HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 222
group-onsemi 0:098463de4c5d 223 /* Set the Time Base configuration */
group-onsemi 0:098463de4c5d 224 TIM_Base_SetConfig(htim->Instance, &htim->Init);
group-onsemi 0:098463de4c5d 225
group-onsemi 0:098463de4c5d 226 /* Initialize the TIM state*/
group-onsemi 0:098463de4c5d 227 htim->State= HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 228
group-onsemi 0:098463de4c5d 229 return HAL_OK;
group-onsemi 0:098463de4c5d 230 }
group-onsemi 0:098463de4c5d 231
group-onsemi 0:098463de4c5d 232 /**
group-onsemi 0:098463de4c5d 233 * @brief DeInitializes the TIM Base peripheral
group-onsemi 0:098463de4c5d 234 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 235 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 236 * @retval HAL status
group-onsemi 0:098463de4c5d 237 */
group-onsemi 0:098463de4c5d 238 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 239 {
group-onsemi 0:098463de4c5d 240 /* Check the parameters */
group-onsemi 0:098463de4c5d 241 assert_param(IS_TIM_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 242
group-onsemi 0:098463de4c5d 243 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 244
group-onsemi 0:098463de4c5d 245 /* Disable the TIM Peripheral Clock */
group-onsemi 0:098463de4c5d 246 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 247
group-onsemi 0:098463de4c5d 248 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
group-onsemi 0:098463de4c5d 249 HAL_TIM_Base_MspDeInit(htim);
group-onsemi 0:098463de4c5d 250
group-onsemi 0:098463de4c5d 251 /* Change TIM state */
group-onsemi 0:098463de4c5d 252 htim->State = HAL_TIM_STATE_RESET;
group-onsemi 0:098463de4c5d 253
group-onsemi 0:098463de4c5d 254 /* Release Lock */
group-onsemi 0:098463de4c5d 255 __HAL_UNLOCK(htim);
group-onsemi 0:098463de4c5d 256
group-onsemi 0:098463de4c5d 257 return HAL_OK;
group-onsemi 0:098463de4c5d 258 }
group-onsemi 0:098463de4c5d 259
group-onsemi 0:098463de4c5d 260 /**
group-onsemi 0:098463de4c5d 261 * @brief Initializes the TIM Base MSP.
group-onsemi 0:098463de4c5d 262 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 263 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 264 * @retval None
group-onsemi 0:098463de4c5d 265 */
group-onsemi 0:098463de4c5d 266 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 267 {
group-onsemi 0:098463de4c5d 268 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 269 UNUSED(htim);
group-onsemi 0:098463de4c5d 270
group-onsemi 0:098463de4c5d 271 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 272 the HAL_TIM_Base_MspInit could be implemented in the user file
group-onsemi 0:098463de4c5d 273 */
group-onsemi 0:098463de4c5d 274 }
group-onsemi 0:098463de4c5d 275
group-onsemi 0:098463de4c5d 276 /**
group-onsemi 0:098463de4c5d 277 * @brief DeInitializes TIM Base MSP.
group-onsemi 0:098463de4c5d 278 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 279 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 280 * @retval None
group-onsemi 0:098463de4c5d 281 */
group-onsemi 0:098463de4c5d 282 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 283 {
group-onsemi 0:098463de4c5d 284 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 285 UNUSED(htim);
group-onsemi 0:098463de4c5d 286
group-onsemi 0:098463de4c5d 287 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 288 the HAL_TIM_Base_MspDeInit could be implemented in the user file
group-onsemi 0:098463de4c5d 289 */
group-onsemi 0:098463de4c5d 290 }
group-onsemi 0:098463de4c5d 291
group-onsemi 0:098463de4c5d 292 /**
group-onsemi 0:098463de4c5d 293 * @brief Starts the TIM Base generation.
group-onsemi 0:098463de4c5d 294 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 295 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 296 * @retval HAL status
group-onsemi 0:098463de4c5d 297 */
group-onsemi 0:098463de4c5d 298 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 299 {
group-onsemi 0:098463de4c5d 300 /* Check the parameters */
group-onsemi 0:098463de4c5d 301 assert_param(IS_TIM_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 302
group-onsemi 0:098463de4c5d 303 /* Set the TIM state */
group-onsemi 0:098463de4c5d 304 htim->State= HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 305
group-onsemi 0:098463de4c5d 306 /* Enable the Peripheral */
group-onsemi 0:098463de4c5d 307 __HAL_TIM_ENABLE(htim);
group-onsemi 0:098463de4c5d 308
group-onsemi 0:098463de4c5d 309 /* Change the TIM state*/
group-onsemi 0:098463de4c5d 310 htim->State= HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 311
group-onsemi 0:098463de4c5d 312 /* Return function status */
group-onsemi 0:098463de4c5d 313 return HAL_OK;
group-onsemi 0:098463de4c5d 314 }
group-onsemi 0:098463de4c5d 315
group-onsemi 0:098463de4c5d 316 /**
group-onsemi 0:098463de4c5d 317 * @brief Stops the TIM Base generation.
group-onsemi 0:098463de4c5d 318 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 319 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 320 * @retval HAL status
group-onsemi 0:098463de4c5d 321 */
group-onsemi 0:098463de4c5d 322 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 323 {
group-onsemi 0:098463de4c5d 324 /* Check the parameters */
group-onsemi 0:098463de4c5d 325 assert_param(IS_TIM_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 326
group-onsemi 0:098463de4c5d 327 /* Set the TIM state */
group-onsemi 0:098463de4c5d 328 htim->State= HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 329
group-onsemi 0:098463de4c5d 330 /* Disable the Peripheral */
group-onsemi 0:098463de4c5d 331 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 332
group-onsemi 0:098463de4c5d 333 /* Change the TIM state*/
group-onsemi 0:098463de4c5d 334 htim->State= HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 335
group-onsemi 0:098463de4c5d 336 /* Return function status */
group-onsemi 0:098463de4c5d 337 return HAL_OK;
group-onsemi 0:098463de4c5d 338 }
group-onsemi 0:098463de4c5d 339
group-onsemi 0:098463de4c5d 340 /**
group-onsemi 0:098463de4c5d 341 * @brief Starts the TIM Base generation in interrupt mode.
group-onsemi 0:098463de4c5d 342 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 343 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 344 * @retval HAL status
group-onsemi 0:098463de4c5d 345 */
group-onsemi 0:098463de4c5d 346 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 347 {
group-onsemi 0:098463de4c5d 348 /* Check the parameters */
group-onsemi 0:098463de4c5d 349 assert_param(IS_TIM_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 350
group-onsemi 0:098463de4c5d 351 /* Enable the TIM Update interrupt */
group-onsemi 0:098463de4c5d 352 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
group-onsemi 0:098463de4c5d 353
group-onsemi 0:098463de4c5d 354 /* Enable the Peripheral */
group-onsemi 0:098463de4c5d 355 __HAL_TIM_ENABLE(htim);
group-onsemi 0:098463de4c5d 356
group-onsemi 0:098463de4c5d 357 /* Return function status */
group-onsemi 0:098463de4c5d 358 return HAL_OK;
group-onsemi 0:098463de4c5d 359 }
group-onsemi 0:098463de4c5d 360
group-onsemi 0:098463de4c5d 361 /**
group-onsemi 0:098463de4c5d 362 * @brief Stops the TIM Base generation in interrupt mode.
group-onsemi 0:098463de4c5d 363 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 364 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 365 * @retval HAL status
group-onsemi 0:098463de4c5d 366 */
group-onsemi 0:098463de4c5d 367 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 368 {
group-onsemi 0:098463de4c5d 369 /* Check the parameters */
group-onsemi 0:098463de4c5d 370 assert_param(IS_TIM_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 371 /* Disable the TIM Update interrupt */
group-onsemi 0:098463de4c5d 372 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
group-onsemi 0:098463de4c5d 373
group-onsemi 0:098463de4c5d 374 /* Disable the Peripheral */
group-onsemi 0:098463de4c5d 375 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 376
group-onsemi 0:098463de4c5d 377 /* Return function status */
group-onsemi 0:098463de4c5d 378 return HAL_OK;
group-onsemi 0:098463de4c5d 379 }
group-onsemi 0:098463de4c5d 380
group-onsemi 0:098463de4c5d 381 /**
group-onsemi 0:098463de4c5d 382 * @brief Starts the TIM Base generation in DMA mode.
group-onsemi 0:098463de4c5d 383 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 384 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 385 * @param pData: The source Buffer address.
group-onsemi 0:098463de4c5d 386 * @param Length: The length of data to be transferred from memory to peripheral.
group-onsemi 0:098463de4c5d 387 * @retval HAL status
group-onsemi 0:098463de4c5d 388 */
group-onsemi 0:098463de4c5d 389 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
group-onsemi 0:098463de4c5d 390 {
group-onsemi 0:098463de4c5d 391 /* Check the parameters */
group-onsemi 0:098463de4c5d 392 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 393
group-onsemi 0:098463de4c5d 394 if((htim->State == HAL_TIM_STATE_BUSY))
group-onsemi 0:098463de4c5d 395 {
group-onsemi 0:098463de4c5d 396 return HAL_BUSY;
group-onsemi 0:098463de4c5d 397 }
group-onsemi 0:098463de4c5d 398 else if((htim->State == HAL_TIM_STATE_READY))
group-onsemi 0:098463de4c5d 399 {
group-onsemi 0:098463de4c5d 400 if((pData == 0 ) && (Length > 0))
group-onsemi 0:098463de4c5d 401 {
group-onsemi 0:098463de4c5d 402 return HAL_ERROR;
group-onsemi 0:098463de4c5d 403 }
group-onsemi 0:098463de4c5d 404 else
group-onsemi 0:098463de4c5d 405 {
group-onsemi 0:098463de4c5d 406 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 407 }
group-onsemi 0:098463de4c5d 408 }
group-onsemi 0:098463de4c5d 409 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 410 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
group-onsemi 0:098463de4c5d 411
group-onsemi 0:098463de4c5d 412 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 413 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 414
group-onsemi 0:098463de4c5d 415 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 416 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
group-onsemi 0:098463de4c5d 417
group-onsemi 0:098463de4c5d 418 /* Enable the TIM Update DMA request */
group-onsemi 0:098463de4c5d 419 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
group-onsemi 0:098463de4c5d 420
group-onsemi 0:098463de4c5d 421 /* Enable the Peripheral */
group-onsemi 0:098463de4c5d 422 __HAL_TIM_ENABLE(htim);
group-onsemi 0:098463de4c5d 423
group-onsemi 0:098463de4c5d 424 /* Return function status */
group-onsemi 0:098463de4c5d 425 return HAL_OK;
group-onsemi 0:098463de4c5d 426 }
group-onsemi 0:098463de4c5d 427
group-onsemi 0:098463de4c5d 428 /**
group-onsemi 0:098463de4c5d 429 * @brief Stops the TIM Base generation in DMA mode.
group-onsemi 0:098463de4c5d 430 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 431 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 432 * @retval HAL status
group-onsemi 0:098463de4c5d 433 */
group-onsemi 0:098463de4c5d 434 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 435 {
group-onsemi 0:098463de4c5d 436 /* Check the parameters */
group-onsemi 0:098463de4c5d 437 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 438
group-onsemi 0:098463de4c5d 439 /* Disable the TIM Update DMA request */
group-onsemi 0:098463de4c5d 440 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
group-onsemi 0:098463de4c5d 441
group-onsemi 0:098463de4c5d 442 /* Disable the Peripheral */
group-onsemi 0:098463de4c5d 443 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 444
group-onsemi 0:098463de4c5d 445 /* Change the htim state */
group-onsemi 0:098463de4c5d 446 htim->State = HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 447
group-onsemi 0:098463de4c5d 448 /* Return function status */
group-onsemi 0:098463de4c5d 449 return HAL_OK;
group-onsemi 0:098463de4c5d 450 }
group-onsemi 0:098463de4c5d 451
group-onsemi 0:098463de4c5d 452 /**
group-onsemi 0:098463de4c5d 453 * @}
group-onsemi 0:098463de4c5d 454 */
group-onsemi 0:098463de4c5d 455
group-onsemi 0:098463de4c5d 456 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
group-onsemi 0:098463de4c5d 457 * @brief Time Output Compare functions
group-onsemi 0:098463de4c5d 458 *
group-onsemi 0:098463de4c5d 459 @verbatim
group-onsemi 0:098463de4c5d 460 ==============================================================================
group-onsemi 0:098463de4c5d 461 ##### Time Output Compare functions #####
group-onsemi 0:098463de4c5d 462 ==============================================================================
group-onsemi 0:098463de4c5d 463 [..]
group-onsemi 0:098463de4c5d 464 This section provides functions allowing to:
group-onsemi 0:098463de4c5d 465 (+) Initialize and configure the TIM Output Compare.
group-onsemi 0:098463de4c5d 466 (+) De-initialize the TIM Output Compare.
group-onsemi 0:098463de4c5d 467 (+) Start the Time Output Compare.
group-onsemi 0:098463de4c5d 468 (+) Stop the Time Output Compare.
group-onsemi 0:098463de4c5d 469 (+) Start the Time Output Compare and enable interrupt.
group-onsemi 0:098463de4c5d 470 (+) Stop the Time Output Compare and disable interrupt.
group-onsemi 0:098463de4c5d 471 (+) Start the Time Output Compare and enable DMA transfer.
group-onsemi 0:098463de4c5d 472 (+) Stop the Time Output Compare and disable DMA transfer.
group-onsemi 0:098463de4c5d 473
group-onsemi 0:098463de4c5d 474 @endverbatim
group-onsemi 0:098463de4c5d 475 * @{
group-onsemi 0:098463de4c5d 476 */
group-onsemi 0:098463de4c5d 477 /**
group-onsemi 0:098463de4c5d 478 * @brief Initializes the TIM Output Compare according to the specified
group-onsemi 0:098463de4c5d 479 * parameters in the TIM_HandleTypeDef and create the associated handle.
group-onsemi 0:098463de4c5d 480 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 481 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 482 * @retval HAL status
group-onsemi 0:098463de4c5d 483 */
group-onsemi 0:098463de4c5d 484 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
group-onsemi 0:098463de4c5d 485 {
group-onsemi 0:098463de4c5d 486 /* Check the TIM handle allocation */
group-onsemi 0:098463de4c5d 487 if(htim == NULL)
group-onsemi 0:098463de4c5d 488 {
group-onsemi 0:098463de4c5d 489 return HAL_ERROR;
group-onsemi 0:098463de4c5d 490 }
group-onsemi 0:098463de4c5d 491
group-onsemi 0:098463de4c5d 492 /* Check the parameters */
group-onsemi 0:098463de4c5d 493 assert_param(IS_TIM_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 494 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
group-onsemi 0:098463de4c5d 495 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
group-onsemi 0:098463de4c5d 496
group-onsemi 0:098463de4c5d 497 if(htim->State == HAL_TIM_STATE_RESET)
group-onsemi 0:098463de4c5d 498 {
group-onsemi 0:098463de4c5d 499 /* Allocate lock resource and initialize it */
group-onsemi 0:098463de4c5d 500 htim->Lock = HAL_UNLOCKED;
group-onsemi 0:098463de4c5d 501 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
group-onsemi 0:098463de4c5d 502 HAL_TIM_OC_MspInit(htim);
group-onsemi 0:098463de4c5d 503 }
group-onsemi 0:098463de4c5d 504
group-onsemi 0:098463de4c5d 505 /* Set the TIM state */
group-onsemi 0:098463de4c5d 506 htim->State= HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 507
group-onsemi 0:098463de4c5d 508 /* Init the base time for the Output Compare */
group-onsemi 0:098463de4c5d 509 TIM_Base_SetConfig(htim->Instance, &htim->Init);
group-onsemi 0:098463de4c5d 510
group-onsemi 0:098463de4c5d 511 /* Initialize the TIM state*/
group-onsemi 0:098463de4c5d 512 htim->State= HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 513
group-onsemi 0:098463de4c5d 514 return HAL_OK;
group-onsemi 0:098463de4c5d 515 }
group-onsemi 0:098463de4c5d 516
group-onsemi 0:098463de4c5d 517 /**
group-onsemi 0:098463de4c5d 518 * @brief DeInitializes the TIM peripheral
group-onsemi 0:098463de4c5d 519 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 520 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 521 * @retval HAL status
group-onsemi 0:098463de4c5d 522 */
group-onsemi 0:098463de4c5d 523 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 524 {
group-onsemi 0:098463de4c5d 525 /* Check the parameters */
group-onsemi 0:098463de4c5d 526 assert_param(IS_TIM_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 527
group-onsemi 0:098463de4c5d 528 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 529
group-onsemi 0:098463de4c5d 530 /* Disable the TIM Peripheral Clock */
group-onsemi 0:098463de4c5d 531 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 532
group-onsemi 0:098463de4c5d 533 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
group-onsemi 0:098463de4c5d 534 HAL_TIM_OC_MspDeInit(htim);
group-onsemi 0:098463de4c5d 535
group-onsemi 0:098463de4c5d 536 /* Change TIM state */
group-onsemi 0:098463de4c5d 537 htim->State = HAL_TIM_STATE_RESET;
group-onsemi 0:098463de4c5d 538
group-onsemi 0:098463de4c5d 539 /* Release Lock */
group-onsemi 0:098463de4c5d 540 __HAL_UNLOCK(htim);
group-onsemi 0:098463de4c5d 541
group-onsemi 0:098463de4c5d 542 return HAL_OK;
group-onsemi 0:098463de4c5d 543 }
group-onsemi 0:098463de4c5d 544
group-onsemi 0:098463de4c5d 545 /**
group-onsemi 0:098463de4c5d 546 * @brief Initializes the TIM Output Compare MSP.
group-onsemi 0:098463de4c5d 547 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 548 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 549 * @retval None
group-onsemi 0:098463de4c5d 550 */
group-onsemi 0:098463de4c5d 551 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 552 {
group-onsemi 0:098463de4c5d 553 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 554 UNUSED(htim);
group-onsemi 0:098463de4c5d 555
group-onsemi 0:098463de4c5d 556 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 557 the HAL_TIM_OC_MspInit could be implemented in the user file
group-onsemi 0:098463de4c5d 558 */
group-onsemi 0:098463de4c5d 559 }
group-onsemi 0:098463de4c5d 560
group-onsemi 0:098463de4c5d 561 /**
group-onsemi 0:098463de4c5d 562 * @brief DeInitializes TIM Output Compare MSP.
group-onsemi 0:098463de4c5d 563 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 564 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 565 * @retval None
group-onsemi 0:098463de4c5d 566 */
group-onsemi 0:098463de4c5d 567 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 568 {
group-onsemi 0:098463de4c5d 569 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 570 UNUSED(htim);
group-onsemi 0:098463de4c5d 571
group-onsemi 0:098463de4c5d 572 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 573 the HAL_TIM_OC_MspDeInit could be implemented in the user file
group-onsemi 0:098463de4c5d 574 */
group-onsemi 0:098463de4c5d 575 }
group-onsemi 0:098463de4c5d 576
group-onsemi 0:098463de4c5d 577 /**
group-onsemi 0:098463de4c5d 578 * @brief Starts the TIM Output Compare signal generation.
group-onsemi 0:098463de4c5d 579 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 580 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 581 * @param Channel: TIM Channel to be enabled.
group-onsemi 0:098463de4c5d 582 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 583 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 584 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 585 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 586 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 587 * @retval HAL status
group-onsemi 0:098463de4c5d 588 */
group-onsemi 0:098463de4c5d 589 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 590 {
group-onsemi 0:098463de4c5d 591 /* Check the parameters */
group-onsemi 0:098463de4c5d 592 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
group-onsemi 0:098463de4c5d 593
group-onsemi 0:098463de4c5d 594 /* Enable the Output compare channel */
group-onsemi 0:098463de4c5d 595 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 596
group-onsemi 0:098463de4c5d 597 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
group-onsemi 0:098463de4c5d 598 {
group-onsemi 0:098463de4c5d 599 /* Enable the main output */
group-onsemi 0:098463de4c5d 600 __HAL_TIM_MOE_ENABLE(htim);
group-onsemi 0:098463de4c5d 601 }
group-onsemi 0:098463de4c5d 602
group-onsemi 0:098463de4c5d 603 /* Enable the Peripheral */
group-onsemi 0:098463de4c5d 604 __HAL_TIM_ENABLE(htim);
group-onsemi 0:098463de4c5d 605
group-onsemi 0:098463de4c5d 606 /* Return function status */
group-onsemi 0:098463de4c5d 607 return HAL_OK;
group-onsemi 0:098463de4c5d 608 }
group-onsemi 0:098463de4c5d 609
group-onsemi 0:098463de4c5d 610 /**
group-onsemi 0:098463de4c5d 611 * @brief Stops the TIM Output Compare signal generation.
group-onsemi 0:098463de4c5d 612 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 613 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 614 * @param Channel: TIM Channel to be disabled.
group-onsemi 0:098463de4c5d 615 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 616 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 617 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 618 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 619 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 620 * @retval HAL status
group-onsemi 0:098463de4c5d 621 */
group-onsemi 0:098463de4c5d 622 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 623 {
group-onsemi 0:098463de4c5d 624 /* Check the parameters */
group-onsemi 0:098463de4c5d 625 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
group-onsemi 0:098463de4c5d 626
group-onsemi 0:098463de4c5d 627 /* Disable the Output compare channel */
group-onsemi 0:098463de4c5d 628 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 629
group-onsemi 0:098463de4c5d 630 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
group-onsemi 0:098463de4c5d 631 {
group-onsemi 0:098463de4c5d 632 /* Disable the Main Output */
group-onsemi 0:098463de4c5d 633 __HAL_TIM_MOE_DISABLE(htim);
group-onsemi 0:098463de4c5d 634 }
group-onsemi 0:098463de4c5d 635
group-onsemi 0:098463de4c5d 636 /* Disable the Peripheral */
group-onsemi 0:098463de4c5d 637 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 638
group-onsemi 0:098463de4c5d 639 /* Return function status */
group-onsemi 0:098463de4c5d 640 return HAL_OK;
group-onsemi 0:098463de4c5d 641 }
group-onsemi 0:098463de4c5d 642
group-onsemi 0:098463de4c5d 643 /**
group-onsemi 0:098463de4c5d 644 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
group-onsemi 0:098463de4c5d 645 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 646 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 647 * @param Channel: TIM Channel to be enabled.
group-onsemi 0:098463de4c5d 648 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 649 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 650 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 651 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 652 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 653 * @retval HAL status
group-onsemi 0:098463de4c5d 654 */
group-onsemi 0:098463de4c5d 655 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 656 {
group-onsemi 0:098463de4c5d 657 /* Check the parameters */
group-onsemi 0:098463de4c5d 658 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
group-onsemi 0:098463de4c5d 659
group-onsemi 0:098463de4c5d 660 switch (Channel)
group-onsemi 0:098463de4c5d 661 {
group-onsemi 0:098463de4c5d 662 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 663 {
group-onsemi 0:098463de4c5d 664 /* Enable the TIM Capture/Compare 1 interrupt */
group-onsemi 0:098463de4c5d 665 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
group-onsemi 0:098463de4c5d 666 }
group-onsemi 0:098463de4c5d 667 break;
group-onsemi 0:098463de4c5d 668
group-onsemi 0:098463de4c5d 669 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 670 {
group-onsemi 0:098463de4c5d 671 /* Enable the TIM Capture/Compare 2 interrupt */
group-onsemi 0:098463de4c5d 672 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
group-onsemi 0:098463de4c5d 673 }
group-onsemi 0:098463de4c5d 674 break;
group-onsemi 0:098463de4c5d 675
group-onsemi 0:098463de4c5d 676 case TIM_CHANNEL_3:
group-onsemi 0:098463de4c5d 677 {
group-onsemi 0:098463de4c5d 678 /* Enable the TIM Capture/Compare 3 interrupt */
group-onsemi 0:098463de4c5d 679 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
group-onsemi 0:098463de4c5d 680 }
group-onsemi 0:098463de4c5d 681 break;
group-onsemi 0:098463de4c5d 682
group-onsemi 0:098463de4c5d 683 case TIM_CHANNEL_4:
group-onsemi 0:098463de4c5d 684 {
group-onsemi 0:098463de4c5d 685 /* Enable the TIM Capture/Compare 4 interrupt */
group-onsemi 0:098463de4c5d 686 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
group-onsemi 0:098463de4c5d 687 }
group-onsemi 0:098463de4c5d 688 break;
group-onsemi 0:098463de4c5d 689
group-onsemi 0:098463de4c5d 690 default:
group-onsemi 0:098463de4c5d 691 break;
group-onsemi 0:098463de4c5d 692 }
group-onsemi 0:098463de4c5d 693
group-onsemi 0:098463de4c5d 694 /* Enable the Output compare channel */
group-onsemi 0:098463de4c5d 695 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 696
group-onsemi 0:098463de4c5d 697 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
group-onsemi 0:098463de4c5d 698 {
group-onsemi 0:098463de4c5d 699 /* Enable the main output */
group-onsemi 0:098463de4c5d 700 __HAL_TIM_MOE_ENABLE(htim);
group-onsemi 0:098463de4c5d 701 }
group-onsemi 0:098463de4c5d 702
group-onsemi 0:098463de4c5d 703 /* Enable the Peripheral */
group-onsemi 0:098463de4c5d 704 __HAL_TIM_ENABLE(htim);
group-onsemi 0:098463de4c5d 705
group-onsemi 0:098463de4c5d 706 /* Return function status */
group-onsemi 0:098463de4c5d 707 return HAL_OK;
group-onsemi 0:098463de4c5d 708 }
group-onsemi 0:098463de4c5d 709
group-onsemi 0:098463de4c5d 710 /**
group-onsemi 0:098463de4c5d 711 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
group-onsemi 0:098463de4c5d 712 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 713 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 714 * @param Channel: TIM Channel to be disabled.
group-onsemi 0:098463de4c5d 715 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 716 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 717 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 718 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 719 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 720 * @retval HAL status
group-onsemi 0:098463de4c5d 721 */
group-onsemi 0:098463de4c5d 722 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 723 {
group-onsemi 0:098463de4c5d 724 /* Check the parameters */
group-onsemi 0:098463de4c5d 725 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
group-onsemi 0:098463de4c5d 726
group-onsemi 0:098463de4c5d 727 switch (Channel)
group-onsemi 0:098463de4c5d 728 {
group-onsemi 0:098463de4c5d 729 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 730 {
group-onsemi 0:098463de4c5d 731 /* Disable the TIM Capture/Compare 1 interrupt */
group-onsemi 0:098463de4c5d 732 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
group-onsemi 0:098463de4c5d 733 }
group-onsemi 0:098463de4c5d 734 break;
group-onsemi 0:098463de4c5d 735
group-onsemi 0:098463de4c5d 736 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 737 {
group-onsemi 0:098463de4c5d 738 /* Disable the TIM Capture/Compare 2 interrupt */
group-onsemi 0:098463de4c5d 739 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
group-onsemi 0:098463de4c5d 740 }
group-onsemi 0:098463de4c5d 741 break;
group-onsemi 0:098463de4c5d 742
group-onsemi 0:098463de4c5d 743 case TIM_CHANNEL_3:
group-onsemi 0:098463de4c5d 744 {
group-onsemi 0:098463de4c5d 745 /* Disable the TIM Capture/Compare 3 interrupt */
group-onsemi 0:098463de4c5d 746 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
group-onsemi 0:098463de4c5d 747 }
group-onsemi 0:098463de4c5d 748 break;
group-onsemi 0:098463de4c5d 749
group-onsemi 0:098463de4c5d 750 case TIM_CHANNEL_4:
group-onsemi 0:098463de4c5d 751 {
group-onsemi 0:098463de4c5d 752 /* Disable the TIM Capture/Compare 4 interrupt */
group-onsemi 0:098463de4c5d 753 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
group-onsemi 0:098463de4c5d 754 }
group-onsemi 0:098463de4c5d 755 break;
group-onsemi 0:098463de4c5d 756
group-onsemi 0:098463de4c5d 757 default:
group-onsemi 0:098463de4c5d 758 break;
group-onsemi 0:098463de4c5d 759 }
group-onsemi 0:098463de4c5d 760
group-onsemi 0:098463de4c5d 761 /* Disable the Output compare channel */
group-onsemi 0:098463de4c5d 762 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 763
group-onsemi 0:098463de4c5d 764 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
group-onsemi 0:098463de4c5d 765 {
group-onsemi 0:098463de4c5d 766 /* Disable the Main Output */
group-onsemi 0:098463de4c5d 767 __HAL_TIM_MOE_DISABLE(htim);
group-onsemi 0:098463de4c5d 768 }
group-onsemi 0:098463de4c5d 769
group-onsemi 0:098463de4c5d 770 /* Disable the Peripheral */
group-onsemi 0:098463de4c5d 771 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 772
group-onsemi 0:098463de4c5d 773 /* Return function status */
group-onsemi 0:098463de4c5d 774 return HAL_OK;
group-onsemi 0:098463de4c5d 775 }
group-onsemi 0:098463de4c5d 776
group-onsemi 0:098463de4c5d 777 /**
group-onsemi 0:098463de4c5d 778 * @brief Starts the TIM Output Compare signal generation in DMA mode.
group-onsemi 0:098463de4c5d 779 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 780 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 781 * @param Channel: TIM Channel to be enabled.
group-onsemi 0:098463de4c5d 782 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 783 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 784 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 785 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 786 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 787 * @param pData: The source Buffer address.
group-onsemi 0:098463de4c5d 788 * @param Length: The length of data to be transferred from memory to TIM peripheral
group-onsemi 0:098463de4c5d 789 * @retval HAL status
group-onsemi 0:098463de4c5d 790 */
group-onsemi 0:098463de4c5d 791 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
group-onsemi 0:098463de4c5d 792 {
group-onsemi 0:098463de4c5d 793 /* Check the parameters */
group-onsemi 0:098463de4c5d 794 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
group-onsemi 0:098463de4c5d 795
group-onsemi 0:098463de4c5d 796 if((htim->State == HAL_TIM_STATE_BUSY))
group-onsemi 0:098463de4c5d 797 {
group-onsemi 0:098463de4c5d 798 return HAL_BUSY;
group-onsemi 0:098463de4c5d 799 }
group-onsemi 0:098463de4c5d 800 else if((htim->State == HAL_TIM_STATE_READY))
group-onsemi 0:098463de4c5d 801 {
group-onsemi 0:098463de4c5d 802 if(((uint32_t)pData == 0 ) && (Length > 0))
group-onsemi 0:098463de4c5d 803 {
group-onsemi 0:098463de4c5d 804 return HAL_ERROR;
group-onsemi 0:098463de4c5d 805 }
group-onsemi 0:098463de4c5d 806 else
group-onsemi 0:098463de4c5d 807 {
group-onsemi 0:098463de4c5d 808 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 809 }
group-onsemi 0:098463de4c5d 810 }
group-onsemi 0:098463de4c5d 811 switch (Channel)
group-onsemi 0:098463de4c5d 812 {
group-onsemi 0:098463de4c5d 813 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 814 {
group-onsemi 0:098463de4c5d 815 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 816 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
group-onsemi 0:098463de4c5d 817
group-onsemi 0:098463de4c5d 818 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 819 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 820
group-onsemi 0:098463de4c5d 821 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 822 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
group-onsemi 0:098463de4c5d 823
group-onsemi 0:098463de4c5d 824 /* Enable the TIM Capture/Compare 1 DMA request */
group-onsemi 0:098463de4c5d 825 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
group-onsemi 0:098463de4c5d 826 }
group-onsemi 0:098463de4c5d 827 break;
group-onsemi 0:098463de4c5d 828
group-onsemi 0:098463de4c5d 829 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 830 {
group-onsemi 0:098463de4c5d 831 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 832 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
group-onsemi 0:098463de4c5d 833
group-onsemi 0:098463de4c5d 834 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 835 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 836
group-onsemi 0:098463de4c5d 837 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 838 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
group-onsemi 0:098463de4c5d 839
group-onsemi 0:098463de4c5d 840 /* Enable the TIM Capture/Compare 2 DMA request */
group-onsemi 0:098463de4c5d 841 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
group-onsemi 0:098463de4c5d 842 }
group-onsemi 0:098463de4c5d 843 break;
group-onsemi 0:098463de4c5d 844
group-onsemi 0:098463de4c5d 845 case TIM_CHANNEL_3:
group-onsemi 0:098463de4c5d 846 {
group-onsemi 0:098463de4c5d 847 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 848 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
group-onsemi 0:098463de4c5d 849
group-onsemi 0:098463de4c5d 850 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 851 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 852
group-onsemi 0:098463de4c5d 853 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 854 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
group-onsemi 0:098463de4c5d 855
group-onsemi 0:098463de4c5d 856 /* Enable the TIM Capture/Compare 3 DMA request */
group-onsemi 0:098463de4c5d 857 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
group-onsemi 0:098463de4c5d 858 }
group-onsemi 0:098463de4c5d 859 break;
group-onsemi 0:098463de4c5d 860
group-onsemi 0:098463de4c5d 861 case TIM_CHANNEL_4:
group-onsemi 0:098463de4c5d 862 {
group-onsemi 0:098463de4c5d 863 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 864 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
group-onsemi 0:098463de4c5d 865
group-onsemi 0:098463de4c5d 866 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 867 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 868
group-onsemi 0:098463de4c5d 869 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 870 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
group-onsemi 0:098463de4c5d 871
group-onsemi 0:098463de4c5d 872 /* Enable the TIM Capture/Compare 4 DMA request */
group-onsemi 0:098463de4c5d 873 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
group-onsemi 0:098463de4c5d 874 }
group-onsemi 0:098463de4c5d 875 break;
group-onsemi 0:098463de4c5d 876
group-onsemi 0:098463de4c5d 877 default:
group-onsemi 0:098463de4c5d 878 break;
group-onsemi 0:098463de4c5d 879 }
group-onsemi 0:098463de4c5d 880
group-onsemi 0:098463de4c5d 881 /* Enable the Output compare channel */
group-onsemi 0:098463de4c5d 882 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 883
group-onsemi 0:098463de4c5d 884 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
group-onsemi 0:098463de4c5d 885 {
group-onsemi 0:098463de4c5d 886 /* Enable the main output */
group-onsemi 0:098463de4c5d 887 __HAL_TIM_MOE_ENABLE(htim);
group-onsemi 0:098463de4c5d 888 }
group-onsemi 0:098463de4c5d 889
group-onsemi 0:098463de4c5d 890 /* Enable the Peripheral */
group-onsemi 0:098463de4c5d 891 __HAL_TIM_ENABLE(htim);
group-onsemi 0:098463de4c5d 892
group-onsemi 0:098463de4c5d 893 /* Return function status */
group-onsemi 0:098463de4c5d 894 return HAL_OK;
group-onsemi 0:098463de4c5d 895 }
group-onsemi 0:098463de4c5d 896
group-onsemi 0:098463de4c5d 897 /**
group-onsemi 0:098463de4c5d 898 * @brief Stops the TIM Output Compare signal generation in DMA mode.
group-onsemi 0:098463de4c5d 899 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 900 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 901 * @param Channel: TIM Channel to be disabled.
group-onsemi 0:098463de4c5d 902 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 903 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 904 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 905 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 906 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 907 * @retval HAL status
group-onsemi 0:098463de4c5d 908 */
group-onsemi 0:098463de4c5d 909 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 910 {
group-onsemi 0:098463de4c5d 911 /* Check the parameters */
group-onsemi 0:098463de4c5d 912 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
group-onsemi 0:098463de4c5d 913
group-onsemi 0:098463de4c5d 914 switch (Channel)
group-onsemi 0:098463de4c5d 915 {
group-onsemi 0:098463de4c5d 916 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 917 {
group-onsemi 0:098463de4c5d 918 /* Disable the TIM Capture/Compare 1 DMA request */
group-onsemi 0:098463de4c5d 919 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
group-onsemi 0:098463de4c5d 920 }
group-onsemi 0:098463de4c5d 921 break;
group-onsemi 0:098463de4c5d 922
group-onsemi 0:098463de4c5d 923 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 924 {
group-onsemi 0:098463de4c5d 925 /* Disable the TIM Capture/Compare 2 DMA request */
group-onsemi 0:098463de4c5d 926 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
group-onsemi 0:098463de4c5d 927 }
group-onsemi 0:098463de4c5d 928 break;
group-onsemi 0:098463de4c5d 929
group-onsemi 0:098463de4c5d 930 case TIM_CHANNEL_3:
group-onsemi 0:098463de4c5d 931 {
group-onsemi 0:098463de4c5d 932 /* Disable the TIM Capture/Compare 3 DMA request */
group-onsemi 0:098463de4c5d 933 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
group-onsemi 0:098463de4c5d 934 }
group-onsemi 0:098463de4c5d 935 break;
group-onsemi 0:098463de4c5d 936
group-onsemi 0:098463de4c5d 937 case TIM_CHANNEL_4:
group-onsemi 0:098463de4c5d 938 {
group-onsemi 0:098463de4c5d 939 /* Disable the TIM Capture/Compare 4 interrupt */
group-onsemi 0:098463de4c5d 940 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
group-onsemi 0:098463de4c5d 941 }
group-onsemi 0:098463de4c5d 942 break;
group-onsemi 0:098463de4c5d 943
group-onsemi 0:098463de4c5d 944 default:
group-onsemi 0:098463de4c5d 945 break;
group-onsemi 0:098463de4c5d 946 }
group-onsemi 0:098463de4c5d 947
group-onsemi 0:098463de4c5d 948 /* Disable the Output compare channel */
group-onsemi 0:098463de4c5d 949 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 950
group-onsemi 0:098463de4c5d 951 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
group-onsemi 0:098463de4c5d 952 {
group-onsemi 0:098463de4c5d 953 /* Disable the Main Output */
group-onsemi 0:098463de4c5d 954 __HAL_TIM_MOE_DISABLE(htim);
group-onsemi 0:098463de4c5d 955 }
group-onsemi 0:098463de4c5d 956
group-onsemi 0:098463de4c5d 957 /* Disable the Peripheral */
group-onsemi 0:098463de4c5d 958 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 959
group-onsemi 0:098463de4c5d 960 /* Change the htim state */
group-onsemi 0:098463de4c5d 961 htim->State = HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 962
group-onsemi 0:098463de4c5d 963 /* Return function status */
group-onsemi 0:098463de4c5d 964 return HAL_OK;
group-onsemi 0:098463de4c5d 965 }
group-onsemi 0:098463de4c5d 966
group-onsemi 0:098463de4c5d 967 /**
group-onsemi 0:098463de4c5d 968 * @}
group-onsemi 0:098463de4c5d 969 */
group-onsemi 0:098463de4c5d 970
group-onsemi 0:098463de4c5d 971 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
group-onsemi 0:098463de4c5d 972 * @brief Time PWM functions
group-onsemi 0:098463de4c5d 973 *
group-onsemi 0:098463de4c5d 974 @verbatim
group-onsemi 0:098463de4c5d 975 ==============================================================================
group-onsemi 0:098463de4c5d 976 ##### Time PWM functions #####
group-onsemi 0:098463de4c5d 977 ==============================================================================
group-onsemi 0:098463de4c5d 978 [..]
group-onsemi 0:098463de4c5d 979 This section provides functions allowing to:
group-onsemi 0:098463de4c5d 980 (+) Initialize and configure the TIM OPWM.
group-onsemi 0:098463de4c5d 981 (+) De-initialize the TIM PWM.
group-onsemi 0:098463de4c5d 982 (+) Start the Time PWM.
group-onsemi 0:098463de4c5d 983 (+) Stop the Time PWM.
group-onsemi 0:098463de4c5d 984 (+) Start the Time PWM and enable interrupt.
group-onsemi 0:098463de4c5d 985 (+) Stop the Time PWM and disable interrupt.
group-onsemi 0:098463de4c5d 986 (+) Start the Time PWM and enable DMA transfer.
group-onsemi 0:098463de4c5d 987 (+) Stop the Time PWM and disable DMA transfer.
group-onsemi 0:098463de4c5d 988
group-onsemi 0:098463de4c5d 989 @endverbatim
group-onsemi 0:098463de4c5d 990 * @{
group-onsemi 0:098463de4c5d 991 */
group-onsemi 0:098463de4c5d 992 /**
group-onsemi 0:098463de4c5d 993 * @brief Initializes the TIM PWM Time Base according to the specified
group-onsemi 0:098463de4c5d 994 * parameters in the TIM_HandleTypeDef and create the associated handle.
group-onsemi 0:098463de4c5d 995 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 996 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 997 * @retval HAL status
group-onsemi 0:098463de4c5d 998 */
group-onsemi 0:098463de4c5d 999 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 1000 {
group-onsemi 0:098463de4c5d 1001 /* Check the TIM handle allocation */
group-onsemi 0:098463de4c5d 1002 if(htim == NULL)
group-onsemi 0:098463de4c5d 1003 {
group-onsemi 0:098463de4c5d 1004 return HAL_ERROR;
group-onsemi 0:098463de4c5d 1005 }
group-onsemi 0:098463de4c5d 1006
group-onsemi 0:098463de4c5d 1007 /* Check the parameters */
group-onsemi 0:098463de4c5d 1008 assert_param(IS_TIM_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 1009 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
group-onsemi 0:098463de4c5d 1010 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
group-onsemi 0:098463de4c5d 1011
group-onsemi 0:098463de4c5d 1012 if(htim->State == HAL_TIM_STATE_RESET)
group-onsemi 0:098463de4c5d 1013 {
group-onsemi 0:098463de4c5d 1014 /* Allocate lock resource and initialize it */
group-onsemi 0:098463de4c5d 1015 htim->Lock = HAL_UNLOCKED;
group-onsemi 0:098463de4c5d 1016 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
group-onsemi 0:098463de4c5d 1017 HAL_TIM_PWM_MspInit(htim);
group-onsemi 0:098463de4c5d 1018 }
group-onsemi 0:098463de4c5d 1019
group-onsemi 0:098463de4c5d 1020 /* Set the TIM state */
group-onsemi 0:098463de4c5d 1021 htim->State= HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 1022
group-onsemi 0:098463de4c5d 1023 /* Init the base time for the PWM */
group-onsemi 0:098463de4c5d 1024 TIM_Base_SetConfig(htim->Instance, &htim->Init);
group-onsemi 0:098463de4c5d 1025
group-onsemi 0:098463de4c5d 1026 /* Initialize the TIM state*/
group-onsemi 0:098463de4c5d 1027 htim->State= HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 1028
group-onsemi 0:098463de4c5d 1029 return HAL_OK;
group-onsemi 0:098463de4c5d 1030 }
group-onsemi 0:098463de4c5d 1031
group-onsemi 0:098463de4c5d 1032 /**
group-onsemi 0:098463de4c5d 1033 * @brief DeInitializes the TIM peripheral
group-onsemi 0:098463de4c5d 1034 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1035 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1036 * @retval HAL status
group-onsemi 0:098463de4c5d 1037 */
group-onsemi 0:098463de4c5d 1038 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 1039 {
group-onsemi 0:098463de4c5d 1040 /* Check the parameters */
group-onsemi 0:098463de4c5d 1041 assert_param(IS_TIM_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 1042
group-onsemi 0:098463de4c5d 1043 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 1044
group-onsemi 0:098463de4c5d 1045 /* Disable the TIM Peripheral Clock */
group-onsemi 0:098463de4c5d 1046 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 1047
group-onsemi 0:098463de4c5d 1048 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
group-onsemi 0:098463de4c5d 1049 HAL_TIM_PWM_MspDeInit(htim);
group-onsemi 0:098463de4c5d 1050
group-onsemi 0:098463de4c5d 1051 /* Change TIM state */
group-onsemi 0:098463de4c5d 1052 htim->State = HAL_TIM_STATE_RESET;
group-onsemi 0:098463de4c5d 1053
group-onsemi 0:098463de4c5d 1054 /* Release Lock */
group-onsemi 0:098463de4c5d 1055 __HAL_UNLOCK(htim);
group-onsemi 0:098463de4c5d 1056
group-onsemi 0:098463de4c5d 1057 return HAL_OK;
group-onsemi 0:098463de4c5d 1058 }
group-onsemi 0:098463de4c5d 1059
group-onsemi 0:098463de4c5d 1060 /**
group-onsemi 0:098463de4c5d 1061 * @brief Initializes the TIM PWM MSP.
group-onsemi 0:098463de4c5d 1062 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1063 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1064 * @retval None
group-onsemi 0:098463de4c5d 1065 */
group-onsemi 0:098463de4c5d 1066 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 1067 {
group-onsemi 0:098463de4c5d 1068 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 1069 UNUSED(htim);
group-onsemi 0:098463de4c5d 1070
group-onsemi 0:098463de4c5d 1071 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 1072 the HAL_TIM_PWM_MspInit could be implemented in the user file
group-onsemi 0:098463de4c5d 1073 */
group-onsemi 0:098463de4c5d 1074 }
group-onsemi 0:098463de4c5d 1075
group-onsemi 0:098463de4c5d 1076 /**
group-onsemi 0:098463de4c5d 1077 * @brief DeInitializes TIM PWM MSP.
group-onsemi 0:098463de4c5d 1078 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1079 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1080 * @retval None
group-onsemi 0:098463de4c5d 1081 */
group-onsemi 0:098463de4c5d 1082 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 1083 {
group-onsemi 0:098463de4c5d 1084 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 1085 UNUSED(htim);
group-onsemi 0:098463de4c5d 1086
group-onsemi 0:098463de4c5d 1087 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 1088 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
group-onsemi 0:098463de4c5d 1089 */
group-onsemi 0:098463de4c5d 1090 }
group-onsemi 0:098463de4c5d 1091
group-onsemi 0:098463de4c5d 1092 /**
group-onsemi 0:098463de4c5d 1093 * @brief Starts the PWM signal generation.
group-onsemi 0:098463de4c5d 1094 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1095 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1096 * @param Channel: TIM Channels to be enabled.
group-onsemi 0:098463de4c5d 1097 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 1098 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 1099 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 1100 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 1101 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 1102 * @retval HAL status
group-onsemi 0:098463de4c5d 1103 */
group-onsemi 0:098463de4c5d 1104 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 1105 {
group-onsemi 0:098463de4c5d 1106 /* Check the parameters */
group-onsemi 0:098463de4c5d 1107 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
group-onsemi 0:098463de4c5d 1108
group-onsemi 0:098463de4c5d 1109 /* Enable the Capture compare channel */
group-onsemi 0:098463de4c5d 1110 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 1111
group-onsemi 0:098463de4c5d 1112 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
group-onsemi 0:098463de4c5d 1113 {
group-onsemi 0:098463de4c5d 1114 /* Enable the main output */
group-onsemi 0:098463de4c5d 1115 __HAL_TIM_MOE_ENABLE(htim);
group-onsemi 0:098463de4c5d 1116 }
group-onsemi 0:098463de4c5d 1117
group-onsemi 0:098463de4c5d 1118 /* Enable the Peripheral */
group-onsemi 0:098463de4c5d 1119 __HAL_TIM_ENABLE(htim);
group-onsemi 0:098463de4c5d 1120
group-onsemi 0:098463de4c5d 1121 /* Return function status */
group-onsemi 0:098463de4c5d 1122 return HAL_OK;
group-onsemi 0:098463de4c5d 1123 }
group-onsemi 0:098463de4c5d 1124
group-onsemi 0:098463de4c5d 1125 /**
group-onsemi 0:098463de4c5d 1126 * @brief Stops the PWM signal generation.
group-onsemi 0:098463de4c5d 1127 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1128 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1129 * @param Channel: TIM Channels to be disabled.
group-onsemi 0:098463de4c5d 1130 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 1131 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 1132 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 1133 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 1134 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 1135 * @retval HAL status
group-onsemi 0:098463de4c5d 1136 */
group-onsemi 0:098463de4c5d 1137 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 1138 {
group-onsemi 0:098463de4c5d 1139 /* Check the parameters */
group-onsemi 0:098463de4c5d 1140 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
group-onsemi 0:098463de4c5d 1141
group-onsemi 0:098463de4c5d 1142 /* Disable the Capture compare channel */
group-onsemi 0:098463de4c5d 1143 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 1144
group-onsemi 0:098463de4c5d 1145 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
group-onsemi 0:098463de4c5d 1146 {
group-onsemi 0:098463de4c5d 1147 /* Disable the Main Output */
group-onsemi 0:098463de4c5d 1148 __HAL_TIM_MOE_DISABLE(htim);
group-onsemi 0:098463de4c5d 1149 }
group-onsemi 0:098463de4c5d 1150
group-onsemi 0:098463de4c5d 1151 /* Disable the Peripheral */
group-onsemi 0:098463de4c5d 1152 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 1153
group-onsemi 0:098463de4c5d 1154 /* Change the htim state */
group-onsemi 0:098463de4c5d 1155 htim->State = HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 1156
group-onsemi 0:098463de4c5d 1157 /* Return function status */
group-onsemi 0:098463de4c5d 1158 return HAL_OK;
group-onsemi 0:098463de4c5d 1159 }
group-onsemi 0:098463de4c5d 1160
group-onsemi 0:098463de4c5d 1161 /**
group-onsemi 0:098463de4c5d 1162 * @brief Starts the PWM signal generation in interrupt mode.
group-onsemi 0:098463de4c5d 1163 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1164 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1165 * @param Channel: TIM Channel to be enabled.
group-onsemi 0:098463de4c5d 1166 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 1167 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 1168 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 1169 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 1170 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 1171 * @retval HAL status
group-onsemi 0:098463de4c5d 1172 */
group-onsemi 0:098463de4c5d 1173 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 1174 {
group-onsemi 0:098463de4c5d 1175 /* Check the parameters */
group-onsemi 0:098463de4c5d 1176 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
group-onsemi 0:098463de4c5d 1177
group-onsemi 0:098463de4c5d 1178 switch (Channel)
group-onsemi 0:098463de4c5d 1179 {
group-onsemi 0:098463de4c5d 1180 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 1181 {
group-onsemi 0:098463de4c5d 1182 /* Enable the TIM Capture/Compare 1 interrupt */
group-onsemi 0:098463de4c5d 1183 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
group-onsemi 0:098463de4c5d 1184 }
group-onsemi 0:098463de4c5d 1185 break;
group-onsemi 0:098463de4c5d 1186
group-onsemi 0:098463de4c5d 1187 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 1188 {
group-onsemi 0:098463de4c5d 1189 /* Enable the TIM Capture/Compare 2 interrupt */
group-onsemi 0:098463de4c5d 1190 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
group-onsemi 0:098463de4c5d 1191 }
group-onsemi 0:098463de4c5d 1192 break;
group-onsemi 0:098463de4c5d 1193
group-onsemi 0:098463de4c5d 1194 case TIM_CHANNEL_3:
group-onsemi 0:098463de4c5d 1195 {
group-onsemi 0:098463de4c5d 1196 /* Enable the TIM Capture/Compare 3 interrupt */
group-onsemi 0:098463de4c5d 1197 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
group-onsemi 0:098463de4c5d 1198 }
group-onsemi 0:098463de4c5d 1199 break;
group-onsemi 0:098463de4c5d 1200
group-onsemi 0:098463de4c5d 1201 case TIM_CHANNEL_4:
group-onsemi 0:098463de4c5d 1202 {
group-onsemi 0:098463de4c5d 1203 /* Enable the TIM Capture/Compare 4 interrupt */
group-onsemi 0:098463de4c5d 1204 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
group-onsemi 0:098463de4c5d 1205 }
group-onsemi 0:098463de4c5d 1206 break;
group-onsemi 0:098463de4c5d 1207
group-onsemi 0:098463de4c5d 1208 default:
group-onsemi 0:098463de4c5d 1209 break;
group-onsemi 0:098463de4c5d 1210 }
group-onsemi 0:098463de4c5d 1211
group-onsemi 0:098463de4c5d 1212 /* Enable the Capture compare channel */
group-onsemi 0:098463de4c5d 1213 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 1214
group-onsemi 0:098463de4c5d 1215 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
group-onsemi 0:098463de4c5d 1216 {
group-onsemi 0:098463de4c5d 1217 /* Enable the main output */
group-onsemi 0:098463de4c5d 1218 __HAL_TIM_MOE_ENABLE(htim);
group-onsemi 0:098463de4c5d 1219 }
group-onsemi 0:098463de4c5d 1220
group-onsemi 0:098463de4c5d 1221 /* Enable the Peripheral */
group-onsemi 0:098463de4c5d 1222 __HAL_TIM_ENABLE(htim);
group-onsemi 0:098463de4c5d 1223
group-onsemi 0:098463de4c5d 1224 /* Return function status */
group-onsemi 0:098463de4c5d 1225 return HAL_OK;
group-onsemi 0:098463de4c5d 1226 }
group-onsemi 0:098463de4c5d 1227
group-onsemi 0:098463de4c5d 1228 /**
group-onsemi 0:098463de4c5d 1229 * @brief Stops the PWM signal generation in interrupt mode.
group-onsemi 0:098463de4c5d 1230 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1231 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1232 * @param Channel: TIM Channels to be disabled.
group-onsemi 0:098463de4c5d 1233 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 1234 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 1235 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 1236 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 1237 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 1238 * @retval HAL status
group-onsemi 0:098463de4c5d 1239 */
group-onsemi 0:098463de4c5d 1240 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 1241 {
group-onsemi 0:098463de4c5d 1242 /* Check the parameters */
group-onsemi 0:098463de4c5d 1243 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
group-onsemi 0:098463de4c5d 1244
group-onsemi 0:098463de4c5d 1245 switch (Channel)
group-onsemi 0:098463de4c5d 1246 {
group-onsemi 0:098463de4c5d 1247 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 1248 {
group-onsemi 0:098463de4c5d 1249 /* Disable the TIM Capture/Compare 1 interrupt */
group-onsemi 0:098463de4c5d 1250 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
group-onsemi 0:098463de4c5d 1251 }
group-onsemi 0:098463de4c5d 1252 break;
group-onsemi 0:098463de4c5d 1253
group-onsemi 0:098463de4c5d 1254 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 1255 {
group-onsemi 0:098463de4c5d 1256 /* Disable the TIM Capture/Compare 2 interrupt */
group-onsemi 0:098463de4c5d 1257 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
group-onsemi 0:098463de4c5d 1258 }
group-onsemi 0:098463de4c5d 1259 break;
group-onsemi 0:098463de4c5d 1260
group-onsemi 0:098463de4c5d 1261 case TIM_CHANNEL_3:
group-onsemi 0:098463de4c5d 1262 {
group-onsemi 0:098463de4c5d 1263 /* Disable the TIM Capture/Compare 3 interrupt */
group-onsemi 0:098463de4c5d 1264 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
group-onsemi 0:098463de4c5d 1265 }
group-onsemi 0:098463de4c5d 1266 break;
group-onsemi 0:098463de4c5d 1267
group-onsemi 0:098463de4c5d 1268 case TIM_CHANNEL_4:
group-onsemi 0:098463de4c5d 1269 {
group-onsemi 0:098463de4c5d 1270 /* Disable the TIM Capture/Compare 4 interrupt */
group-onsemi 0:098463de4c5d 1271 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
group-onsemi 0:098463de4c5d 1272 }
group-onsemi 0:098463de4c5d 1273 break;
group-onsemi 0:098463de4c5d 1274
group-onsemi 0:098463de4c5d 1275 default:
group-onsemi 0:098463de4c5d 1276 break;
group-onsemi 0:098463de4c5d 1277 }
group-onsemi 0:098463de4c5d 1278
group-onsemi 0:098463de4c5d 1279 /* Disable the Capture compare channel */
group-onsemi 0:098463de4c5d 1280 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 1281
group-onsemi 0:098463de4c5d 1282 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
group-onsemi 0:098463de4c5d 1283 {
group-onsemi 0:098463de4c5d 1284 /* Disable the Main Output */
group-onsemi 0:098463de4c5d 1285 __HAL_TIM_MOE_DISABLE(htim);
group-onsemi 0:098463de4c5d 1286 }
group-onsemi 0:098463de4c5d 1287
group-onsemi 0:098463de4c5d 1288 /* Disable the Peripheral */
group-onsemi 0:098463de4c5d 1289 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 1290
group-onsemi 0:098463de4c5d 1291 /* Return function status */
group-onsemi 0:098463de4c5d 1292 return HAL_OK;
group-onsemi 0:098463de4c5d 1293 }
group-onsemi 0:098463de4c5d 1294
group-onsemi 0:098463de4c5d 1295 /**
group-onsemi 0:098463de4c5d 1296 * @brief Starts the TIM PWM signal generation in DMA mode.
group-onsemi 0:098463de4c5d 1297 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1298 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1299 * @param Channel: TIM Channels to be enabled.
group-onsemi 0:098463de4c5d 1300 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 1301 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 1302 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 1303 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 1304 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 1305 * @param pData: The source Buffer address.
group-onsemi 0:098463de4c5d 1306 * @param Length: The length of data to be transferred from memory to TIM peripheral
group-onsemi 0:098463de4c5d 1307 * @retval HAL status
group-onsemi 0:098463de4c5d 1308 */
group-onsemi 0:098463de4c5d 1309 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
group-onsemi 0:098463de4c5d 1310 {
group-onsemi 0:098463de4c5d 1311 /* Check the parameters */
group-onsemi 0:098463de4c5d 1312 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
group-onsemi 0:098463de4c5d 1313
group-onsemi 0:098463de4c5d 1314 if((htim->State == HAL_TIM_STATE_BUSY))
group-onsemi 0:098463de4c5d 1315 {
group-onsemi 0:098463de4c5d 1316 return HAL_BUSY;
group-onsemi 0:098463de4c5d 1317 }
group-onsemi 0:098463de4c5d 1318 else if((htim->State == HAL_TIM_STATE_READY))
group-onsemi 0:098463de4c5d 1319 {
group-onsemi 0:098463de4c5d 1320 if(((uint32_t)pData == 0 ) && (Length > 0))
group-onsemi 0:098463de4c5d 1321 {
group-onsemi 0:098463de4c5d 1322 return HAL_ERROR;
group-onsemi 0:098463de4c5d 1323 }
group-onsemi 0:098463de4c5d 1324 else
group-onsemi 0:098463de4c5d 1325 {
group-onsemi 0:098463de4c5d 1326 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 1327 }
group-onsemi 0:098463de4c5d 1328 }
group-onsemi 0:098463de4c5d 1329 switch (Channel)
group-onsemi 0:098463de4c5d 1330 {
group-onsemi 0:098463de4c5d 1331 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 1332 {
group-onsemi 0:098463de4c5d 1333 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 1334 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
group-onsemi 0:098463de4c5d 1335
group-onsemi 0:098463de4c5d 1336 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 1337 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 1338
group-onsemi 0:098463de4c5d 1339 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 1340 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
group-onsemi 0:098463de4c5d 1341
group-onsemi 0:098463de4c5d 1342 /* Enable the TIM Capture/Compare 1 DMA request */
group-onsemi 0:098463de4c5d 1343 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
group-onsemi 0:098463de4c5d 1344 }
group-onsemi 0:098463de4c5d 1345 break;
group-onsemi 0:098463de4c5d 1346
group-onsemi 0:098463de4c5d 1347 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 1348 {
group-onsemi 0:098463de4c5d 1349 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 1350 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
group-onsemi 0:098463de4c5d 1351
group-onsemi 0:098463de4c5d 1352 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 1353 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 1354
group-onsemi 0:098463de4c5d 1355 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 1356 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
group-onsemi 0:098463de4c5d 1357
group-onsemi 0:098463de4c5d 1358 /* Enable the TIM Capture/Compare 2 DMA request */
group-onsemi 0:098463de4c5d 1359 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
group-onsemi 0:098463de4c5d 1360 }
group-onsemi 0:098463de4c5d 1361 break;
group-onsemi 0:098463de4c5d 1362
group-onsemi 0:098463de4c5d 1363 case TIM_CHANNEL_3:
group-onsemi 0:098463de4c5d 1364 {
group-onsemi 0:098463de4c5d 1365 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 1366 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
group-onsemi 0:098463de4c5d 1367
group-onsemi 0:098463de4c5d 1368 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 1369 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 1370
group-onsemi 0:098463de4c5d 1371 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 1372 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
group-onsemi 0:098463de4c5d 1373
group-onsemi 0:098463de4c5d 1374 /* Enable the TIM Output Capture/Compare 3 request */
group-onsemi 0:098463de4c5d 1375 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
group-onsemi 0:098463de4c5d 1376 }
group-onsemi 0:098463de4c5d 1377 break;
group-onsemi 0:098463de4c5d 1378
group-onsemi 0:098463de4c5d 1379 case TIM_CHANNEL_4:
group-onsemi 0:098463de4c5d 1380 {
group-onsemi 0:098463de4c5d 1381 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 1382 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
group-onsemi 0:098463de4c5d 1383
group-onsemi 0:098463de4c5d 1384 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 1385 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 1386
group-onsemi 0:098463de4c5d 1387 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 1388 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
group-onsemi 0:098463de4c5d 1389
group-onsemi 0:098463de4c5d 1390 /* Enable the TIM Capture/Compare 4 DMA request */
group-onsemi 0:098463de4c5d 1391 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
group-onsemi 0:098463de4c5d 1392 }
group-onsemi 0:098463de4c5d 1393 break;
group-onsemi 0:098463de4c5d 1394
group-onsemi 0:098463de4c5d 1395 default:
group-onsemi 0:098463de4c5d 1396 break;
group-onsemi 0:098463de4c5d 1397 }
group-onsemi 0:098463de4c5d 1398
group-onsemi 0:098463de4c5d 1399 /* Enable the Capture compare channel */
group-onsemi 0:098463de4c5d 1400 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 1401
group-onsemi 0:098463de4c5d 1402 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
group-onsemi 0:098463de4c5d 1403 {
group-onsemi 0:098463de4c5d 1404 /* Enable the main output */
group-onsemi 0:098463de4c5d 1405 __HAL_TIM_MOE_ENABLE(htim);
group-onsemi 0:098463de4c5d 1406 }
group-onsemi 0:098463de4c5d 1407
group-onsemi 0:098463de4c5d 1408 /* Enable the Peripheral */
group-onsemi 0:098463de4c5d 1409 __HAL_TIM_ENABLE(htim);
group-onsemi 0:098463de4c5d 1410
group-onsemi 0:098463de4c5d 1411 /* Return function status */
group-onsemi 0:098463de4c5d 1412 return HAL_OK;
group-onsemi 0:098463de4c5d 1413 }
group-onsemi 0:098463de4c5d 1414
group-onsemi 0:098463de4c5d 1415 /**
group-onsemi 0:098463de4c5d 1416 * @brief Stops the TIM PWM signal generation in DMA mode.
group-onsemi 0:098463de4c5d 1417 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1418 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1419 * @param Channel: TIM Channels to be disabled.
group-onsemi 0:098463de4c5d 1420 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 1421 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 1422 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 1423 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 1424 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 1425 * @retval HAL status
group-onsemi 0:098463de4c5d 1426 */
group-onsemi 0:098463de4c5d 1427 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 1428 {
group-onsemi 0:098463de4c5d 1429 /* Check the parameters */
group-onsemi 0:098463de4c5d 1430 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
group-onsemi 0:098463de4c5d 1431
group-onsemi 0:098463de4c5d 1432 switch (Channel)
group-onsemi 0:098463de4c5d 1433 {
group-onsemi 0:098463de4c5d 1434 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 1435 {
group-onsemi 0:098463de4c5d 1436 /* Disable the TIM Capture/Compare 1 DMA request */
group-onsemi 0:098463de4c5d 1437 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
group-onsemi 0:098463de4c5d 1438 }
group-onsemi 0:098463de4c5d 1439 break;
group-onsemi 0:098463de4c5d 1440
group-onsemi 0:098463de4c5d 1441 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 1442 {
group-onsemi 0:098463de4c5d 1443 /* Disable the TIM Capture/Compare 2 DMA request */
group-onsemi 0:098463de4c5d 1444 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
group-onsemi 0:098463de4c5d 1445 }
group-onsemi 0:098463de4c5d 1446 break;
group-onsemi 0:098463de4c5d 1447
group-onsemi 0:098463de4c5d 1448 case TIM_CHANNEL_3:
group-onsemi 0:098463de4c5d 1449 {
group-onsemi 0:098463de4c5d 1450 /* Disable the TIM Capture/Compare 3 DMA request */
group-onsemi 0:098463de4c5d 1451 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
group-onsemi 0:098463de4c5d 1452 }
group-onsemi 0:098463de4c5d 1453 break;
group-onsemi 0:098463de4c5d 1454
group-onsemi 0:098463de4c5d 1455 case TIM_CHANNEL_4:
group-onsemi 0:098463de4c5d 1456 {
group-onsemi 0:098463de4c5d 1457 /* Disable the TIM Capture/Compare 4 interrupt */
group-onsemi 0:098463de4c5d 1458 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
group-onsemi 0:098463de4c5d 1459 }
group-onsemi 0:098463de4c5d 1460 break;
group-onsemi 0:098463de4c5d 1461
group-onsemi 0:098463de4c5d 1462 default:
group-onsemi 0:098463de4c5d 1463 break;
group-onsemi 0:098463de4c5d 1464 }
group-onsemi 0:098463de4c5d 1465
group-onsemi 0:098463de4c5d 1466 /* Disable the Capture compare channel */
group-onsemi 0:098463de4c5d 1467 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 1468
group-onsemi 0:098463de4c5d 1469 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
group-onsemi 0:098463de4c5d 1470 {
group-onsemi 0:098463de4c5d 1471 /* Disable the Main Output */
group-onsemi 0:098463de4c5d 1472 __HAL_TIM_MOE_DISABLE(htim);
group-onsemi 0:098463de4c5d 1473 }
group-onsemi 0:098463de4c5d 1474
group-onsemi 0:098463de4c5d 1475 /* Disable the Peripheral */
group-onsemi 0:098463de4c5d 1476 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 1477
group-onsemi 0:098463de4c5d 1478 /* Change the htim state */
group-onsemi 0:098463de4c5d 1479 htim->State = HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 1480
group-onsemi 0:098463de4c5d 1481 /* Return function status */
group-onsemi 0:098463de4c5d 1482 return HAL_OK;
group-onsemi 0:098463de4c5d 1483 }
group-onsemi 0:098463de4c5d 1484
group-onsemi 0:098463de4c5d 1485 /**
group-onsemi 0:098463de4c5d 1486 * @}
group-onsemi 0:098463de4c5d 1487 */
group-onsemi 0:098463de4c5d 1488
group-onsemi 0:098463de4c5d 1489 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
group-onsemi 0:098463de4c5d 1490 * @brief Time Input Capture functions
group-onsemi 0:098463de4c5d 1491 *
group-onsemi 0:098463de4c5d 1492 @verbatim
group-onsemi 0:098463de4c5d 1493 ==============================================================================
group-onsemi 0:098463de4c5d 1494 ##### Time Input Capture functions #####
group-onsemi 0:098463de4c5d 1495 ==============================================================================
group-onsemi 0:098463de4c5d 1496 [..]
group-onsemi 0:098463de4c5d 1497 This section provides functions allowing to:
group-onsemi 0:098463de4c5d 1498 (+) Initialize and configure the TIM Input Capture.
group-onsemi 0:098463de4c5d 1499 (+) De-initialize the TIM Input Capture.
group-onsemi 0:098463de4c5d 1500 (+) Start the Time Input Capture.
group-onsemi 0:098463de4c5d 1501 (+) Stop the Time Input Capture.
group-onsemi 0:098463de4c5d 1502 (+) Start the Time Input Capture and enable interrupt.
group-onsemi 0:098463de4c5d 1503 (+) Stop the Time Input Capture and disable interrupt.
group-onsemi 0:098463de4c5d 1504 (+) Start the Time Input Capture and enable DMA transfer.
group-onsemi 0:098463de4c5d 1505 (+) Stop the Time Input Capture and disable DMA transfer.
group-onsemi 0:098463de4c5d 1506
group-onsemi 0:098463de4c5d 1507 @endverbatim
group-onsemi 0:098463de4c5d 1508 * @{
group-onsemi 0:098463de4c5d 1509 */
group-onsemi 0:098463de4c5d 1510 /**
group-onsemi 0:098463de4c5d 1511 * @brief Initializes the TIM Input Capture Time base according to the specified
group-onsemi 0:098463de4c5d 1512 * parameters in the TIM_HandleTypeDef and create the associated handle.
group-onsemi 0:098463de4c5d 1513 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1514 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1515 * @retval HAL status
group-onsemi 0:098463de4c5d 1516 */
group-onsemi 0:098463de4c5d 1517 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 1518 {
group-onsemi 0:098463de4c5d 1519 /* Check the TIM handle allocation */
group-onsemi 0:098463de4c5d 1520 if(htim == NULL)
group-onsemi 0:098463de4c5d 1521 {
group-onsemi 0:098463de4c5d 1522 return HAL_ERROR;
group-onsemi 0:098463de4c5d 1523 }
group-onsemi 0:098463de4c5d 1524
group-onsemi 0:098463de4c5d 1525 /* Check the parameters */
group-onsemi 0:098463de4c5d 1526 assert_param(IS_TIM_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 1527 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
group-onsemi 0:098463de4c5d 1528 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
group-onsemi 0:098463de4c5d 1529
group-onsemi 0:098463de4c5d 1530 if(htim->State == HAL_TIM_STATE_RESET)
group-onsemi 0:098463de4c5d 1531 {
group-onsemi 0:098463de4c5d 1532 /* Allocate lock resource and initialize it */
group-onsemi 0:098463de4c5d 1533 htim->Lock = HAL_UNLOCKED;
group-onsemi 0:098463de4c5d 1534 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
group-onsemi 0:098463de4c5d 1535 HAL_TIM_IC_MspInit(htim);
group-onsemi 0:098463de4c5d 1536 }
group-onsemi 0:098463de4c5d 1537
group-onsemi 0:098463de4c5d 1538 /* Set the TIM state */
group-onsemi 0:098463de4c5d 1539 htim->State= HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 1540
group-onsemi 0:098463de4c5d 1541 /* Init the base time for the input capture */
group-onsemi 0:098463de4c5d 1542 TIM_Base_SetConfig(htim->Instance, &htim->Init);
group-onsemi 0:098463de4c5d 1543
group-onsemi 0:098463de4c5d 1544 /* Initialize the TIM state*/
group-onsemi 0:098463de4c5d 1545 htim->State= HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 1546
group-onsemi 0:098463de4c5d 1547 return HAL_OK;
group-onsemi 0:098463de4c5d 1548 }
group-onsemi 0:098463de4c5d 1549
group-onsemi 0:098463de4c5d 1550 /**
group-onsemi 0:098463de4c5d 1551 * @brief DeInitializes the TIM peripheral
group-onsemi 0:098463de4c5d 1552 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1553 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1554 * @retval HAL status
group-onsemi 0:098463de4c5d 1555 */
group-onsemi 0:098463de4c5d 1556 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 1557 {
group-onsemi 0:098463de4c5d 1558 /* Check the parameters */
group-onsemi 0:098463de4c5d 1559 assert_param(IS_TIM_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 1560
group-onsemi 0:098463de4c5d 1561 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 1562
group-onsemi 0:098463de4c5d 1563 /* Disable the TIM Peripheral Clock */
group-onsemi 0:098463de4c5d 1564 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 1565
group-onsemi 0:098463de4c5d 1566 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
group-onsemi 0:098463de4c5d 1567 HAL_TIM_IC_MspDeInit(htim);
group-onsemi 0:098463de4c5d 1568
group-onsemi 0:098463de4c5d 1569 /* Change TIM state */
group-onsemi 0:098463de4c5d 1570 htim->State = HAL_TIM_STATE_RESET;
group-onsemi 0:098463de4c5d 1571
group-onsemi 0:098463de4c5d 1572 /* Release Lock */
group-onsemi 0:098463de4c5d 1573 __HAL_UNLOCK(htim);
group-onsemi 0:098463de4c5d 1574
group-onsemi 0:098463de4c5d 1575 return HAL_OK;
group-onsemi 0:098463de4c5d 1576 }
group-onsemi 0:098463de4c5d 1577
group-onsemi 0:098463de4c5d 1578 /**
group-onsemi 0:098463de4c5d 1579 * @brief Initializes the TIM INput Capture MSP.
group-onsemi 0:098463de4c5d 1580 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1581 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1582 * @retval None
group-onsemi 0:098463de4c5d 1583 */
group-onsemi 0:098463de4c5d 1584 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 1585 {
group-onsemi 0:098463de4c5d 1586 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 1587 UNUSED(htim);
group-onsemi 0:098463de4c5d 1588
group-onsemi 0:098463de4c5d 1589 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 1590 the HAL_TIM_IC_MspInit could be implemented in the user file
group-onsemi 0:098463de4c5d 1591 */
group-onsemi 0:098463de4c5d 1592 }
group-onsemi 0:098463de4c5d 1593
group-onsemi 0:098463de4c5d 1594 /**
group-onsemi 0:098463de4c5d 1595 * @brief DeInitializes TIM Input Capture MSP.
group-onsemi 0:098463de4c5d 1596 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1597 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1598 * @retval None
group-onsemi 0:098463de4c5d 1599 */
group-onsemi 0:098463de4c5d 1600 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 1601 {
group-onsemi 0:098463de4c5d 1602 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 1603 UNUSED(htim);
group-onsemi 0:098463de4c5d 1604
group-onsemi 0:098463de4c5d 1605 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 1606 the HAL_TIM_IC_MspDeInit could be implemented in the user file
group-onsemi 0:098463de4c5d 1607 */
group-onsemi 0:098463de4c5d 1608 }
group-onsemi 0:098463de4c5d 1609
group-onsemi 0:098463de4c5d 1610 /**
group-onsemi 0:098463de4c5d 1611 * @brief Starts the TIM Input Capture measurement.
group-onsemi 0:098463de4c5d 1612 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1613 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1614 * @param Channel: TIM Channels to be enabled.
group-onsemi 0:098463de4c5d 1615 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 1616 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 1617 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 1618 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 1619 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 1620 * @retval HAL status
group-onsemi 0:098463de4c5d 1621 */
group-onsemi 0:098463de4c5d 1622 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 1623 {
group-onsemi 0:098463de4c5d 1624 /* Check the parameters */
group-onsemi 0:098463de4c5d 1625 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
group-onsemi 0:098463de4c5d 1626
group-onsemi 0:098463de4c5d 1627 /* Enable the Input Capture channel */
group-onsemi 0:098463de4c5d 1628 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 1629
group-onsemi 0:098463de4c5d 1630 /* Enable the Peripheral */
group-onsemi 0:098463de4c5d 1631 __HAL_TIM_ENABLE(htim);
group-onsemi 0:098463de4c5d 1632
group-onsemi 0:098463de4c5d 1633 /* Return function status */
group-onsemi 0:098463de4c5d 1634 return HAL_OK;
group-onsemi 0:098463de4c5d 1635 }
group-onsemi 0:098463de4c5d 1636
group-onsemi 0:098463de4c5d 1637 /**
group-onsemi 0:098463de4c5d 1638 * @brief Stops the TIM Input Capture measurement.
group-onsemi 0:098463de4c5d 1639 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1640 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1641 * @param Channel: TIM Channels to be disabled.
group-onsemi 0:098463de4c5d 1642 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 1643 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 1644 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 1645 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 1646 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 1647 * @retval HAL status
group-onsemi 0:098463de4c5d 1648 */
group-onsemi 0:098463de4c5d 1649 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 1650 {
group-onsemi 0:098463de4c5d 1651 /* Check the parameters */
group-onsemi 0:098463de4c5d 1652 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
group-onsemi 0:098463de4c5d 1653
group-onsemi 0:098463de4c5d 1654 /* Disable the Input Capture channel */
group-onsemi 0:098463de4c5d 1655 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 1656
group-onsemi 0:098463de4c5d 1657 /* Disable the Peripheral */
group-onsemi 0:098463de4c5d 1658 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 1659
group-onsemi 0:098463de4c5d 1660 /* Return function status */
group-onsemi 0:098463de4c5d 1661 return HAL_OK;
group-onsemi 0:098463de4c5d 1662 }
group-onsemi 0:098463de4c5d 1663
group-onsemi 0:098463de4c5d 1664 /**
group-onsemi 0:098463de4c5d 1665 * @brief Starts the TIM Input Capture measurement in interrupt mode.
group-onsemi 0:098463de4c5d 1666 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1667 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1668 * @param Channel: TIM Channels to be enabled.
group-onsemi 0:098463de4c5d 1669 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 1670 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 1671 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 1672 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 1673 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 1674 * @retval HAL status
group-onsemi 0:098463de4c5d 1675 */
group-onsemi 0:098463de4c5d 1676 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 1677 {
group-onsemi 0:098463de4c5d 1678 /* Check the parameters */
group-onsemi 0:098463de4c5d 1679 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
group-onsemi 0:098463de4c5d 1680
group-onsemi 0:098463de4c5d 1681 switch (Channel)
group-onsemi 0:098463de4c5d 1682 {
group-onsemi 0:098463de4c5d 1683 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 1684 {
group-onsemi 0:098463de4c5d 1685 /* Enable the TIM Capture/Compare 1 interrupt */
group-onsemi 0:098463de4c5d 1686 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
group-onsemi 0:098463de4c5d 1687 }
group-onsemi 0:098463de4c5d 1688 break;
group-onsemi 0:098463de4c5d 1689
group-onsemi 0:098463de4c5d 1690 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 1691 {
group-onsemi 0:098463de4c5d 1692 /* Enable the TIM Capture/Compare 2 interrupt */
group-onsemi 0:098463de4c5d 1693 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
group-onsemi 0:098463de4c5d 1694 }
group-onsemi 0:098463de4c5d 1695 break;
group-onsemi 0:098463de4c5d 1696
group-onsemi 0:098463de4c5d 1697 case TIM_CHANNEL_3:
group-onsemi 0:098463de4c5d 1698 {
group-onsemi 0:098463de4c5d 1699 /* Enable the TIM Capture/Compare 3 interrupt */
group-onsemi 0:098463de4c5d 1700 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
group-onsemi 0:098463de4c5d 1701 }
group-onsemi 0:098463de4c5d 1702 break;
group-onsemi 0:098463de4c5d 1703
group-onsemi 0:098463de4c5d 1704 case TIM_CHANNEL_4:
group-onsemi 0:098463de4c5d 1705 {
group-onsemi 0:098463de4c5d 1706 /* Enable the TIM Capture/Compare 4 interrupt */
group-onsemi 0:098463de4c5d 1707 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
group-onsemi 0:098463de4c5d 1708 }
group-onsemi 0:098463de4c5d 1709 break;
group-onsemi 0:098463de4c5d 1710
group-onsemi 0:098463de4c5d 1711 default:
group-onsemi 0:098463de4c5d 1712 break;
group-onsemi 0:098463de4c5d 1713 }
group-onsemi 0:098463de4c5d 1714 /* Enable the Input Capture channel */
group-onsemi 0:098463de4c5d 1715 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 1716
group-onsemi 0:098463de4c5d 1717 /* Enable the Peripheral */
group-onsemi 0:098463de4c5d 1718 __HAL_TIM_ENABLE(htim);
group-onsemi 0:098463de4c5d 1719
group-onsemi 0:098463de4c5d 1720 /* Return function status */
group-onsemi 0:098463de4c5d 1721 return HAL_OK;
group-onsemi 0:098463de4c5d 1722 }
group-onsemi 0:098463de4c5d 1723
group-onsemi 0:098463de4c5d 1724 /**
group-onsemi 0:098463de4c5d 1725 * @brief Stops the TIM Input Capture measurement in interrupt mode.
group-onsemi 0:098463de4c5d 1726 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1727 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1728 * @param Channel: TIM Channels to be disabled.
group-onsemi 0:098463de4c5d 1729 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 1730 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 1731 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 1732 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 1733 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 1734 * @retval HAL status
group-onsemi 0:098463de4c5d 1735 */
group-onsemi 0:098463de4c5d 1736 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 1737 {
group-onsemi 0:098463de4c5d 1738 /* Check the parameters */
group-onsemi 0:098463de4c5d 1739 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
group-onsemi 0:098463de4c5d 1740
group-onsemi 0:098463de4c5d 1741 switch (Channel)
group-onsemi 0:098463de4c5d 1742 {
group-onsemi 0:098463de4c5d 1743 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 1744 {
group-onsemi 0:098463de4c5d 1745 /* Disable the TIM Capture/Compare 1 interrupt */
group-onsemi 0:098463de4c5d 1746 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
group-onsemi 0:098463de4c5d 1747 }
group-onsemi 0:098463de4c5d 1748 break;
group-onsemi 0:098463de4c5d 1749
group-onsemi 0:098463de4c5d 1750 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 1751 {
group-onsemi 0:098463de4c5d 1752 /* Disable the TIM Capture/Compare 2 interrupt */
group-onsemi 0:098463de4c5d 1753 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
group-onsemi 0:098463de4c5d 1754 }
group-onsemi 0:098463de4c5d 1755 break;
group-onsemi 0:098463de4c5d 1756
group-onsemi 0:098463de4c5d 1757 case TIM_CHANNEL_3:
group-onsemi 0:098463de4c5d 1758 {
group-onsemi 0:098463de4c5d 1759 /* Disable the TIM Capture/Compare 3 interrupt */
group-onsemi 0:098463de4c5d 1760 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
group-onsemi 0:098463de4c5d 1761 }
group-onsemi 0:098463de4c5d 1762 break;
group-onsemi 0:098463de4c5d 1763
group-onsemi 0:098463de4c5d 1764 case TIM_CHANNEL_4:
group-onsemi 0:098463de4c5d 1765 {
group-onsemi 0:098463de4c5d 1766 /* Disable the TIM Capture/Compare 4 interrupt */
group-onsemi 0:098463de4c5d 1767 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
group-onsemi 0:098463de4c5d 1768 }
group-onsemi 0:098463de4c5d 1769 break;
group-onsemi 0:098463de4c5d 1770
group-onsemi 0:098463de4c5d 1771 default:
group-onsemi 0:098463de4c5d 1772 break;
group-onsemi 0:098463de4c5d 1773 }
group-onsemi 0:098463de4c5d 1774
group-onsemi 0:098463de4c5d 1775 /* Disable the Input Capture channel */
group-onsemi 0:098463de4c5d 1776 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 1777
group-onsemi 0:098463de4c5d 1778 /* Disable the Peripheral */
group-onsemi 0:098463de4c5d 1779 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 1780
group-onsemi 0:098463de4c5d 1781 /* Return function status */
group-onsemi 0:098463de4c5d 1782 return HAL_OK;
group-onsemi 0:098463de4c5d 1783 }
group-onsemi 0:098463de4c5d 1784
group-onsemi 0:098463de4c5d 1785 /**
group-onsemi 0:098463de4c5d 1786 * @brief Starts the TIM Input Capture measurement on in DMA mode.
group-onsemi 0:098463de4c5d 1787 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1788 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1789 * @param Channel: TIM Channels to be enabled.
group-onsemi 0:098463de4c5d 1790 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 1791 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 1792 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 1793 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 1794 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 1795 * @param pData: The destination Buffer address.
group-onsemi 0:098463de4c5d 1796 * @param Length: The length of data to be transferred from TIM peripheral to memory.
group-onsemi 0:098463de4c5d 1797 * @retval HAL status
group-onsemi 0:098463de4c5d 1798 */
group-onsemi 0:098463de4c5d 1799 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
group-onsemi 0:098463de4c5d 1800 {
group-onsemi 0:098463de4c5d 1801 /* Check the parameters */
group-onsemi 0:098463de4c5d 1802 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
group-onsemi 0:098463de4c5d 1803 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 1804
group-onsemi 0:098463de4c5d 1805 if((htim->State == HAL_TIM_STATE_BUSY))
group-onsemi 0:098463de4c5d 1806 {
group-onsemi 0:098463de4c5d 1807 return HAL_BUSY;
group-onsemi 0:098463de4c5d 1808 }
group-onsemi 0:098463de4c5d 1809 else if((htim->State == HAL_TIM_STATE_READY))
group-onsemi 0:098463de4c5d 1810 {
group-onsemi 0:098463de4c5d 1811 if((pData == 0 ) && (Length > 0))
group-onsemi 0:098463de4c5d 1812 {
group-onsemi 0:098463de4c5d 1813 return HAL_ERROR;
group-onsemi 0:098463de4c5d 1814 }
group-onsemi 0:098463de4c5d 1815 else
group-onsemi 0:098463de4c5d 1816 {
group-onsemi 0:098463de4c5d 1817 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 1818 }
group-onsemi 0:098463de4c5d 1819 }
group-onsemi 0:098463de4c5d 1820
group-onsemi 0:098463de4c5d 1821 switch (Channel)
group-onsemi 0:098463de4c5d 1822 {
group-onsemi 0:098463de4c5d 1823 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 1824 {
group-onsemi 0:098463de4c5d 1825 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 1826 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
group-onsemi 0:098463de4c5d 1827
group-onsemi 0:098463de4c5d 1828 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 1829 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 1830
group-onsemi 0:098463de4c5d 1831 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 1832 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
group-onsemi 0:098463de4c5d 1833
group-onsemi 0:098463de4c5d 1834 /* Enable the TIM Capture/Compare 1 DMA request */
group-onsemi 0:098463de4c5d 1835 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
group-onsemi 0:098463de4c5d 1836 }
group-onsemi 0:098463de4c5d 1837 break;
group-onsemi 0:098463de4c5d 1838
group-onsemi 0:098463de4c5d 1839 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 1840 {
group-onsemi 0:098463de4c5d 1841 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 1842 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
group-onsemi 0:098463de4c5d 1843
group-onsemi 0:098463de4c5d 1844 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 1845 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 1846
group-onsemi 0:098463de4c5d 1847 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 1848 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
group-onsemi 0:098463de4c5d 1849
group-onsemi 0:098463de4c5d 1850 /* Enable the TIM Capture/Compare 2 DMA request */
group-onsemi 0:098463de4c5d 1851 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
group-onsemi 0:098463de4c5d 1852 }
group-onsemi 0:098463de4c5d 1853 break;
group-onsemi 0:098463de4c5d 1854
group-onsemi 0:098463de4c5d 1855 case TIM_CHANNEL_3:
group-onsemi 0:098463de4c5d 1856 {
group-onsemi 0:098463de4c5d 1857 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 1858 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
group-onsemi 0:098463de4c5d 1859
group-onsemi 0:098463de4c5d 1860 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 1861 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 1862
group-onsemi 0:098463de4c5d 1863 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 1864 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
group-onsemi 0:098463de4c5d 1865
group-onsemi 0:098463de4c5d 1866 /* Enable the TIM Capture/Compare 3 DMA request */
group-onsemi 0:098463de4c5d 1867 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
group-onsemi 0:098463de4c5d 1868 }
group-onsemi 0:098463de4c5d 1869 break;
group-onsemi 0:098463de4c5d 1870
group-onsemi 0:098463de4c5d 1871 case TIM_CHANNEL_4:
group-onsemi 0:098463de4c5d 1872 {
group-onsemi 0:098463de4c5d 1873 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 1874 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
group-onsemi 0:098463de4c5d 1875
group-onsemi 0:098463de4c5d 1876 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 1877 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 1878
group-onsemi 0:098463de4c5d 1879 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 1880 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
group-onsemi 0:098463de4c5d 1881
group-onsemi 0:098463de4c5d 1882 /* Enable the TIM Capture/Compare 4 DMA request */
group-onsemi 0:098463de4c5d 1883 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
group-onsemi 0:098463de4c5d 1884 }
group-onsemi 0:098463de4c5d 1885 break;
group-onsemi 0:098463de4c5d 1886
group-onsemi 0:098463de4c5d 1887 default:
group-onsemi 0:098463de4c5d 1888 break;
group-onsemi 0:098463de4c5d 1889 }
group-onsemi 0:098463de4c5d 1890
group-onsemi 0:098463de4c5d 1891 /* Enable the Input Capture channel */
group-onsemi 0:098463de4c5d 1892 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 1893
group-onsemi 0:098463de4c5d 1894 /* Enable the Peripheral */
group-onsemi 0:098463de4c5d 1895 __HAL_TIM_ENABLE(htim);
group-onsemi 0:098463de4c5d 1896
group-onsemi 0:098463de4c5d 1897 /* Return function status */
group-onsemi 0:098463de4c5d 1898 return HAL_OK;
group-onsemi 0:098463de4c5d 1899 }
group-onsemi 0:098463de4c5d 1900
group-onsemi 0:098463de4c5d 1901 /**
group-onsemi 0:098463de4c5d 1902 * @brief Stops the TIM Input Capture measurement on in DMA mode.
group-onsemi 0:098463de4c5d 1903 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1904 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1905 * @param Channel: TIM Channels to be disabled.
group-onsemi 0:098463de4c5d 1906 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 1907 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 1908 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 1909 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 1910 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 1911 * @retval HAL status
group-onsemi 0:098463de4c5d 1912 */
group-onsemi 0:098463de4c5d 1913 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 1914 {
group-onsemi 0:098463de4c5d 1915 /* Check the parameters */
group-onsemi 0:098463de4c5d 1916 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
group-onsemi 0:098463de4c5d 1917 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 1918
group-onsemi 0:098463de4c5d 1919 switch (Channel)
group-onsemi 0:098463de4c5d 1920 {
group-onsemi 0:098463de4c5d 1921 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 1922 {
group-onsemi 0:098463de4c5d 1923 /* Disable the TIM Capture/Compare 1 DMA request */
group-onsemi 0:098463de4c5d 1924 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
group-onsemi 0:098463de4c5d 1925 }
group-onsemi 0:098463de4c5d 1926 break;
group-onsemi 0:098463de4c5d 1927
group-onsemi 0:098463de4c5d 1928 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 1929 {
group-onsemi 0:098463de4c5d 1930 /* Disable the TIM Capture/Compare 2 DMA request */
group-onsemi 0:098463de4c5d 1931 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
group-onsemi 0:098463de4c5d 1932 }
group-onsemi 0:098463de4c5d 1933 break;
group-onsemi 0:098463de4c5d 1934
group-onsemi 0:098463de4c5d 1935 case TIM_CHANNEL_3:
group-onsemi 0:098463de4c5d 1936 {
group-onsemi 0:098463de4c5d 1937 /* Disable the TIM Capture/Compare 3 DMA request */
group-onsemi 0:098463de4c5d 1938 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
group-onsemi 0:098463de4c5d 1939 }
group-onsemi 0:098463de4c5d 1940 break;
group-onsemi 0:098463de4c5d 1941
group-onsemi 0:098463de4c5d 1942 case TIM_CHANNEL_4:
group-onsemi 0:098463de4c5d 1943 {
group-onsemi 0:098463de4c5d 1944 /* Disable the TIM Capture/Compare 4 DMA request */
group-onsemi 0:098463de4c5d 1945 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
group-onsemi 0:098463de4c5d 1946 }
group-onsemi 0:098463de4c5d 1947 break;
group-onsemi 0:098463de4c5d 1948
group-onsemi 0:098463de4c5d 1949 default:
group-onsemi 0:098463de4c5d 1950 break;
group-onsemi 0:098463de4c5d 1951 }
group-onsemi 0:098463de4c5d 1952
group-onsemi 0:098463de4c5d 1953 /* Disable the Input Capture channel */
group-onsemi 0:098463de4c5d 1954 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 1955
group-onsemi 0:098463de4c5d 1956 /* Disable the Peripheral */
group-onsemi 0:098463de4c5d 1957 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 1958
group-onsemi 0:098463de4c5d 1959 /* Change the htim state */
group-onsemi 0:098463de4c5d 1960 htim->State = HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 1961
group-onsemi 0:098463de4c5d 1962 /* Return function status */
group-onsemi 0:098463de4c5d 1963 return HAL_OK;
group-onsemi 0:098463de4c5d 1964 }
group-onsemi 0:098463de4c5d 1965 /**
group-onsemi 0:098463de4c5d 1966 * @}
group-onsemi 0:098463de4c5d 1967 */
group-onsemi 0:098463de4c5d 1968
group-onsemi 0:098463de4c5d 1969 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
group-onsemi 0:098463de4c5d 1970 * @brief Time One Pulse functions
group-onsemi 0:098463de4c5d 1971 *
group-onsemi 0:098463de4c5d 1972 @verbatim
group-onsemi 0:098463de4c5d 1973 ==============================================================================
group-onsemi 0:098463de4c5d 1974 ##### Time One Pulse functions #####
group-onsemi 0:098463de4c5d 1975 ==============================================================================
group-onsemi 0:098463de4c5d 1976 [..]
group-onsemi 0:098463de4c5d 1977 This section provides functions allowing to:
group-onsemi 0:098463de4c5d 1978 (+) Initialize and configure the TIM One Pulse.
group-onsemi 0:098463de4c5d 1979 (+) De-initialize the TIM One Pulse.
group-onsemi 0:098463de4c5d 1980 (+) Start the Time One Pulse.
group-onsemi 0:098463de4c5d 1981 (+) Stop the Time One Pulse.
group-onsemi 0:098463de4c5d 1982 (+) Start the Time One Pulse and enable interrupt.
group-onsemi 0:098463de4c5d 1983 (+) Stop the Time One Pulse and disable interrupt.
group-onsemi 0:098463de4c5d 1984 (+) Start the Time One Pulse and enable DMA transfer.
group-onsemi 0:098463de4c5d 1985 (+) Stop the Time One Pulse and disable DMA transfer.
group-onsemi 0:098463de4c5d 1986
group-onsemi 0:098463de4c5d 1987 @endverbatim
group-onsemi 0:098463de4c5d 1988 * @{
group-onsemi 0:098463de4c5d 1989 */
group-onsemi 0:098463de4c5d 1990 /**
group-onsemi 0:098463de4c5d 1991 * @brief Initializes the TIM One Pulse Time Base according to the specified
group-onsemi 0:098463de4c5d 1992 * parameters in the TIM_HandleTypeDef and create the associated handle.
group-onsemi 0:098463de4c5d 1993 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1994 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 1995 * @param OnePulseMode: Select the One pulse mode.
group-onsemi 0:098463de4c5d 1996 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 1997 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
group-onsemi 0:098463de4c5d 1998 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
group-onsemi 0:098463de4c5d 1999 * @retval HAL status
group-onsemi 0:098463de4c5d 2000 */
group-onsemi 0:098463de4c5d 2001 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
group-onsemi 0:098463de4c5d 2002 {
group-onsemi 0:098463de4c5d 2003 /* Check the TIM handle allocation */
group-onsemi 0:098463de4c5d 2004 if(htim == NULL)
group-onsemi 0:098463de4c5d 2005 {
group-onsemi 0:098463de4c5d 2006 return HAL_ERROR;
group-onsemi 0:098463de4c5d 2007 }
group-onsemi 0:098463de4c5d 2008
group-onsemi 0:098463de4c5d 2009 /* Check the parameters */
group-onsemi 0:098463de4c5d 2010 assert_param(IS_TIM_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 2011 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
group-onsemi 0:098463de4c5d 2012 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
group-onsemi 0:098463de4c5d 2013 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
group-onsemi 0:098463de4c5d 2014
group-onsemi 0:098463de4c5d 2015 if(htim->State == HAL_TIM_STATE_RESET)
group-onsemi 0:098463de4c5d 2016 {
group-onsemi 0:098463de4c5d 2017 /* Allocate lock resource and initialize it */
group-onsemi 0:098463de4c5d 2018 htim->Lock = HAL_UNLOCKED;
group-onsemi 0:098463de4c5d 2019 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
group-onsemi 0:098463de4c5d 2020 HAL_TIM_OnePulse_MspInit(htim);
group-onsemi 0:098463de4c5d 2021 }
group-onsemi 0:098463de4c5d 2022
group-onsemi 0:098463de4c5d 2023 /* Set the TIM state */
group-onsemi 0:098463de4c5d 2024 htim->State= HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 2025
group-onsemi 0:098463de4c5d 2026 /* Configure the Time base in the One Pulse Mode */
group-onsemi 0:098463de4c5d 2027 TIM_Base_SetConfig(htim->Instance, &htim->Init);
group-onsemi 0:098463de4c5d 2028
group-onsemi 0:098463de4c5d 2029 /* Reset the OPM Bit */
group-onsemi 0:098463de4c5d 2030 htim->Instance->CR1 &= ~TIM_CR1_OPM;
group-onsemi 0:098463de4c5d 2031
group-onsemi 0:098463de4c5d 2032 /* Configure the OPM Mode */
group-onsemi 0:098463de4c5d 2033 htim->Instance->CR1 |= OnePulseMode;
group-onsemi 0:098463de4c5d 2034
group-onsemi 0:098463de4c5d 2035 /* Initialize the TIM state*/
group-onsemi 0:098463de4c5d 2036 htim->State= HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 2037
group-onsemi 0:098463de4c5d 2038 return HAL_OK;
group-onsemi 0:098463de4c5d 2039 }
group-onsemi 0:098463de4c5d 2040
group-onsemi 0:098463de4c5d 2041 /**
group-onsemi 0:098463de4c5d 2042 * @brief DeInitializes the TIM One Pulse
group-onsemi 0:098463de4c5d 2043 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2044 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2045 * @retval HAL status
group-onsemi 0:098463de4c5d 2046 */
group-onsemi 0:098463de4c5d 2047 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 2048 {
group-onsemi 0:098463de4c5d 2049 /* Check the parameters */
group-onsemi 0:098463de4c5d 2050 assert_param(IS_TIM_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 2051
group-onsemi 0:098463de4c5d 2052 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 2053
group-onsemi 0:098463de4c5d 2054 /* Disable the TIM Peripheral Clock */
group-onsemi 0:098463de4c5d 2055 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 2056
group-onsemi 0:098463de4c5d 2057 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
group-onsemi 0:098463de4c5d 2058 HAL_TIM_OnePulse_MspDeInit(htim);
group-onsemi 0:098463de4c5d 2059
group-onsemi 0:098463de4c5d 2060 /* Change TIM state */
group-onsemi 0:098463de4c5d 2061 htim->State = HAL_TIM_STATE_RESET;
group-onsemi 0:098463de4c5d 2062
group-onsemi 0:098463de4c5d 2063 /* Release Lock */
group-onsemi 0:098463de4c5d 2064 __HAL_UNLOCK(htim);
group-onsemi 0:098463de4c5d 2065
group-onsemi 0:098463de4c5d 2066 return HAL_OK;
group-onsemi 0:098463de4c5d 2067 }
group-onsemi 0:098463de4c5d 2068
group-onsemi 0:098463de4c5d 2069 /**
group-onsemi 0:098463de4c5d 2070 * @brief Initializes the TIM One Pulse MSP.
group-onsemi 0:098463de4c5d 2071 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2072 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2073 * @retval None
group-onsemi 0:098463de4c5d 2074 */
group-onsemi 0:098463de4c5d 2075 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 2076 {
group-onsemi 0:098463de4c5d 2077 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 2078 UNUSED(htim);
group-onsemi 0:098463de4c5d 2079
group-onsemi 0:098463de4c5d 2080 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 2081 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
group-onsemi 0:098463de4c5d 2082 */
group-onsemi 0:098463de4c5d 2083 }
group-onsemi 0:098463de4c5d 2084
group-onsemi 0:098463de4c5d 2085 /**
group-onsemi 0:098463de4c5d 2086 * @brief DeInitializes TIM One Pulse MSP.
group-onsemi 0:098463de4c5d 2087 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2088 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2089 * @retval None
group-onsemi 0:098463de4c5d 2090 */
group-onsemi 0:098463de4c5d 2091 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 2092 {
group-onsemi 0:098463de4c5d 2093 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 2094 UNUSED(htim);
group-onsemi 0:098463de4c5d 2095
group-onsemi 0:098463de4c5d 2096 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 2097 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
group-onsemi 0:098463de4c5d 2098 */
group-onsemi 0:098463de4c5d 2099 }
group-onsemi 0:098463de4c5d 2100
group-onsemi 0:098463de4c5d 2101 /**
group-onsemi 0:098463de4c5d 2102 * @brief Starts the TIM One Pulse signal generation.
group-onsemi 0:098463de4c5d 2103 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2104 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2105 * @param OutputChannel : TIM Channels to be enabled.
group-onsemi 0:098463de4c5d 2106 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 2107 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 2108 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 2109 * @retval HAL status
group-onsemi 0:098463de4c5d 2110 */
group-onsemi 0:098463de4c5d 2111 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
group-onsemi 0:098463de4c5d 2112 {
group-onsemi 0:098463de4c5d 2113 /* Enable the Capture compare and the Input Capture channels
group-onsemi 0:098463de4c5d 2114 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
group-onsemi 0:098463de4c5d 2115 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
group-onsemi 0:098463de4c5d 2116 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
group-onsemi 0:098463de4c5d 2117 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
group-onsemi 0:098463de4c5d 2118
group-onsemi 0:098463de4c5d 2119 No need to enable the counter, it's enabled automatically by hardware
group-onsemi 0:098463de4c5d 2120 (the counter starts in response to a stimulus and generate a pulse */
group-onsemi 0:098463de4c5d 2121
group-onsemi 0:098463de4c5d 2122 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 2123 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 2124
group-onsemi 0:098463de4c5d 2125 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
group-onsemi 0:098463de4c5d 2126 {
group-onsemi 0:098463de4c5d 2127 /* Enable the main output */
group-onsemi 0:098463de4c5d 2128 __HAL_TIM_MOE_ENABLE(htim);
group-onsemi 0:098463de4c5d 2129 }
group-onsemi 0:098463de4c5d 2130
group-onsemi 0:098463de4c5d 2131 /* Return function status */
group-onsemi 0:098463de4c5d 2132 return HAL_OK;
group-onsemi 0:098463de4c5d 2133 }
group-onsemi 0:098463de4c5d 2134
group-onsemi 0:098463de4c5d 2135 /**
group-onsemi 0:098463de4c5d 2136 * @brief Stops the TIM One Pulse signal generation.
group-onsemi 0:098463de4c5d 2137 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2138 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2139 * @param OutputChannel : TIM Channels to be disable.
group-onsemi 0:098463de4c5d 2140 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 2141 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 2142 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 2143 * @retval HAL status
group-onsemi 0:098463de4c5d 2144 */
group-onsemi 0:098463de4c5d 2145 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
group-onsemi 0:098463de4c5d 2146 {
group-onsemi 0:098463de4c5d 2147 /* Disable the Capture compare and the Input Capture channels
group-onsemi 0:098463de4c5d 2148 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
group-onsemi 0:098463de4c5d 2149 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
group-onsemi 0:098463de4c5d 2150 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
group-onsemi 0:098463de4c5d 2151 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
group-onsemi 0:098463de4c5d 2152
group-onsemi 0:098463de4c5d 2153 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 2154 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 2155
group-onsemi 0:098463de4c5d 2156 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
group-onsemi 0:098463de4c5d 2157 {
group-onsemi 0:098463de4c5d 2158 /* Disable the Main Output */
group-onsemi 0:098463de4c5d 2159 __HAL_TIM_MOE_DISABLE(htim);
group-onsemi 0:098463de4c5d 2160 }
group-onsemi 0:098463de4c5d 2161
group-onsemi 0:098463de4c5d 2162 /* Disable the Peripheral */
group-onsemi 0:098463de4c5d 2163 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 2164
group-onsemi 0:098463de4c5d 2165 /* Return function status */
group-onsemi 0:098463de4c5d 2166 return HAL_OK;
group-onsemi 0:098463de4c5d 2167 }
group-onsemi 0:098463de4c5d 2168
group-onsemi 0:098463de4c5d 2169 /**
group-onsemi 0:098463de4c5d 2170 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
group-onsemi 0:098463de4c5d 2171 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2172 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2173 * @param OutputChannel : TIM Channels to be enabled.
group-onsemi 0:098463de4c5d 2174 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 2175 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 2176 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 2177 * @retval HAL status
group-onsemi 0:098463de4c5d 2178 */
group-onsemi 0:098463de4c5d 2179 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
group-onsemi 0:098463de4c5d 2180 {
group-onsemi 0:098463de4c5d 2181 /* Enable the Capture compare and the Input Capture channels
group-onsemi 0:098463de4c5d 2182 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
group-onsemi 0:098463de4c5d 2183 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
group-onsemi 0:098463de4c5d 2184 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
group-onsemi 0:098463de4c5d 2185 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
group-onsemi 0:098463de4c5d 2186
group-onsemi 0:098463de4c5d 2187 No need to enable the counter, it's enabled automatically by hardware
group-onsemi 0:098463de4c5d 2188 (the counter starts in response to a stimulus and generate a pulse */
group-onsemi 0:098463de4c5d 2189
group-onsemi 0:098463de4c5d 2190 /* Enable the TIM Capture/Compare 1 interrupt */
group-onsemi 0:098463de4c5d 2191 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
group-onsemi 0:098463de4c5d 2192
group-onsemi 0:098463de4c5d 2193 /* Enable the TIM Capture/Compare 2 interrupt */
group-onsemi 0:098463de4c5d 2194 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
group-onsemi 0:098463de4c5d 2195
group-onsemi 0:098463de4c5d 2196 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 2197 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 2198
group-onsemi 0:098463de4c5d 2199 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
group-onsemi 0:098463de4c5d 2200 {
group-onsemi 0:098463de4c5d 2201 /* Enable the main output */
group-onsemi 0:098463de4c5d 2202 __HAL_TIM_MOE_ENABLE(htim);
group-onsemi 0:098463de4c5d 2203 }
group-onsemi 0:098463de4c5d 2204
group-onsemi 0:098463de4c5d 2205 /* Return function status */
group-onsemi 0:098463de4c5d 2206 return HAL_OK;
group-onsemi 0:098463de4c5d 2207 }
group-onsemi 0:098463de4c5d 2208
group-onsemi 0:098463de4c5d 2209 /**
group-onsemi 0:098463de4c5d 2210 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
group-onsemi 0:098463de4c5d 2211 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2212 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2213 * @param OutputChannel : TIM Channels to be enabled.
group-onsemi 0:098463de4c5d 2214 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 2215 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 2216 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 2217 * @retval HAL status
group-onsemi 0:098463de4c5d 2218 */
group-onsemi 0:098463de4c5d 2219 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
group-onsemi 0:098463de4c5d 2220 {
group-onsemi 0:098463de4c5d 2221 /* Disable the TIM Capture/Compare 1 interrupt */
group-onsemi 0:098463de4c5d 2222 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
group-onsemi 0:098463de4c5d 2223
group-onsemi 0:098463de4c5d 2224 /* Disable the TIM Capture/Compare 2 interrupt */
group-onsemi 0:098463de4c5d 2225 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
group-onsemi 0:098463de4c5d 2226
group-onsemi 0:098463de4c5d 2227 /* Disable the Capture compare and the Input Capture channels
group-onsemi 0:098463de4c5d 2228 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
group-onsemi 0:098463de4c5d 2229 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
group-onsemi 0:098463de4c5d 2230 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
group-onsemi 0:098463de4c5d 2231 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
group-onsemi 0:098463de4c5d 2232 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 2233 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 2234
group-onsemi 0:098463de4c5d 2235 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
group-onsemi 0:098463de4c5d 2236 {
group-onsemi 0:098463de4c5d 2237 /* Disable the Main Output */
group-onsemi 0:098463de4c5d 2238 __HAL_TIM_MOE_DISABLE(htim);
group-onsemi 0:098463de4c5d 2239 }
group-onsemi 0:098463de4c5d 2240
group-onsemi 0:098463de4c5d 2241 /* Disable the Peripheral */
group-onsemi 0:098463de4c5d 2242 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 2243
group-onsemi 0:098463de4c5d 2244 /* Return function status */
group-onsemi 0:098463de4c5d 2245 return HAL_OK;
group-onsemi 0:098463de4c5d 2246 }
group-onsemi 0:098463de4c5d 2247
group-onsemi 0:098463de4c5d 2248 /**
group-onsemi 0:098463de4c5d 2249 * @}
group-onsemi 0:098463de4c5d 2250 */
group-onsemi 0:098463de4c5d 2251
group-onsemi 0:098463de4c5d 2252 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
group-onsemi 0:098463de4c5d 2253 * @brief Time Encoder functions
group-onsemi 0:098463de4c5d 2254 *
group-onsemi 0:098463de4c5d 2255 @verbatim
group-onsemi 0:098463de4c5d 2256 ==============================================================================
group-onsemi 0:098463de4c5d 2257 ##### Time Encoder functions #####
group-onsemi 0:098463de4c5d 2258 ==============================================================================
group-onsemi 0:098463de4c5d 2259 [..]
group-onsemi 0:098463de4c5d 2260 This section provides functions allowing to:
group-onsemi 0:098463de4c5d 2261 (+) Initialize and configure the TIM Encoder.
group-onsemi 0:098463de4c5d 2262 (+) De-initialize the TIM Encoder.
group-onsemi 0:098463de4c5d 2263 (+) Start the Time Encoder.
group-onsemi 0:098463de4c5d 2264 (+) Stop the Time Encoder.
group-onsemi 0:098463de4c5d 2265 (+) Start the Time Encoder and enable interrupt.
group-onsemi 0:098463de4c5d 2266 (+) Stop the Time Encoder and disable interrupt.
group-onsemi 0:098463de4c5d 2267 (+) Start the Time Encoder and enable DMA transfer.
group-onsemi 0:098463de4c5d 2268 (+) Stop the Time Encoder and disable DMA transfer.
group-onsemi 0:098463de4c5d 2269
group-onsemi 0:098463de4c5d 2270 @endverbatim
group-onsemi 0:098463de4c5d 2271 * @{
group-onsemi 0:098463de4c5d 2272 */
group-onsemi 0:098463de4c5d 2273 /**
group-onsemi 0:098463de4c5d 2274 * @brief Initializes the TIM Encoder Interface and create the associated handle.
group-onsemi 0:098463de4c5d 2275 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2276 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2277 * @param sConfig: TIM Encoder Interface configuration structure
group-onsemi 0:098463de4c5d 2278 * @retval HAL status
group-onsemi 0:098463de4c5d 2279 */
group-onsemi 0:098463de4c5d 2280 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
group-onsemi 0:098463de4c5d 2281 {
group-onsemi 0:098463de4c5d 2282 uint32_t tmpsmcr = 0;
group-onsemi 0:098463de4c5d 2283 uint32_t tmpccmr1 = 0;
group-onsemi 0:098463de4c5d 2284 uint32_t tmpccer = 0;
group-onsemi 0:098463de4c5d 2285
group-onsemi 0:098463de4c5d 2286 /* Check the TIM handle allocation */
group-onsemi 0:098463de4c5d 2287 if(htim == NULL)
group-onsemi 0:098463de4c5d 2288 {
group-onsemi 0:098463de4c5d 2289 return HAL_ERROR;
group-onsemi 0:098463de4c5d 2290 }
group-onsemi 0:098463de4c5d 2291
group-onsemi 0:098463de4c5d 2292 /* Check the parameters */
group-onsemi 0:098463de4c5d 2293 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 2294 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
group-onsemi 0:098463de4c5d 2295 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
group-onsemi 0:098463de4c5d 2296 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
group-onsemi 0:098463de4c5d 2297 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
group-onsemi 0:098463de4c5d 2298 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
group-onsemi 0:098463de4c5d 2299 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
group-onsemi 0:098463de4c5d 2300 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
group-onsemi 0:098463de4c5d 2301 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
group-onsemi 0:098463de4c5d 2302 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
group-onsemi 0:098463de4c5d 2303
group-onsemi 0:098463de4c5d 2304 if(htim->State == HAL_TIM_STATE_RESET)
group-onsemi 0:098463de4c5d 2305 {
group-onsemi 0:098463de4c5d 2306 /* Allocate lock resource and initialize it */
group-onsemi 0:098463de4c5d 2307 htim->Lock = HAL_UNLOCKED;
group-onsemi 0:098463de4c5d 2308 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
group-onsemi 0:098463de4c5d 2309 HAL_TIM_Encoder_MspInit(htim);
group-onsemi 0:098463de4c5d 2310 }
group-onsemi 0:098463de4c5d 2311
group-onsemi 0:098463de4c5d 2312 /* Set the TIM state */
group-onsemi 0:098463de4c5d 2313 htim->State= HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 2314
group-onsemi 0:098463de4c5d 2315 /* Reset the SMS bits */
group-onsemi 0:098463de4c5d 2316 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
group-onsemi 0:098463de4c5d 2317
group-onsemi 0:098463de4c5d 2318 /* Configure the Time base in the Encoder Mode */
group-onsemi 0:098463de4c5d 2319 TIM_Base_SetConfig(htim->Instance, &htim->Init);
group-onsemi 0:098463de4c5d 2320
group-onsemi 0:098463de4c5d 2321 /* Get the TIMx SMCR register value */
group-onsemi 0:098463de4c5d 2322 tmpsmcr = htim->Instance->SMCR;
group-onsemi 0:098463de4c5d 2323
group-onsemi 0:098463de4c5d 2324 /* Get the TIMx CCMR1 register value */
group-onsemi 0:098463de4c5d 2325 tmpccmr1 = htim->Instance->CCMR1;
group-onsemi 0:098463de4c5d 2326
group-onsemi 0:098463de4c5d 2327 /* Get the TIMx CCER register value */
group-onsemi 0:098463de4c5d 2328 tmpccer = htim->Instance->CCER;
group-onsemi 0:098463de4c5d 2329
group-onsemi 0:098463de4c5d 2330 /* Set the encoder Mode */
group-onsemi 0:098463de4c5d 2331 tmpsmcr |= sConfig->EncoderMode;
group-onsemi 0:098463de4c5d 2332
group-onsemi 0:098463de4c5d 2333 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
group-onsemi 0:098463de4c5d 2334 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
group-onsemi 0:098463de4c5d 2335 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
group-onsemi 0:098463de4c5d 2336
group-onsemi 0:098463de4c5d 2337 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
group-onsemi 0:098463de4c5d 2338 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
group-onsemi 0:098463de4c5d 2339 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
group-onsemi 0:098463de4c5d 2340 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
group-onsemi 0:098463de4c5d 2341 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
group-onsemi 0:098463de4c5d 2342
group-onsemi 0:098463de4c5d 2343 /* Set the TI1 and the TI2 Polarities */
group-onsemi 0:098463de4c5d 2344 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
group-onsemi 0:098463de4c5d 2345 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
group-onsemi 0:098463de4c5d 2346 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
group-onsemi 0:098463de4c5d 2347
group-onsemi 0:098463de4c5d 2348 /* Write to TIMx SMCR */
group-onsemi 0:098463de4c5d 2349 htim->Instance->SMCR = tmpsmcr;
group-onsemi 0:098463de4c5d 2350
group-onsemi 0:098463de4c5d 2351 /* Write to TIMx CCMR1 */
group-onsemi 0:098463de4c5d 2352 htim->Instance->CCMR1 = tmpccmr1;
group-onsemi 0:098463de4c5d 2353
group-onsemi 0:098463de4c5d 2354 /* Write to TIMx CCER */
group-onsemi 0:098463de4c5d 2355 htim->Instance->CCER = tmpccer;
group-onsemi 0:098463de4c5d 2356
group-onsemi 0:098463de4c5d 2357 /* Initialize the TIM state*/
group-onsemi 0:098463de4c5d 2358 htim->State= HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 2359
group-onsemi 0:098463de4c5d 2360 return HAL_OK;
group-onsemi 0:098463de4c5d 2361 }
group-onsemi 0:098463de4c5d 2362
group-onsemi 0:098463de4c5d 2363 /**
group-onsemi 0:098463de4c5d 2364 * @brief DeInitializes the TIM Encoder interface
group-onsemi 0:098463de4c5d 2365 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2366 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2367 * @retval HAL status
group-onsemi 0:098463de4c5d 2368 */
group-onsemi 0:098463de4c5d 2369 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 2370 {
group-onsemi 0:098463de4c5d 2371 /* Check the parameters */
group-onsemi 0:098463de4c5d 2372 assert_param(IS_TIM_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 2373
group-onsemi 0:098463de4c5d 2374 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 2375
group-onsemi 0:098463de4c5d 2376 /* Disable the TIM Peripheral Clock */
group-onsemi 0:098463de4c5d 2377 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 2378
group-onsemi 0:098463de4c5d 2379 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
group-onsemi 0:098463de4c5d 2380 HAL_TIM_Encoder_MspDeInit(htim);
group-onsemi 0:098463de4c5d 2381
group-onsemi 0:098463de4c5d 2382 /* Change TIM state */
group-onsemi 0:098463de4c5d 2383 htim->State = HAL_TIM_STATE_RESET;
group-onsemi 0:098463de4c5d 2384
group-onsemi 0:098463de4c5d 2385 /* Release Lock */
group-onsemi 0:098463de4c5d 2386 __HAL_UNLOCK(htim);
group-onsemi 0:098463de4c5d 2387
group-onsemi 0:098463de4c5d 2388 return HAL_OK;
group-onsemi 0:098463de4c5d 2389 }
group-onsemi 0:098463de4c5d 2390
group-onsemi 0:098463de4c5d 2391 /**
group-onsemi 0:098463de4c5d 2392 * @brief Initializes the TIM Encoder Interface MSP.
group-onsemi 0:098463de4c5d 2393 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2394 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2395 * @retval None
group-onsemi 0:098463de4c5d 2396 */
group-onsemi 0:098463de4c5d 2397 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 2398 {
group-onsemi 0:098463de4c5d 2399 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 2400 UNUSED(htim);
group-onsemi 0:098463de4c5d 2401
group-onsemi 0:098463de4c5d 2402 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 2403 the HAL_TIM_Encoder_MspInit could be implemented in the user file
group-onsemi 0:098463de4c5d 2404 */
group-onsemi 0:098463de4c5d 2405 }
group-onsemi 0:098463de4c5d 2406
group-onsemi 0:098463de4c5d 2407 /**
group-onsemi 0:098463de4c5d 2408 * @brief DeInitializes TIM Encoder Interface MSP.
group-onsemi 0:098463de4c5d 2409 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2410 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2411 * @retval None
group-onsemi 0:098463de4c5d 2412 */
group-onsemi 0:098463de4c5d 2413 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 2414 {
group-onsemi 0:098463de4c5d 2415 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 2416 UNUSED(htim);
group-onsemi 0:098463de4c5d 2417
group-onsemi 0:098463de4c5d 2418 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 2419 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
group-onsemi 0:098463de4c5d 2420 */
group-onsemi 0:098463de4c5d 2421 }
group-onsemi 0:098463de4c5d 2422
group-onsemi 0:098463de4c5d 2423 /**
group-onsemi 0:098463de4c5d 2424 * @brief Starts the TIM Encoder Interface.
group-onsemi 0:098463de4c5d 2425 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2426 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2427 * @param Channel: TIM Channels to be enabled.
group-onsemi 0:098463de4c5d 2428 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 2429 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 2430 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 2431 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
group-onsemi 0:098463de4c5d 2432 * @retval HAL status
group-onsemi 0:098463de4c5d 2433 */
group-onsemi 0:098463de4c5d 2434 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 2435 {
group-onsemi 0:098463de4c5d 2436 /* Check the parameters */
group-onsemi 0:098463de4c5d 2437 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 2438
group-onsemi 0:098463de4c5d 2439 /* Enable the encoder interface channels */
group-onsemi 0:098463de4c5d 2440 switch (Channel)
group-onsemi 0:098463de4c5d 2441 {
group-onsemi 0:098463de4c5d 2442 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 2443 {
group-onsemi 0:098463de4c5d 2444 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 2445 break;
group-onsemi 0:098463de4c5d 2446 }
group-onsemi 0:098463de4c5d 2447 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 2448 {
group-onsemi 0:098463de4c5d 2449 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 2450 break;
group-onsemi 0:098463de4c5d 2451 }
group-onsemi 0:098463de4c5d 2452 default :
group-onsemi 0:098463de4c5d 2453 {
group-onsemi 0:098463de4c5d 2454 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 2455 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 2456 break;
group-onsemi 0:098463de4c5d 2457 }
group-onsemi 0:098463de4c5d 2458 }
group-onsemi 0:098463de4c5d 2459 /* Enable the Peripheral */
group-onsemi 0:098463de4c5d 2460 __HAL_TIM_ENABLE(htim);
group-onsemi 0:098463de4c5d 2461
group-onsemi 0:098463de4c5d 2462 /* Return function status */
group-onsemi 0:098463de4c5d 2463 return HAL_OK;
group-onsemi 0:098463de4c5d 2464 }
group-onsemi 0:098463de4c5d 2465
group-onsemi 0:098463de4c5d 2466 /**
group-onsemi 0:098463de4c5d 2467 * @brief Stops the TIM Encoder Interface.
group-onsemi 0:098463de4c5d 2468 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2469 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2470 * @param Channel: TIM Channels to be disabled.
group-onsemi 0:098463de4c5d 2471 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 2472 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 2473 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 2474 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
group-onsemi 0:098463de4c5d 2475 * @retval HAL status
group-onsemi 0:098463de4c5d 2476 */
group-onsemi 0:098463de4c5d 2477 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 2478 {
group-onsemi 0:098463de4c5d 2479 /* Check the parameters */
group-onsemi 0:098463de4c5d 2480 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 2481
group-onsemi 0:098463de4c5d 2482 /* Disable the Input Capture channels 1 and 2
group-onsemi 0:098463de4c5d 2483 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
group-onsemi 0:098463de4c5d 2484 switch (Channel)
group-onsemi 0:098463de4c5d 2485 {
group-onsemi 0:098463de4c5d 2486 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 2487 {
group-onsemi 0:098463de4c5d 2488 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 2489 break;
group-onsemi 0:098463de4c5d 2490 }
group-onsemi 0:098463de4c5d 2491 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 2492 {
group-onsemi 0:098463de4c5d 2493 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 2494 break;
group-onsemi 0:098463de4c5d 2495 }
group-onsemi 0:098463de4c5d 2496 default :
group-onsemi 0:098463de4c5d 2497 {
group-onsemi 0:098463de4c5d 2498 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 2499 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 2500 break;
group-onsemi 0:098463de4c5d 2501 }
group-onsemi 0:098463de4c5d 2502 }
group-onsemi 0:098463de4c5d 2503 /* Disable the Peripheral */
group-onsemi 0:098463de4c5d 2504 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 2505
group-onsemi 0:098463de4c5d 2506 /* Return function status */
group-onsemi 0:098463de4c5d 2507 return HAL_OK;
group-onsemi 0:098463de4c5d 2508 }
group-onsemi 0:098463de4c5d 2509
group-onsemi 0:098463de4c5d 2510 /**
group-onsemi 0:098463de4c5d 2511 * @brief Starts the TIM Encoder Interface in interrupt mode.
group-onsemi 0:098463de4c5d 2512 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2513 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2514 * @param Channel: TIM Channels to be enabled.
group-onsemi 0:098463de4c5d 2515 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 2516 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 2517 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 2518 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
group-onsemi 0:098463de4c5d 2519 * @retval HAL status
group-onsemi 0:098463de4c5d 2520 */
group-onsemi 0:098463de4c5d 2521 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 2522 {
group-onsemi 0:098463de4c5d 2523 /* Check the parameters */
group-onsemi 0:098463de4c5d 2524 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 2525
group-onsemi 0:098463de4c5d 2526 /* Enable the encoder interface channels */
group-onsemi 0:098463de4c5d 2527 /* Enable the capture compare Interrupts 1 and/or 2 */
group-onsemi 0:098463de4c5d 2528 switch (Channel)
group-onsemi 0:098463de4c5d 2529 {
group-onsemi 0:098463de4c5d 2530 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 2531 {
group-onsemi 0:098463de4c5d 2532 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 2533 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
group-onsemi 0:098463de4c5d 2534 break;
group-onsemi 0:098463de4c5d 2535 }
group-onsemi 0:098463de4c5d 2536 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 2537 {
group-onsemi 0:098463de4c5d 2538 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 2539 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
group-onsemi 0:098463de4c5d 2540 break;
group-onsemi 0:098463de4c5d 2541 }
group-onsemi 0:098463de4c5d 2542 default :
group-onsemi 0:098463de4c5d 2543 {
group-onsemi 0:098463de4c5d 2544 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 2545 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 2546 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
group-onsemi 0:098463de4c5d 2547 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
group-onsemi 0:098463de4c5d 2548 break;
group-onsemi 0:098463de4c5d 2549 }
group-onsemi 0:098463de4c5d 2550 }
group-onsemi 0:098463de4c5d 2551
group-onsemi 0:098463de4c5d 2552 /* Enable the Peripheral */
group-onsemi 0:098463de4c5d 2553 __HAL_TIM_ENABLE(htim);
group-onsemi 0:098463de4c5d 2554
group-onsemi 0:098463de4c5d 2555 /* Return function status */
group-onsemi 0:098463de4c5d 2556 return HAL_OK;
group-onsemi 0:098463de4c5d 2557 }
group-onsemi 0:098463de4c5d 2558
group-onsemi 0:098463de4c5d 2559 /**
group-onsemi 0:098463de4c5d 2560 * @brief Stops the TIM Encoder Interface in interrupt mode.
group-onsemi 0:098463de4c5d 2561 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2562 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2563 * @param Channel: TIM Channels to be disabled.
group-onsemi 0:098463de4c5d 2564 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 2565 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 2566 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 2567 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
group-onsemi 0:098463de4c5d 2568 * @retval HAL status
group-onsemi 0:098463de4c5d 2569 */
group-onsemi 0:098463de4c5d 2570 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 2571 {
group-onsemi 0:098463de4c5d 2572 /* Check the parameters */
group-onsemi 0:098463de4c5d 2573 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 2574
group-onsemi 0:098463de4c5d 2575 /* Disable the Input Capture channels 1 and 2
group-onsemi 0:098463de4c5d 2576 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
group-onsemi 0:098463de4c5d 2577 if(Channel == TIM_CHANNEL_1)
group-onsemi 0:098463de4c5d 2578 {
group-onsemi 0:098463de4c5d 2579 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 2580
group-onsemi 0:098463de4c5d 2581 /* Disable the capture compare Interrupts 1 */
group-onsemi 0:098463de4c5d 2582 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
group-onsemi 0:098463de4c5d 2583 }
group-onsemi 0:098463de4c5d 2584 else if(Channel == TIM_CHANNEL_2)
group-onsemi 0:098463de4c5d 2585 {
group-onsemi 0:098463de4c5d 2586 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 2587
group-onsemi 0:098463de4c5d 2588 /* Disable the capture compare Interrupts 2 */
group-onsemi 0:098463de4c5d 2589 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
group-onsemi 0:098463de4c5d 2590 }
group-onsemi 0:098463de4c5d 2591 else
group-onsemi 0:098463de4c5d 2592 {
group-onsemi 0:098463de4c5d 2593 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 2594 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 2595
group-onsemi 0:098463de4c5d 2596 /* Disable the capture compare Interrupts 1 and 2 */
group-onsemi 0:098463de4c5d 2597 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
group-onsemi 0:098463de4c5d 2598 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
group-onsemi 0:098463de4c5d 2599 }
group-onsemi 0:098463de4c5d 2600
group-onsemi 0:098463de4c5d 2601 /* Disable the Peripheral */
group-onsemi 0:098463de4c5d 2602 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 2603
group-onsemi 0:098463de4c5d 2604 /* Change the htim state */
group-onsemi 0:098463de4c5d 2605 htim->State = HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 2606
group-onsemi 0:098463de4c5d 2607 /* Return function status */
group-onsemi 0:098463de4c5d 2608 return HAL_OK;
group-onsemi 0:098463de4c5d 2609 }
group-onsemi 0:098463de4c5d 2610
group-onsemi 0:098463de4c5d 2611 /**
group-onsemi 0:098463de4c5d 2612 * @brief Starts the TIM Encoder Interface in DMA mode.
group-onsemi 0:098463de4c5d 2613 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2614 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2615 * @param Channel: TIM Channels to be enabled.
group-onsemi 0:098463de4c5d 2616 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 2617 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 2618 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 2619 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
group-onsemi 0:098463de4c5d 2620 * @param pData1: The destination Buffer address for IC1.
group-onsemi 0:098463de4c5d 2621 * @param pData2: The destination Buffer address for IC2.
group-onsemi 0:098463de4c5d 2622 * @param Length: The length of data to be transferred from TIM peripheral to memory.
group-onsemi 0:098463de4c5d 2623 * @retval HAL status
group-onsemi 0:098463de4c5d 2624 */
group-onsemi 0:098463de4c5d 2625 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
group-onsemi 0:098463de4c5d 2626 {
group-onsemi 0:098463de4c5d 2627 /* Check the parameters */
group-onsemi 0:098463de4c5d 2628 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 2629
group-onsemi 0:098463de4c5d 2630 if((htim->State == HAL_TIM_STATE_BUSY))
group-onsemi 0:098463de4c5d 2631 {
group-onsemi 0:098463de4c5d 2632 return HAL_BUSY;
group-onsemi 0:098463de4c5d 2633 }
group-onsemi 0:098463de4c5d 2634 else if((htim->State == HAL_TIM_STATE_READY))
group-onsemi 0:098463de4c5d 2635 {
group-onsemi 0:098463de4c5d 2636 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
group-onsemi 0:098463de4c5d 2637 {
group-onsemi 0:098463de4c5d 2638 return HAL_ERROR;
group-onsemi 0:098463de4c5d 2639 }
group-onsemi 0:098463de4c5d 2640 else
group-onsemi 0:098463de4c5d 2641 {
group-onsemi 0:098463de4c5d 2642 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 2643 }
group-onsemi 0:098463de4c5d 2644 }
group-onsemi 0:098463de4c5d 2645
group-onsemi 0:098463de4c5d 2646 switch (Channel)
group-onsemi 0:098463de4c5d 2647 {
group-onsemi 0:098463de4c5d 2648 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 2649 {
group-onsemi 0:098463de4c5d 2650 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 2651 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
group-onsemi 0:098463de4c5d 2652
group-onsemi 0:098463de4c5d 2653 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 2654 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 2655
group-onsemi 0:098463de4c5d 2656 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 2657 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
group-onsemi 0:098463de4c5d 2658
group-onsemi 0:098463de4c5d 2659 /* Enable the TIM Input Capture DMA request */
group-onsemi 0:098463de4c5d 2660 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
group-onsemi 0:098463de4c5d 2661
group-onsemi 0:098463de4c5d 2662 /* Enable the Peripheral */
group-onsemi 0:098463de4c5d 2663 __HAL_TIM_ENABLE(htim);
group-onsemi 0:098463de4c5d 2664
group-onsemi 0:098463de4c5d 2665 /* Enable the Capture compare channel */
group-onsemi 0:098463de4c5d 2666 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 2667 }
group-onsemi 0:098463de4c5d 2668 break;
group-onsemi 0:098463de4c5d 2669
group-onsemi 0:098463de4c5d 2670 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 2671 {
group-onsemi 0:098463de4c5d 2672 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 2673 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
group-onsemi 0:098463de4c5d 2674
group-onsemi 0:098463de4c5d 2675 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 2676 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
group-onsemi 0:098463de4c5d 2677 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 2678 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
group-onsemi 0:098463de4c5d 2679
group-onsemi 0:098463de4c5d 2680 /* Enable the TIM Input Capture DMA request */
group-onsemi 0:098463de4c5d 2681 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
group-onsemi 0:098463de4c5d 2682
group-onsemi 0:098463de4c5d 2683 /* Enable the Peripheral */
group-onsemi 0:098463de4c5d 2684 __HAL_TIM_ENABLE(htim);
group-onsemi 0:098463de4c5d 2685
group-onsemi 0:098463de4c5d 2686 /* Enable the Capture compare channel */
group-onsemi 0:098463de4c5d 2687 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 2688 }
group-onsemi 0:098463de4c5d 2689 break;
group-onsemi 0:098463de4c5d 2690
group-onsemi 0:098463de4c5d 2691 case TIM_CHANNEL_ALL:
group-onsemi 0:098463de4c5d 2692 {
group-onsemi 0:098463de4c5d 2693 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 2694 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
group-onsemi 0:098463de4c5d 2695
group-onsemi 0:098463de4c5d 2696 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 2697 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 2698
group-onsemi 0:098463de4c5d 2699 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 2700 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
group-onsemi 0:098463de4c5d 2701
group-onsemi 0:098463de4c5d 2702 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 2703 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
group-onsemi 0:098463de4c5d 2704
group-onsemi 0:098463de4c5d 2705 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 2706 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 2707
group-onsemi 0:098463de4c5d 2708 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 2709 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
group-onsemi 0:098463de4c5d 2710
group-onsemi 0:098463de4c5d 2711 /* Enable the Peripheral */
group-onsemi 0:098463de4c5d 2712 __HAL_TIM_ENABLE(htim);
group-onsemi 0:098463de4c5d 2713
group-onsemi 0:098463de4c5d 2714 /* Enable the Capture compare channel */
group-onsemi 0:098463de4c5d 2715 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 2716 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
group-onsemi 0:098463de4c5d 2717
group-onsemi 0:098463de4c5d 2718 /* Enable the TIM Input Capture DMA request */
group-onsemi 0:098463de4c5d 2719 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
group-onsemi 0:098463de4c5d 2720 /* Enable the TIM Input Capture DMA request */
group-onsemi 0:098463de4c5d 2721 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
group-onsemi 0:098463de4c5d 2722 }
group-onsemi 0:098463de4c5d 2723 break;
group-onsemi 0:098463de4c5d 2724
group-onsemi 0:098463de4c5d 2725 default:
group-onsemi 0:098463de4c5d 2726 break;
group-onsemi 0:098463de4c5d 2727 }
group-onsemi 0:098463de4c5d 2728 /* Return function status */
group-onsemi 0:098463de4c5d 2729 return HAL_OK;
group-onsemi 0:098463de4c5d 2730 }
group-onsemi 0:098463de4c5d 2731
group-onsemi 0:098463de4c5d 2732 /**
group-onsemi 0:098463de4c5d 2733 * @brief Stops the TIM Encoder Interface in DMA mode.
group-onsemi 0:098463de4c5d 2734 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2735 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2736 * @param Channel: TIM Channels to be enabled.
group-onsemi 0:098463de4c5d 2737 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 2738 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 2739 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 2740 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
group-onsemi 0:098463de4c5d 2741 * @retval HAL status
group-onsemi 0:098463de4c5d 2742 */
group-onsemi 0:098463de4c5d 2743 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 2744 {
group-onsemi 0:098463de4c5d 2745 /* Check the parameters */
group-onsemi 0:098463de4c5d 2746 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 2747
group-onsemi 0:098463de4c5d 2748 /* Disable the Input Capture channels 1 and 2
group-onsemi 0:098463de4c5d 2749 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
group-onsemi 0:098463de4c5d 2750 if(Channel == TIM_CHANNEL_1)
group-onsemi 0:098463de4c5d 2751 {
group-onsemi 0:098463de4c5d 2752 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 2753
group-onsemi 0:098463de4c5d 2754 /* Disable the capture compare DMA Request 1 */
group-onsemi 0:098463de4c5d 2755 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
group-onsemi 0:098463de4c5d 2756 }
group-onsemi 0:098463de4c5d 2757 else if(Channel == TIM_CHANNEL_2)
group-onsemi 0:098463de4c5d 2758 {
group-onsemi 0:098463de4c5d 2759 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 2760
group-onsemi 0:098463de4c5d 2761 /* Disable the capture compare DMA Request 2 */
group-onsemi 0:098463de4c5d 2762 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
group-onsemi 0:098463de4c5d 2763 }
group-onsemi 0:098463de4c5d 2764 else
group-onsemi 0:098463de4c5d 2765 {
group-onsemi 0:098463de4c5d 2766 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 2767 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
group-onsemi 0:098463de4c5d 2768
group-onsemi 0:098463de4c5d 2769 /* Disable the capture compare DMA Request 1 and 2 */
group-onsemi 0:098463de4c5d 2770 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
group-onsemi 0:098463de4c5d 2771 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
group-onsemi 0:098463de4c5d 2772 }
group-onsemi 0:098463de4c5d 2773
group-onsemi 0:098463de4c5d 2774 /* Disable the Peripheral */
group-onsemi 0:098463de4c5d 2775 __HAL_TIM_DISABLE(htim);
group-onsemi 0:098463de4c5d 2776
group-onsemi 0:098463de4c5d 2777 /* Change the htim state */
group-onsemi 0:098463de4c5d 2778 htim->State = HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 2779
group-onsemi 0:098463de4c5d 2780 /* Return function status */
group-onsemi 0:098463de4c5d 2781 return HAL_OK;
group-onsemi 0:098463de4c5d 2782 }
group-onsemi 0:098463de4c5d 2783
group-onsemi 0:098463de4c5d 2784 /**
group-onsemi 0:098463de4c5d 2785 * @}
group-onsemi 0:098463de4c5d 2786 */
group-onsemi 0:098463de4c5d 2787 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
group-onsemi 0:098463de4c5d 2788 * @brief IRQ handler management
group-onsemi 0:098463de4c5d 2789 *
group-onsemi 0:098463de4c5d 2790 @verbatim
group-onsemi 0:098463de4c5d 2791 ==============================================================================
group-onsemi 0:098463de4c5d 2792 ##### IRQ handler management #####
group-onsemi 0:098463de4c5d 2793 ==============================================================================
group-onsemi 0:098463de4c5d 2794 [..]
group-onsemi 0:098463de4c5d 2795 This section provides Timer IRQ handler function.
group-onsemi 0:098463de4c5d 2796
group-onsemi 0:098463de4c5d 2797 @endverbatim
group-onsemi 0:098463de4c5d 2798 * @{
group-onsemi 0:098463de4c5d 2799 */
group-onsemi 0:098463de4c5d 2800 /**
group-onsemi 0:098463de4c5d 2801 * @brief This function handles TIM interrupts requests.
group-onsemi 0:098463de4c5d 2802 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2803 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2804 * @retval None
group-onsemi 0:098463de4c5d 2805 */
group-onsemi 0:098463de4c5d 2806 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 2807 {
group-onsemi 0:098463de4c5d 2808 /* Capture compare 1 event */
group-onsemi 0:098463de4c5d 2809 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
group-onsemi 0:098463de4c5d 2810 {
group-onsemi 0:098463de4c5d 2811 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
group-onsemi 0:098463de4c5d 2812 {
group-onsemi 0:098463de4c5d 2813 {
group-onsemi 0:098463de4c5d 2814 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
group-onsemi 0:098463de4c5d 2815 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
group-onsemi 0:098463de4c5d 2816
group-onsemi 0:098463de4c5d 2817 /* Input capture event */
group-onsemi 0:098463de4c5d 2818 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
group-onsemi 0:098463de4c5d 2819 {
group-onsemi 0:098463de4c5d 2820 HAL_TIM_IC_CaptureCallback(htim);
group-onsemi 0:098463de4c5d 2821 }
group-onsemi 0:098463de4c5d 2822 /* Output compare event */
group-onsemi 0:098463de4c5d 2823 else
group-onsemi 0:098463de4c5d 2824 {
group-onsemi 0:098463de4c5d 2825 HAL_TIM_OC_DelayElapsedCallback(htim);
group-onsemi 0:098463de4c5d 2826 HAL_TIM_PWM_PulseFinishedCallback(htim);
group-onsemi 0:098463de4c5d 2827 }
group-onsemi 0:098463de4c5d 2828 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
group-onsemi 0:098463de4c5d 2829 }
group-onsemi 0:098463de4c5d 2830 }
group-onsemi 0:098463de4c5d 2831 }
group-onsemi 0:098463de4c5d 2832 /* Capture compare 2 event */
group-onsemi 0:098463de4c5d 2833 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
group-onsemi 0:098463de4c5d 2834 {
group-onsemi 0:098463de4c5d 2835 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
group-onsemi 0:098463de4c5d 2836 {
group-onsemi 0:098463de4c5d 2837 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
group-onsemi 0:098463de4c5d 2838 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
group-onsemi 0:098463de4c5d 2839 /* Input capture event */
group-onsemi 0:098463de4c5d 2840 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
group-onsemi 0:098463de4c5d 2841 {
group-onsemi 0:098463de4c5d 2842 HAL_TIM_IC_CaptureCallback(htim);
group-onsemi 0:098463de4c5d 2843 }
group-onsemi 0:098463de4c5d 2844 /* Output compare event */
group-onsemi 0:098463de4c5d 2845 else
group-onsemi 0:098463de4c5d 2846 {
group-onsemi 0:098463de4c5d 2847 HAL_TIM_OC_DelayElapsedCallback(htim);
group-onsemi 0:098463de4c5d 2848 HAL_TIM_PWM_PulseFinishedCallback(htim);
group-onsemi 0:098463de4c5d 2849 }
group-onsemi 0:098463de4c5d 2850 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
group-onsemi 0:098463de4c5d 2851 }
group-onsemi 0:098463de4c5d 2852 }
group-onsemi 0:098463de4c5d 2853 /* Capture compare 3 event */
group-onsemi 0:098463de4c5d 2854 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
group-onsemi 0:098463de4c5d 2855 {
group-onsemi 0:098463de4c5d 2856 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
group-onsemi 0:098463de4c5d 2857 {
group-onsemi 0:098463de4c5d 2858 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
group-onsemi 0:098463de4c5d 2859 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
group-onsemi 0:098463de4c5d 2860 /* Input capture event */
group-onsemi 0:098463de4c5d 2861 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
group-onsemi 0:098463de4c5d 2862 {
group-onsemi 0:098463de4c5d 2863 HAL_TIM_IC_CaptureCallback(htim);
group-onsemi 0:098463de4c5d 2864 }
group-onsemi 0:098463de4c5d 2865 /* Output compare event */
group-onsemi 0:098463de4c5d 2866 else
group-onsemi 0:098463de4c5d 2867 {
group-onsemi 0:098463de4c5d 2868 HAL_TIM_OC_DelayElapsedCallback(htim);
group-onsemi 0:098463de4c5d 2869 HAL_TIM_PWM_PulseFinishedCallback(htim);
group-onsemi 0:098463de4c5d 2870 }
group-onsemi 0:098463de4c5d 2871 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
group-onsemi 0:098463de4c5d 2872 }
group-onsemi 0:098463de4c5d 2873 }
group-onsemi 0:098463de4c5d 2874 /* Capture compare 4 event */
group-onsemi 0:098463de4c5d 2875 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
group-onsemi 0:098463de4c5d 2876 {
group-onsemi 0:098463de4c5d 2877 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
group-onsemi 0:098463de4c5d 2878 {
group-onsemi 0:098463de4c5d 2879 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
group-onsemi 0:098463de4c5d 2880 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
group-onsemi 0:098463de4c5d 2881 /* Input capture event */
group-onsemi 0:098463de4c5d 2882 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
group-onsemi 0:098463de4c5d 2883 {
group-onsemi 0:098463de4c5d 2884 HAL_TIM_IC_CaptureCallback(htim);
group-onsemi 0:098463de4c5d 2885 }
group-onsemi 0:098463de4c5d 2886 /* Output compare event */
group-onsemi 0:098463de4c5d 2887 else
group-onsemi 0:098463de4c5d 2888 {
group-onsemi 0:098463de4c5d 2889 HAL_TIM_OC_DelayElapsedCallback(htim);
group-onsemi 0:098463de4c5d 2890 HAL_TIM_PWM_PulseFinishedCallback(htim);
group-onsemi 0:098463de4c5d 2891 }
group-onsemi 0:098463de4c5d 2892 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
group-onsemi 0:098463de4c5d 2893 }
group-onsemi 0:098463de4c5d 2894 }
group-onsemi 0:098463de4c5d 2895 /* TIM Update event */
group-onsemi 0:098463de4c5d 2896 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
group-onsemi 0:098463de4c5d 2897 {
group-onsemi 0:098463de4c5d 2898 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
group-onsemi 0:098463de4c5d 2899 {
group-onsemi 0:098463de4c5d 2900 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
group-onsemi 0:098463de4c5d 2901 HAL_TIM_PeriodElapsedCallback(htim);
group-onsemi 0:098463de4c5d 2902 }
group-onsemi 0:098463de4c5d 2903 }
group-onsemi 0:098463de4c5d 2904 /* TIM Break input event */
group-onsemi 0:098463de4c5d 2905 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
group-onsemi 0:098463de4c5d 2906 {
group-onsemi 0:098463de4c5d 2907 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
group-onsemi 0:098463de4c5d 2908 {
group-onsemi 0:098463de4c5d 2909 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
group-onsemi 0:098463de4c5d 2910 HAL_TIMEx_BreakCallback(htim);
group-onsemi 0:098463de4c5d 2911 }
group-onsemi 0:098463de4c5d 2912 }
group-onsemi 0:098463de4c5d 2913
group-onsemi 0:098463de4c5d 2914 /* TIM Break input event */
group-onsemi 0:098463de4c5d 2915 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
group-onsemi 0:098463de4c5d 2916 {
group-onsemi 0:098463de4c5d 2917 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
group-onsemi 0:098463de4c5d 2918 {
group-onsemi 0:098463de4c5d 2919 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
group-onsemi 0:098463de4c5d 2920 HAL_TIMEx_BreakCallback(htim);
group-onsemi 0:098463de4c5d 2921 }
group-onsemi 0:098463de4c5d 2922 }
group-onsemi 0:098463de4c5d 2923
group-onsemi 0:098463de4c5d 2924 /* TIM Trigger detection event */
group-onsemi 0:098463de4c5d 2925 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
group-onsemi 0:098463de4c5d 2926 {
group-onsemi 0:098463de4c5d 2927 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
group-onsemi 0:098463de4c5d 2928 {
group-onsemi 0:098463de4c5d 2929 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
group-onsemi 0:098463de4c5d 2930 HAL_TIM_TriggerCallback(htim);
group-onsemi 0:098463de4c5d 2931 }
group-onsemi 0:098463de4c5d 2932 }
group-onsemi 0:098463de4c5d 2933 /* TIM commutation event */
group-onsemi 0:098463de4c5d 2934 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
group-onsemi 0:098463de4c5d 2935 {
group-onsemi 0:098463de4c5d 2936 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
group-onsemi 0:098463de4c5d 2937 {
group-onsemi 0:098463de4c5d 2938 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
group-onsemi 0:098463de4c5d 2939 HAL_TIMEx_CommutationCallback(htim);
group-onsemi 0:098463de4c5d 2940 }
group-onsemi 0:098463de4c5d 2941 }
group-onsemi 0:098463de4c5d 2942 }
group-onsemi 0:098463de4c5d 2943
group-onsemi 0:098463de4c5d 2944 /**
group-onsemi 0:098463de4c5d 2945 * @}
group-onsemi 0:098463de4c5d 2946 */
group-onsemi 0:098463de4c5d 2947
group-onsemi 0:098463de4c5d 2948 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
group-onsemi 0:098463de4c5d 2949 * @brief Peripheral Control functions
group-onsemi 0:098463de4c5d 2950 *
group-onsemi 0:098463de4c5d 2951 @verbatim
group-onsemi 0:098463de4c5d 2952 ==============================================================================
group-onsemi 0:098463de4c5d 2953 ##### Peripheral Control functions #####
group-onsemi 0:098463de4c5d 2954 ==============================================================================
group-onsemi 0:098463de4c5d 2955 [..]
group-onsemi 0:098463de4c5d 2956 This section provides functions allowing to:
group-onsemi 0:098463de4c5d 2957 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
group-onsemi 0:098463de4c5d 2958 (+) Configure External Clock source.
group-onsemi 0:098463de4c5d 2959 (+) Configure Complementary channels, break features and dead time.
group-onsemi 0:098463de4c5d 2960 (+) Configure Master and the Slave synchronization.
group-onsemi 0:098463de4c5d 2961 (+) Configure the DMA Burst Mode.
group-onsemi 0:098463de4c5d 2962
group-onsemi 0:098463de4c5d 2963 @endverbatim
group-onsemi 0:098463de4c5d 2964 * @{
group-onsemi 0:098463de4c5d 2965 */
group-onsemi 0:098463de4c5d 2966
group-onsemi 0:098463de4c5d 2967 /**
group-onsemi 0:098463de4c5d 2968 * @brief Initializes the TIM Output Compare Channels according to the specified
group-onsemi 0:098463de4c5d 2969 * parameters in the TIM_OC_InitTypeDef.
group-onsemi 0:098463de4c5d 2970 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 2971 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 2972 * @param sConfig: TIM Output Compare configuration structure
group-onsemi 0:098463de4c5d 2973 * @param Channel: TIM Channels to be enabled.
group-onsemi 0:098463de4c5d 2974 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 2975 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 2976 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 2977 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 2978 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 2979 * @retval HAL status
group-onsemi 0:098463de4c5d 2980 */
group-onsemi 0:098463de4c5d 2981 __weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
group-onsemi 0:098463de4c5d 2982 {
group-onsemi 0:098463de4c5d 2983 /* Check the parameters */
group-onsemi 0:098463de4c5d 2984 assert_param(IS_TIM_CHANNELS(Channel));
group-onsemi 0:098463de4c5d 2985 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
group-onsemi 0:098463de4c5d 2986 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
group-onsemi 0:098463de4c5d 2987
group-onsemi 0:098463de4c5d 2988 /* Check input state */
group-onsemi 0:098463de4c5d 2989 __HAL_LOCK(htim);
group-onsemi 0:098463de4c5d 2990
group-onsemi 0:098463de4c5d 2991 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 2992
group-onsemi 0:098463de4c5d 2993 switch (Channel)
group-onsemi 0:098463de4c5d 2994 {
group-onsemi 0:098463de4c5d 2995 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 2996 {
group-onsemi 0:098463de4c5d 2997 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 2998 /* Configure the TIM Channel 1 in Output Compare */
group-onsemi 0:098463de4c5d 2999 TIM_OC1_SetConfig(htim->Instance, sConfig);
group-onsemi 0:098463de4c5d 3000 }
group-onsemi 0:098463de4c5d 3001 break;
group-onsemi 0:098463de4c5d 3002
group-onsemi 0:098463de4c5d 3003 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 3004 {
group-onsemi 0:098463de4c5d 3005 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3006 /* Configure the TIM Channel 2 in Output Compare */
group-onsemi 0:098463de4c5d 3007 TIM_OC2_SetConfig(htim->Instance, sConfig);
group-onsemi 0:098463de4c5d 3008 }
group-onsemi 0:098463de4c5d 3009 break;
group-onsemi 0:098463de4c5d 3010
group-onsemi 0:098463de4c5d 3011 case TIM_CHANNEL_3:
group-onsemi 0:098463de4c5d 3012 {
group-onsemi 0:098463de4c5d 3013 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3014 /* Configure the TIM Channel 3 in Output Compare */
group-onsemi 0:098463de4c5d 3015 TIM_OC3_SetConfig(htim->Instance, sConfig);
group-onsemi 0:098463de4c5d 3016 }
group-onsemi 0:098463de4c5d 3017 break;
group-onsemi 0:098463de4c5d 3018
group-onsemi 0:098463de4c5d 3019 case TIM_CHANNEL_4:
group-onsemi 0:098463de4c5d 3020 {
group-onsemi 0:098463de4c5d 3021 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3022 /* Configure the TIM Channel 4 in Output Compare */
group-onsemi 0:098463de4c5d 3023 TIM_OC4_SetConfig(htim->Instance, sConfig);
group-onsemi 0:098463de4c5d 3024 }
group-onsemi 0:098463de4c5d 3025 break;
group-onsemi 0:098463de4c5d 3026
group-onsemi 0:098463de4c5d 3027 default:
group-onsemi 0:098463de4c5d 3028 break;
group-onsemi 0:098463de4c5d 3029 }
group-onsemi 0:098463de4c5d 3030 htim->State = HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 3031
group-onsemi 0:098463de4c5d 3032 __HAL_UNLOCK(htim);
group-onsemi 0:098463de4c5d 3033
group-onsemi 0:098463de4c5d 3034 return HAL_OK;
group-onsemi 0:098463de4c5d 3035 }
group-onsemi 0:098463de4c5d 3036
group-onsemi 0:098463de4c5d 3037 /**
group-onsemi 0:098463de4c5d 3038 * @brief Initializes the TIM Input Capture Channels according to the specified
group-onsemi 0:098463de4c5d 3039 * parameters in the TIM_IC_InitTypeDef.
group-onsemi 0:098463de4c5d 3040 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 3041 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 3042 * @param sConfig: TIM Input Capture configuration structure
group-onsemi 0:098463de4c5d 3043 * @param Channel: TIM Channels to be enabled.
group-onsemi 0:098463de4c5d 3044 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 3045 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 3046 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 3047 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 3048 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 3049 * @retval HAL status
group-onsemi 0:098463de4c5d 3050 */
group-onsemi 0:098463de4c5d 3051 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
group-onsemi 0:098463de4c5d 3052 {
group-onsemi 0:098463de4c5d 3053 /* Check the parameters */
group-onsemi 0:098463de4c5d 3054 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3055 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
group-onsemi 0:098463de4c5d 3056 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
group-onsemi 0:098463de4c5d 3057 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
group-onsemi 0:098463de4c5d 3058 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
group-onsemi 0:098463de4c5d 3059
group-onsemi 0:098463de4c5d 3060 __HAL_LOCK(htim);
group-onsemi 0:098463de4c5d 3061
group-onsemi 0:098463de4c5d 3062 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 3063
group-onsemi 0:098463de4c5d 3064 if (Channel == TIM_CHANNEL_1)
group-onsemi 0:098463de4c5d 3065 {
group-onsemi 0:098463de4c5d 3066 /* TI1 Configuration */
group-onsemi 0:098463de4c5d 3067 TIM_TI1_SetConfig(htim->Instance,
group-onsemi 0:098463de4c5d 3068 sConfig->ICPolarity,
group-onsemi 0:098463de4c5d 3069 sConfig->ICSelection,
group-onsemi 0:098463de4c5d 3070 sConfig->ICFilter);
group-onsemi 0:098463de4c5d 3071
group-onsemi 0:098463de4c5d 3072 /* Reset the IC1PSC Bits */
group-onsemi 0:098463de4c5d 3073 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
group-onsemi 0:098463de4c5d 3074
group-onsemi 0:098463de4c5d 3075 /* Set the IC1PSC value */
group-onsemi 0:098463de4c5d 3076 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
group-onsemi 0:098463de4c5d 3077 }
group-onsemi 0:098463de4c5d 3078 else if (Channel == TIM_CHANNEL_2)
group-onsemi 0:098463de4c5d 3079 {
group-onsemi 0:098463de4c5d 3080 /* TI2 Configuration */
group-onsemi 0:098463de4c5d 3081 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3082
group-onsemi 0:098463de4c5d 3083 TIM_TI2_SetConfig(htim->Instance,
group-onsemi 0:098463de4c5d 3084 sConfig->ICPolarity,
group-onsemi 0:098463de4c5d 3085 sConfig->ICSelection,
group-onsemi 0:098463de4c5d 3086 sConfig->ICFilter);
group-onsemi 0:098463de4c5d 3087
group-onsemi 0:098463de4c5d 3088 /* Reset the IC2PSC Bits */
group-onsemi 0:098463de4c5d 3089 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
group-onsemi 0:098463de4c5d 3090
group-onsemi 0:098463de4c5d 3091 /* Set the IC2PSC value */
group-onsemi 0:098463de4c5d 3092 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
group-onsemi 0:098463de4c5d 3093 }
group-onsemi 0:098463de4c5d 3094 else if (Channel == TIM_CHANNEL_3)
group-onsemi 0:098463de4c5d 3095 {
group-onsemi 0:098463de4c5d 3096 /* TI3 Configuration */
group-onsemi 0:098463de4c5d 3097 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3098
group-onsemi 0:098463de4c5d 3099 TIM_TI3_SetConfig(htim->Instance,
group-onsemi 0:098463de4c5d 3100 sConfig->ICPolarity,
group-onsemi 0:098463de4c5d 3101 sConfig->ICSelection,
group-onsemi 0:098463de4c5d 3102 sConfig->ICFilter);
group-onsemi 0:098463de4c5d 3103
group-onsemi 0:098463de4c5d 3104 /* Reset the IC3PSC Bits */
group-onsemi 0:098463de4c5d 3105 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
group-onsemi 0:098463de4c5d 3106
group-onsemi 0:098463de4c5d 3107 /* Set the IC3PSC value */
group-onsemi 0:098463de4c5d 3108 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
group-onsemi 0:098463de4c5d 3109 }
group-onsemi 0:098463de4c5d 3110 else
group-onsemi 0:098463de4c5d 3111 {
group-onsemi 0:098463de4c5d 3112 /* TI4 Configuration */
group-onsemi 0:098463de4c5d 3113 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3114
group-onsemi 0:098463de4c5d 3115 TIM_TI4_SetConfig(htim->Instance,
group-onsemi 0:098463de4c5d 3116 sConfig->ICPolarity,
group-onsemi 0:098463de4c5d 3117 sConfig->ICSelection,
group-onsemi 0:098463de4c5d 3118 sConfig->ICFilter);
group-onsemi 0:098463de4c5d 3119
group-onsemi 0:098463de4c5d 3120 /* Reset the IC4PSC Bits */
group-onsemi 0:098463de4c5d 3121 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
group-onsemi 0:098463de4c5d 3122
group-onsemi 0:098463de4c5d 3123 /* Set the IC4PSC value */
group-onsemi 0:098463de4c5d 3124 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
group-onsemi 0:098463de4c5d 3125 }
group-onsemi 0:098463de4c5d 3126
group-onsemi 0:098463de4c5d 3127 htim->State = HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 3128
group-onsemi 0:098463de4c5d 3129 __HAL_UNLOCK(htim);
group-onsemi 0:098463de4c5d 3130
group-onsemi 0:098463de4c5d 3131 return HAL_OK;
group-onsemi 0:098463de4c5d 3132 }
group-onsemi 0:098463de4c5d 3133
group-onsemi 0:098463de4c5d 3134 /**
group-onsemi 0:098463de4c5d 3135 * @brief Initializes the TIM PWM channels according to the specified
group-onsemi 0:098463de4c5d 3136 * parameters in the TIM_OC_InitTypeDef.
group-onsemi 0:098463de4c5d 3137 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 3138 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 3139 * @param sConfig: TIM PWM configuration structure
group-onsemi 0:098463de4c5d 3140 * @param Channel: TIM Channels to be enabled.
group-onsemi 0:098463de4c5d 3141 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 3142 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 3143 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 3144 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 3145 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 3146 * @retval HAL status
group-onsemi 0:098463de4c5d 3147 */
group-onsemi 0:098463de4c5d 3148 __weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
group-onsemi 0:098463de4c5d 3149 {
group-onsemi 0:098463de4c5d 3150 __HAL_LOCK(htim);
group-onsemi 0:098463de4c5d 3151
group-onsemi 0:098463de4c5d 3152 /* Check the parameters */
group-onsemi 0:098463de4c5d 3153 assert_param(IS_TIM_CHANNELS(Channel));
group-onsemi 0:098463de4c5d 3154 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
group-onsemi 0:098463de4c5d 3155 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
group-onsemi 0:098463de4c5d 3156 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
group-onsemi 0:098463de4c5d 3157
group-onsemi 0:098463de4c5d 3158 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 3159
group-onsemi 0:098463de4c5d 3160 switch (Channel)
group-onsemi 0:098463de4c5d 3161 {
group-onsemi 0:098463de4c5d 3162 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 3163 {
group-onsemi 0:098463de4c5d 3164 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3165 /* Configure the Channel 1 in PWM mode */
group-onsemi 0:098463de4c5d 3166 TIM_OC1_SetConfig(htim->Instance, sConfig);
group-onsemi 0:098463de4c5d 3167
group-onsemi 0:098463de4c5d 3168 /* Set the Preload enable bit for channel1 */
group-onsemi 0:098463de4c5d 3169 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
group-onsemi 0:098463de4c5d 3170
group-onsemi 0:098463de4c5d 3171 /* Configure the Output Fast mode */
group-onsemi 0:098463de4c5d 3172 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
group-onsemi 0:098463de4c5d 3173 htim->Instance->CCMR1 |= sConfig->OCFastMode;
group-onsemi 0:098463de4c5d 3174 }
group-onsemi 0:098463de4c5d 3175 break;
group-onsemi 0:098463de4c5d 3176
group-onsemi 0:098463de4c5d 3177 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 3178 {
group-onsemi 0:098463de4c5d 3179 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3180 /* Configure the Channel 2 in PWM mode */
group-onsemi 0:098463de4c5d 3181 TIM_OC2_SetConfig(htim->Instance, sConfig);
group-onsemi 0:098463de4c5d 3182
group-onsemi 0:098463de4c5d 3183 /* Set the Preload enable bit for channel2 */
group-onsemi 0:098463de4c5d 3184 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
group-onsemi 0:098463de4c5d 3185
group-onsemi 0:098463de4c5d 3186 /* Configure the Output Fast mode */
group-onsemi 0:098463de4c5d 3187 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
group-onsemi 0:098463de4c5d 3188 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
group-onsemi 0:098463de4c5d 3189 }
group-onsemi 0:098463de4c5d 3190 break;
group-onsemi 0:098463de4c5d 3191
group-onsemi 0:098463de4c5d 3192 case TIM_CHANNEL_3:
group-onsemi 0:098463de4c5d 3193 {
group-onsemi 0:098463de4c5d 3194 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3195 /* Configure the Channel 3 in PWM mode */
group-onsemi 0:098463de4c5d 3196 TIM_OC3_SetConfig(htim->Instance, sConfig);
group-onsemi 0:098463de4c5d 3197
group-onsemi 0:098463de4c5d 3198 /* Set the Preload enable bit for channel3 */
group-onsemi 0:098463de4c5d 3199 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
group-onsemi 0:098463de4c5d 3200
group-onsemi 0:098463de4c5d 3201 /* Configure the Output Fast mode */
group-onsemi 0:098463de4c5d 3202 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
group-onsemi 0:098463de4c5d 3203 htim->Instance->CCMR2 |= sConfig->OCFastMode;
group-onsemi 0:098463de4c5d 3204 }
group-onsemi 0:098463de4c5d 3205 break;
group-onsemi 0:098463de4c5d 3206
group-onsemi 0:098463de4c5d 3207 case TIM_CHANNEL_4:
group-onsemi 0:098463de4c5d 3208 {
group-onsemi 0:098463de4c5d 3209 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3210 /* Configure the Channel 4 in PWM mode */
group-onsemi 0:098463de4c5d 3211 TIM_OC4_SetConfig(htim->Instance, sConfig);
group-onsemi 0:098463de4c5d 3212
group-onsemi 0:098463de4c5d 3213 /* Set the Preload enable bit for channel4 */
group-onsemi 0:098463de4c5d 3214 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
group-onsemi 0:098463de4c5d 3215
group-onsemi 0:098463de4c5d 3216 /* Configure the Output Fast mode */
group-onsemi 0:098463de4c5d 3217 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
group-onsemi 0:098463de4c5d 3218 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
group-onsemi 0:098463de4c5d 3219 }
group-onsemi 0:098463de4c5d 3220 break;
group-onsemi 0:098463de4c5d 3221
group-onsemi 0:098463de4c5d 3222 default:
group-onsemi 0:098463de4c5d 3223 break;
group-onsemi 0:098463de4c5d 3224 }
group-onsemi 0:098463de4c5d 3225
group-onsemi 0:098463de4c5d 3226 htim->State = HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 3227
group-onsemi 0:098463de4c5d 3228 __HAL_UNLOCK(htim);
group-onsemi 0:098463de4c5d 3229
group-onsemi 0:098463de4c5d 3230 return HAL_OK;
group-onsemi 0:098463de4c5d 3231 }
group-onsemi 0:098463de4c5d 3232
group-onsemi 0:098463de4c5d 3233 /**
group-onsemi 0:098463de4c5d 3234 * @brief Initializes the TIM One Pulse Channels according to the specified
group-onsemi 0:098463de4c5d 3235 * parameters in the TIM_OnePulse_InitTypeDef.
group-onsemi 0:098463de4c5d 3236 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 3237 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 3238 * @param sConfig: TIM One Pulse configuration structure
group-onsemi 0:098463de4c5d 3239 * @param OutputChannel: TIM Channels to be enabled.
group-onsemi 0:098463de4c5d 3240 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 3241 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 3242 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 3243 * @param InputChannel: TIM Channels to be enabled.
group-onsemi 0:098463de4c5d 3244 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 3245 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 3246 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 3247 * @retval HAL status
group-onsemi 0:098463de4c5d 3248 */
group-onsemi 0:098463de4c5d 3249 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
group-onsemi 0:098463de4c5d 3250 {
group-onsemi 0:098463de4c5d 3251 TIM_OC_InitTypeDef temp1;
group-onsemi 0:098463de4c5d 3252
group-onsemi 0:098463de4c5d 3253 /* Check the parameters */
group-onsemi 0:098463de4c5d 3254 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
group-onsemi 0:098463de4c5d 3255 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
group-onsemi 0:098463de4c5d 3256
group-onsemi 0:098463de4c5d 3257 if(OutputChannel != InputChannel)
group-onsemi 0:098463de4c5d 3258 {
group-onsemi 0:098463de4c5d 3259 __HAL_LOCK(htim);
group-onsemi 0:098463de4c5d 3260
group-onsemi 0:098463de4c5d 3261 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 3262
group-onsemi 0:098463de4c5d 3263 /* Extract the Output compare configuration from sConfig structure */
group-onsemi 0:098463de4c5d 3264 temp1.OCMode = sConfig->OCMode;
group-onsemi 0:098463de4c5d 3265 temp1.Pulse = sConfig->Pulse;
group-onsemi 0:098463de4c5d 3266 temp1.OCPolarity = sConfig->OCPolarity;
group-onsemi 0:098463de4c5d 3267 temp1.OCNPolarity = sConfig->OCNPolarity;
group-onsemi 0:098463de4c5d 3268 temp1.OCIdleState = sConfig->OCIdleState;
group-onsemi 0:098463de4c5d 3269 temp1.OCNIdleState = sConfig->OCNIdleState;
group-onsemi 0:098463de4c5d 3270
group-onsemi 0:098463de4c5d 3271 switch (OutputChannel)
group-onsemi 0:098463de4c5d 3272 {
group-onsemi 0:098463de4c5d 3273 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 3274 {
group-onsemi 0:098463de4c5d 3275 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3276
group-onsemi 0:098463de4c5d 3277 TIM_OC1_SetConfig(htim->Instance, &temp1);
group-onsemi 0:098463de4c5d 3278 }
group-onsemi 0:098463de4c5d 3279 break;
group-onsemi 0:098463de4c5d 3280 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 3281 {
group-onsemi 0:098463de4c5d 3282 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3283
group-onsemi 0:098463de4c5d 3284 TIM_OC2_SetConfig(htim->Instance, &temp1);
group-onsemi 0:098463de4c5d 3285 }
group-onsemi 0:098463de4c5d 3286 break;
group-onsemi 0:098463de4c5d 3287 default:
group-onsemi 0:098463de4c5d 3288 break;
group-onsemi 0:098463de4c5d 3289 }
group-onsemi 0:098463de4c5d 3290 switch (InputChannel)
group-onsemi 0:098463de4c5d 3291 {
group-onsemi 0:098463de4c5d 3292 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 3293 {
group-onsemi 0:098463de4c5d 3294 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3295
group-onsemi 0:098463de4c5d 3296 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
group-onsemi 0:098463de4c5d 3297 sConfig->ICSelection, sConfig->ICFilter);
group-onsemi 0:098463de4c5d 3298
group-onsemi 0:098463de4c5d 3299 /* Reset the IC1PSC Bits */
group-onsemi 0:098463de4c5d 3300 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
group-onsemi 0:098463de4c5d 3301
group-onsemi 0:098463de4c5d 3302 /* Select the Trigger source */
group-onsemi 0:098463de4c5d 3303 htim->Instance->SMCR &= ~TIM_SMCR_TS;
group-onsemi 0:098463de4c5d 3304 htim->Instance->SMCR |= TIM_TS_TI1FP1;
group-onsemi 0:098463de4c5d 3305
group-onsemi 0:098463de4c5d 3306 /* Select the Slave Mode */
group-onsemi 0:098463de4c5d 3307 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
group-onsemi 0:098463de4c5d 3308 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
group-onsemi 0:098463de4c5d 3309 }
group-onsemi 0:098463de4c5d 3310 break;
group-onsemi 0:098463de4c5d 3311 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 3312 {
group-onsemi 0:098463de4c5d 3313 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3314
group-onsemi 0:098463de4c5d 3315 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
group-onsemi 0:098463de4c5d 3316 sConfig->ICSelection, sConfig->ICFilter);
group-onsemi 0:098463de4c5d 3317
group-onsemi 0:098463de4c5d 3318 /* Reset the IC2PSC Bits */
group-onsemi 0:098463de4c5d 3319 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
group-onsemi 0:098463de4c5d 3320
group-onsemi 0:098463de4c5d 3321 /* Select the Trigger source */
group-onsemi 0:098463de4c5d 3322 htim->Instance->SMCR &= ~TIM_SMCR_TS;
group-onsemi 0:098463de4c5d 3323 htim->Instance->SMCR |= TIM_TS_TI2FP2;
group-onsemi 0:098463de4c5d 3324
group-onsemi 0:098463de4c5d 3325 /* Select the Slave Mode */
group-onsemi 0:098463de4c5d 3326 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
group-onsemi 0:098463de4c5d 3327 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
group-onsemi 0:098463de4c5d 3328 }
group-onsemi 0:098463de4c5d 3329 break;
group-onsemi 0:098463de4c5d 3330
group-onsemi 0:098463de4c5d 3331 default:
group-onsemi 0:098463de4c5d 3332 break;
group-onsemi 0:098463de4c5d 3333 }
group-onsemi 0:098463de4c5d 3334
group-onsemi 0:098463de4c5d 3335 htim->State = HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 3336
group-onsemi 0:098463de4c5d 3337 __HAL_UNLOCK(htim);
group-onsemi 0:098463de4c5d 3338
group-onsemi 0:098463de4c5d 3339 return HAL_OK;
group-onsemi 0:098463de4c5d 3340 }
group-onsemi 0:098463de4c5d 3341 else
group-onsemi 0:098463de4c5d 3342 {
group-onsemi 0:098463de4c5d 3343 return HAL_ERROR;
group-onsemi 0:098463de4c5d 3344 }
group-onsemi 0:098463de4c5d 3345 }
group-onsemi 0:098463de4c5d 3346
group-onsemi 0:098463de4c5d 3347 /**
group-onsemi 0:098463de4c5d 3348 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
group-onsemi 0:098463de4c5d 3349 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 3350 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 3351 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
group-onsemi 0:098463de4c5d 3352 * This parameters can be on of the following values:
group-onsemi 0:098463de4c5d 3353 * @arg TIM_DMABASE_CR1
group-onsemi 0:098463de4c5d 3354 * @arg TIM_DMABASE_CR2
group-onsemi 0:098463de4c5d 3355 * @arg TIM_DMABASE_SMCR
group-onsemi 0:098463de4c5d 3356 * @arg TIM_DMABASE_DIER
group-onsemi 0:098463de4c5d 3357 * @arg TIM_DMABASE_SR
group-onsemi 0:098463de4c5d 3358 * @arg TIM_DMABASE_EGR
group-onsemi 0:098463de4c5d 3359 * @arg TIM_DMABASE_CCMR1
group-onsemi 0:098463de4c5d 3360 * @arg TIM_DMABASE_CCMR2
group-onsemi 0:098463de4c5d 3361 * @arg TIM_DMABASE_CCER
group-onsemi 0:098463de4c5d 3362 * @arg TIM_DMABASE_CNT
group-onsemi 0:098463de4c5d 3363 * @arg TIM_DMABASE_PSC
group-onsemi 0:098463de4c5d 3364 * @arg TIM_DMABASE_ARR
group-onsemi 0:098463de4c5d 3365 * @arg TIM_DMABASE_RCR
group-onsemi 0:098463de4c5d 3366 * @arg TIM_DMABASE_CCR1
group-onsemi 0:098463de4c5d 3367 * @arg TIM_DMABASE_CCR2
group-onsemi 0:098463de4c5d 3368 * @arg TIM_DMABASE_CCR3
group-onsemi 0:098463de4c5d 3369 * @arg TIM_DMABASE_CCR4
group-onsemi 0:098463de4c5d 3370 * @arg TIM_DMABASE_BDTR
group-onsemi 0:098463de4c5d 3371 * @arg TIM_DMABASE_DCR
group-onsemi 0:098463de4c5d 3372 * @param BurstRequestSrc: TIM DMA Request sources.
group-onsemi 0:098463de4c5d 3373 * This parameters can be on of the following values:
group-onsemi 0:098463de4c5d 3374 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
group-onsemi 0:098463de4c5d 3375 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
group-onsemi 0:098463de4c5d 3376 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
group-onsemi 0:098463de4c5d 3377 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
group-onsemi 0:098463de4c5d 3378 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
group-onsemi 0:098463de4c5d 3379 * @arg TIM_DMA_COM: TIM Commutation DMA source
group-onsemi 0:098463de4c5d 3380 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
group-onsemi 0:098463de4c5d 3381 * @param BurstBuffer: The Buffer address.
group-onsemi 0:098463de4c5d 3382 * @param BurstLength: DMA Burst length. This parameter can be one value
group-onsemi 0:098463de4c5d 3383 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
group-onsemi 0:098463de4c5d 3384 * @retval HAL status
group-onsemi 0:098463de4c5d 3385 */
group-onsemi 0:098463de4c5d 3386 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
group-onsemi 0:098463de4c5d 3387 uint32_t* BurstBuffer, uint32_t BurstLength)
group-onsemi 0:098463de4c5d 3388 {
group-onsemi 0:098463de4c5d 3389 /* Check the parameters */
group-onsemi 0:098463de4c5d 3390 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3391 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
group-onsemi 0:098463de4c5d 3392 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
group-onsemi 0:098463de4c5d 3393 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
group-onsemi 0:098463de4c5d 3394
group-onsemi 0:098463de4c5d 3395 if((htim->State == HAL_TIM_STATE_BUSY))
group-onsemi 0:098463de4c5d 3396 {
group-onsemi 0:098463de4c5d 3397 return HAL_BUSY;
group-onsemi 0:098463de4c5d 3398 }
group-onsemi 0:098463de4c5d 3399 else if((htim->State == HAL_TIM_STATE_READY))
group-onsemi 0:098463de4c5d 3400 {
group-onsemi 0:098463de4c5d 3401 if((BurstBuffer == 0 ) && (BurstLength > 0))
group-onsemi 0:098463de4c5d 3402 {
group-onsemi 0:098463de4c5d 3403 return HAL_ERROR;
group-onsemi 0:098463de4c5d 3404 }
group-onsemi 0:098463de4c5d 3405 else
group-onsemi 0:098463de4c5d 3406 {
group-onsemi 0:098463de4c5d 3407 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 3408 }
group-onsemi 0:098463de4c5d 3409 }
group-onsemi 0:098463de4c5d 3410 switch(BurstRequestSrc)
group-onsemi 0:098463de4c5d 3411 {
group-onsemi 0:098463de4c5d 3412 case TIM_DMA_UPDATE:
group-onsemi 0:098463de4c5d 3413 {
group-onsemi 0:098463de4c5d 3414 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 3415 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
group-onsemi 0:098463de4c5d 3416
group-onsemi 0:098463de4c5d 3417 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 3418 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 3419
group-onsemi 0:098463de4c5d 3420 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 3421 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
group-onsemi 0:098463de4c5d 3422 }
group-onsemi 0:098463de4c5d 3423 break;
group-onsemi 0:098463de4c5d 3424 case TIM_DMA_CC1:
group-onsemi 0:098463de4c5d 3425 {
group-onsemi 0:098463de4c5d 3426 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 3427 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
group-onsemi 0:098463de4c5d 3428
group-onsemi 0:098463de4c5d 3429 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 3430 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 3431
group-onsemi 0:098463de4c5d 3432 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 3433 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
group-onsemi 0:098463de4c5d 3434 }
group-onsemi 0:098463de4c5d 3435 break;
group-onsemi 0:098463de4c5d 3436 case TIM_DMA_CC2:
group-onsemi 0:098463de4c5d 3437 {
group-onsemi 0:098463de4c5d 3438 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 3439 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
group-onsemi 0:098463de4c5d 3440
group-onsemi 0:098463de4c5d 3441 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 3442 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 3443
group-onsemi 0:098463de4c5d 3444 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 3445 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
group-onsemi 0:098463de4c5d 3446 }
group-onsemi 0:098463de4c5d 3447 break;
group-onsemi 0:098463de4c5d 3448 case TIM_DMA_CC3:
group-onsemi 0:098463de4c5d 3449 {
group-onsemi 0:098463de4c5d 3450 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 3451 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
group-onsemi 0:098463de4c5d 3452
group-onsemi 0:098463de4c5d 3453 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 3454 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 3455
group-onsemi 0:098463de4c5d 3456 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 3457 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
group-onsemi 0:098463de4c5d 3458 }
group-onsemi 0:098463de4c5d 3459 break;
group-onsemi 0:098463de4c5d 3460 case TIM_DMA_CC4:
group-onsemi 0:098463de4c5d 3461 {
group-onsemi 0:098463de4c5d 3462 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 3463 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
group-onsemi 0:098463de4c5d 3464
group-onsemi 0:098463de4c5d 3465 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 3466 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 3467
group-onsemi 0:098463de4c5d 3468 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 3469 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
group-onsemi 0:098463de4c5d 3470 }
group-onsemi 0:098463de4c5d 3471 break;
group-onsemi 0:098463de4c5d 3472 case TIM_DMA_COM:
group-onsemi 0:098463de4c5d 3473 {
group-onsemi 0:098463de4c5d 3474 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 3475 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
group-onsemi 0:098463de4c5d 3476
group-onsemi 0:098463de4c5d 3477 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 3478 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 3479
group-onsemi 0:098463de4c5d 3480 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 3481 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
group-onsemi 0:098463de4c5d 3482 }
group-onsemi 0:098463de4c5d 3483 break;
group-onsemi 0:098463de4c5d 3484 case TIM_DMA_TRIGGER:
group-onsemi 0:098463de4c5d 3485 {
group-onsemi 0:098463de4c5d 3486 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 3487 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
group-onsemi 0:098463de4c5d 3488
group-onsemi 0:098463de4c5d 3489 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 3490 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 3491
group-onsemi 0:098463de4c5d 3492 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 3493 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
group-onsemi 0:098463de4c5d 3494 }
group-onsemi 0:098463de4c5d 3495 break;
group-onsemi 0:098463de4c5d 3496 default:
group-onsemi 0:098463de4c5d 3497 break;
group-onsemi 0:098463de4c5d 3498 }
group-onsemi 0:098463de4c5d 3499 /* configure the DMA Burst Mode */
group-onsemi 0:098463de4c5d 3500 htim->Instance->DCR = BurstBaseAddress | BurstLength;
group-onsemi 0:098463de4c5d 3501
group-onsemi 0:098463de4c5d 3502 /* Enable the TIM DMA Request */
group-onsemi 0:098463de4c5d 3503 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
group-onsemi 0:098463de4c5d 3504
group-onsemi 0:098463de4c5d 3505 htim->State = HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 3506
group-onsemi 0:098463de4c5d 3507 /* Return function status */
group-onsemi 0:098463de4c5d 3508 return HAL_OK;
group-onsemi 0:098463de4c5d 3509 }
group-onsemi 0:098463de4c5d 3510
group-onsemi 0:098463de4c5d 3511 /**
group-onsemi 0:098463de4c5d 3512 * @brief Stops the TIM DMA Burst mode
group-onsemi 0:098463de4c5d 3513 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 3514 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 3515 * @param BurstRequestSrc: TIM DMA Request sources to disable
group-onsemi 0:098463de4c5d 3516 * @retval HAL status
group-onsemi 0:098463de4c5d 3517 */
group-onsemi 0:098463de4c5d 3518 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
group-onsemi 0:098463de4c5d 3519 {
group-onsemi 0:098463de4c5d 3520 /* Check the parameters */
group-onsemi 0:098463de4c5d 3521 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
group-onsemi 0:098463de4c5d 3522
group-onsemi 0:098463de4c5d 3523 /* Abort the DMA transfer (at least disable the DMA channel) */
group-onsemi 0:098463de4c5d 3524 switch(BurstRequestSrc)
group-onsemi 0:098463de4c5d 3525 {
group-onsemi 0:098463de4c5d 3526 case TIM_DMA_UPDATE:
group-onsemi 0:098463de4c5d 3527 {
group-onsemi 0:098463de4c5d 3528 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
group-onsemi 0:098463de4c5d 3529 }
group-onsemi 0:098463de4c5d 3530 break;
group-onsemi 0:098463de4c5d 3531 case TIM_DMA_CC1:
group-onsemi 0:098463de4c5d 3532 {
group-onsemi 0:098463de4c5d 3533 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
group-onsemi 0:098463de4c5d 3534 }
group-onsemi 0:098463de4c5d 3535 break;
group-onsemi 0:098463de4c5d 3536 case TIM_DMA_CC2:
group-onsemi 0:098463de4c5d 3537 {
group-onsemi 0:098463de4c5d 3538 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
group-onsemi 0:098463de4c5d 3539 }
group-onsemi 0:098463de4c5d 3540 break;
group-onsemi 0:098463de4c5d 3541 case TIM_DMA_CC3:
group-onsemi 0:098463de4c5d 3542 {
group-onsemi 0:098463de4c5d 3543 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
group-onsemi 0:098463de4c5d 3544 }
group-onsemi 0:098463de4c5d 3545 break;
group-onsemi 0:098463de4c5d 3546 case TIM_DMA_CC4:
group-onsemi 0:098463de4c5d 3547 {
group-onsemi 0:098463de4c5d 3548 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
group-onsemi 0:098463de4c5d 3549 }
group-onsemi 0:098463de4c5d 3550 break;
group-onsemi 0:098463de4c5d 3551 case TIM_DMA_COM:
group-onsemi 0:098463de4c5d 3552 {
group-onsemi 0:098463de4c5d 3553 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
group-onsemi 0:098463de4c5d 3554 }
group-onsemi 0:098463de4c5d 3555 break;
group-onsemi 0:098463de4c5d 3556 case TIM_DMA_TRIGGER:
group-onsemi 0:098463de4c5d 3557 {
group-onsemi 0:098463de4c5d 3558 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
group-onsemi 0:098463de4c5d 3559 }
group-onsemi 0:098463de4c5d 3560 break;
group-onsemi 0:098463de4c5d 3561 default:
group-onsemi 0:098463de4c5d 3562 break;
group-onsemi 0:098463de4c5d 3563 }
group-onsemi 0:098463de4c5d 3564
group-onsemi 0:098463de4c5d 3565 /* Disable the TIM Update DMA request */
group-onsemi 0:098463de4c5d 3566 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
group-onsemi 0:098463de4c5d 3567
group-onsemi 0:098463de4c5d 3568 /* Return function status */
group-onsemi 0:098463de4c5d 3569 return HAL_OK;
group-onsemi 0:098463de4c5d 3570 }
group-onsemi 0:098463de4c5d 3571
group-onsemi 0:098463de4c5d 3572 /**
group-onsemi 0:098463de4c5d 3573 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
group-onsemi 0:098463de4c5d 3574 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 3575 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 3576 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
group-onsemi 0:098463de4c5d 3577 * This parameters can be on of the following values:
group-onsemi 0:098463de4c5d 3578 * @arg TIM_DMABASE_CR1
group-onsemi 0:098463de4c5d 3579 * @arg TIM_DMABASE_CR2
group-onsemi 0:098463de4c5d 3580 * @arg TIM_DMABASE_SMCR
group-onsemi 0:098463de4c5d 3581 * @arg TIM_DMABASE_DIER
group-onsemi 0:098463de4c5d 3582 * @arg TIM_DMABASE_SR
group-onsemi 0:098463de4c5d 3583 * @arg TIM_DMABASE_EGR
group-onsemi 0:098463de4c5d 3584 * @arg TIM_DMABASE_CCMR1
group-onsemi 0:098463de4c5d 3585 * @arg TIM_DMABASE_CCMR2
group-onsemi 0:098463de4c5d 3586 * @arg TIM_DMABASE_CCER
group-onsemi 0:098463de4c5d 3587 * @arg TIM_DMABASE_CNT
group-onsemi 0:098463de4c5d 3588 * @arg TIM_DMABASE_PSC
group-onsemi 0:098463de4c5d 3589 * @arg TIM_DMABASE_ARR
group-onsemi 0:098463de4c5d 3590 * @arg TIM_DMABASE_RCR
group-onsemi 0:098463de4c5d 3591 * @arg TIM_DMABASE_CCR1
group-onsemi 0:098463de4c5d 3592 * @arg TIM_DMABASE_CCR2
group-onsemi 0:098463de4c5d 3593 * @arg TIM_DMABASE_CCR3
group-onsemi 0:098463de4c5d 3594 * @arg TIM_DMABASE_CCR4
group-onsemi 0:098463de4c5d 3595 * @arg TIM_DMABASE_BDTR
group-onsemi 0:098463de4c5d 3596 * @arg TIM_DMABASE_DCR
group-onsemi 0:098463de4c5d 3597 * @param BurstRequestSrc: TIM DMA Request sources.
group-onsemi 0:098463de4c5d 3598 * This parameters can be on of the following values:
group-onsemi 0:098463de4c5d 3599 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
group-onsemi 0:098463de4c5d 3600 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
group-onsemi 0:098463de4c5d 3601 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
group-onsemi 0:098463de4c5d 3602 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
group-onsemi 0:098463de4c5d 3603 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
group-onsemi 0:098463de4c5d 3604 * @arg TIM_DMA_COM: TIM Commutation DMA source
group-onsemi 0:098463de4c5d 3605 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
group-onsemi 0:098463de4c5d 3606 * @param BurstBuffer: The Buffer address.
group-onsemi 0:098463de4c5d 3607 * @param BurstLength: DMA Burst length. This parameter can be one value
group-onsemi 0:098463de4c5d 3608 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
group-onsemi 0:098463de4c5d 3609 * @retval HAL status
group-onsemi 0:098463de4c5d 3610 */
group-onsemi 0:098463de4c5d 3611 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
group-onsemi 0:098463de4c5d 3612 uint32_t *BurstBuffer, uint32_t BurstLength)
group-onsemi 0:098463de4c5d 3613 {
group-onsemi 0:098463de4c5d 3614 /* Check the parameters */
group-onsemi 0:098463de4c5d 3615 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3616 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
group-onsemi 0:098463de4c5d 3617 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
group-onsemi 0:098463de4c5d 3618 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
group-onsemi 0:098463de4c5d 3619
group-onsemi 0:098463de4c5d 3620 if((htim->State == HAL_TIM_STATE_BUSY))
group-onsemi 0:098463de4c5d 3621 {
group-onsemi 0:098463de4c5d 3622 return HAL_BUSY;
group-onsemi 0:098463de4c5d 3623 }
group-onsemi 0:098463de4c5d 3624 else if((htim->State == HAL_TIM_STATE_READY))
group-onsemi 0:098463de4c5d 3625 {
group-onsemi 0:098463de4c5d 3626 if((BurstBuffer == 0 ) && (BurstLength > 0))
group-onsemi 0:098463de4c5d 3627 {
group-onsemi 0:098463de4c5d 3628 return HAL_ERROR;
group-onsemi 0:098463de4c5d 3629 }
group-onsemi 0:098463de4c5d 3630 else
group-onsemi 0:098463de4c5d 3631 {
group-onsemi 0:098463de4c5d 3632 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 3633 }
group-onsemi 0:098463de4c5d 3634 }
group-onsemi 0:098463de4c5d 3635 switch(BurstRequestSrc)
group-onsemi 0:098463de4c5d 3636 {
group-onsemi 0:098463de4c5d 3637 case TIM_DMA_UPDATE:
group-onsemi 0:098463de4c5d 3638 {
group-onsemi 0:098463de4c5d 3639 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 3640 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
group-onsemi 0:098463de4c5d 3641
group-onsemi 0:098463de4c5d 3642 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 3643 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 3644
group-onsemi 0:098463de4c5d 3645 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 3646 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
group-onsemi 0:098463de4c5d 3647 }
group-onsemi 0:098463de4c5d 3648 break;
group-onsemi 0:098463de4c5d 3649 case TIM_DMA_CC1:
group-onsemi 0:098463de4c5d 3650 {
group-onsemi 0:098463de4c5d 3651 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 3652 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
group-onsemi 0:098463de4c5d 3653
group-onsemi 0:098463de4c5d 3654 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 3655 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 3656
group-onsemi 0:098463de4c5d 3657 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 3658 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
group-onsemi 0:098463de4c5d 3659 }
group-onsemi 0:098463de4c5d 3660 break;
group-onsemi 0:098463de4c5d 3661 case TIM_DMA_CC2:
group-onsemi 0:098463de4c5d 3662 {
group-onsemi 0:098463de4c5d 3663 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 3664 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
group-onsemi 0:098463de4c5d 3665
group-onsemi 0:098463de4c5d 3666 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 3667 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 3668
group-onsemi 0:098463de4c5d 3669 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 3670 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
group-onsemi 0:098463de4c5d 3671 }
group-onsemi 0:098463de4c5d 3672 break;
group-onsemi 0:098463de4c5d 3673 case TIM_DMA_CC3:
group-onsemi 0:098463de4c5d 3674 {
group-onsemi 0:098463de4c5d 3675 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 3676 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
group-onsemi 0:098463de4c5d 3677
group-onsemi 0:098463de4c5d 3678 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 3679 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 3680
group-onsemi 0:098463de4c5d 3681 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 3682 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
group-onsemi 0:098463de4c5d 3683 }
group-onsemi 0:098463de4c5d 3684 break;
group-onsemi 0:098463de4c5d 3685 case TIM_DMA_CC4:
group-onsemi 0:098463de4c5d 3686 {
group-onsemi 0:098463de4c5d 3687 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 3688 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
group-onsemi 0:098463de4c5d 3689
group-onsemi 0:098463de4c5d 3690 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 3691 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 3692
group-onsemi 0:098463de4c5d 3693 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 3694 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
group-onsemi 0:098463de4c5d 3695 }
group-onsemi 0:098463de4c5d 3696 break;
group-onsemi 0:098463de4c5d 3697 case TIM_DMA_COM:
group-onsemi 0:098463de4c5d 3698 {
group-onsemi 0:098463de4c5d 3699 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 3700 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
group-onsemi 0:098463de4c5d 3701
group-onsemi 0:098463de4c5d 3702 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 3703 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 3704
group-onsemi 0:098463de4c5d 3705 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 3706 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
group-onsemi 0:098463de4c5d 3707 }
group-onsemi 0:098463de4c5d 3708 break;
group-onsemi 0:098463de4c5d 3709 case TIM_DMA_TRIGGER:
group-onsemi 0:098463de4c5d 3710 {
group-onsemi 0:098463de4c5d 3711 /* Set the DMA Period elapsed callback */
group-onsemi 0:098463de4c5d 3712 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
group-onsemi 0:098463de4c5d 3713
group-onsemi 0:098463de4c5d 3714 /* Set the DMA error callback */
group-onsemi 0:098463de4c5d 3715 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
group-onsemi 0:098463de4c5d 3716
group-onsemi 0:098463de4c5d 3717 /* Enable the DMA Stream */
group-onsemi 0:098463de4c5d 3718 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
group-onsemi 0:098463de4c5d 3719 }
group-onsemi 0:098463de4c5d 3720 break;
group-onsemi 0:098463de4c5d 3721 default:
group-onsemi 0:098463de4c5d 3722 break;
group-onsemi 0:098463de4c5d 3723 }
group-onsemi 0:098463de4c5d 3724
group-onsemi 0:098463de4c5d 3725 /* configure the DMA Burst Mode */
group-onsemi 0:098463de4c5d 3726 htim->Instance->DCR = BurstBaseAddress | BurstLength;
group-onsemi 0:098463de4c5d 3727
group-onsemi 0:098463de4c5d 3728 /* Enable the TIM DMA Request */
group-onsemi 0:098463de4c5d 3729 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
group-onsemi 0:098463de4c5d 3730
group-onsemi 0:098463de4c5d 3731 htim->State = HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 3732
group-onsemi 0:098463de4c5d 3733 /* Return function status */
group-onsemi 0:098463de4c5d 3734 return HAL_OK;
group-onsemi 0:098463de4c5d 3735 }
group-onsemi 0:098463de4c5d 3736
group-onsemi 0:098463de4c5d 3737 /**
group-onsemi 0:098463de4c5d 3738 * @brief Stop the DMA burst reading
group-onsemi 0:098463de4c5d 3739 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 3740 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 3741 * @param BurstRequestSrc: TIM DMA Request sources to disable.
group-onsemi 0:098463de4c5d 3742 * @retval HAL status
group-onsemi 0:098463de4c5d 3743 */
group-onsemi 0:098463de4c5d 3744 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
group-onsemi 0:098463de4c5d 3745 {
group-onsemi 0:098463de4c5d 3746 /* Check the parameters */
group-onsemi 0:098463de4c5d 3747 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
group-onsemi 0:098463de4c5d 3748
group-onsemi 0:098463de4c5d 3749 /* Abort the DMA transfer (at least disable the DMA channel) */
group-onsemi 0:098463de4c5d 3750 switch(BurstRequestSrc)
group-onsemi 0:098463de4c5d 3751 {
group-onsemi 0:098463de4c5d 3752 case TIM_DMA_UPDATE:
group-onsemi 0:098463de4c5d 3753 {
group-onsemi 0:098463de4c5d 3754 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
group-onsemi 0:098463de4c5d 3755 }
group-onsemi 0:098463de4c5d 3756 break;
group-onsemi 0:098463de4c5d 3757 case TIM_DMA_CC1:
group-onsemi 0:098463de4c5d 3758 {
group-onsemi 0:098463de4c5d 3759 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
group-onsemi 0:098463de4c5d 3760 }
group-onsemi 0:098463de4c5d 3761 break;
group-onsemi 0:098463de4c5d 3762 case TIM_DMA_CC2:
group-onsemi 0:098463de4c5d 3763 {
group-onsemi 0:098463de4c5d 3764 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
group-onsemi 0:098463de4c5d 3765 }
group-onsemi 0:098463de4c5d 3766 break;
group-onsemi 0:098463de4c5d 3767 case TIM_DMA_CC3:
group-onsemi 0:098463de4c5d 3768 {
group-onsemi 0:098463de4c5d 3769 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
group-onsemi 0:098463de4c5d 3770 }
group-onsemi 0:098463de4c5d 3771 break;
group-onsemi 0:098463de4c5d 3772 case TIM_DMA_CC4:
group-onsemi 0:098463de4c5d 3773 {
group-onsemi 0:098463de4c5d 3774 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
group-onsemi 0:098463de4c5d 3775 }
group-onsemi 0:098463de4c5d 3776 break;
group-onsemi 0:098463de4c5d 3777 case TIM_DMA_COM:
group-onsemi 0:098463de4c5d 3778 {
group-onsemi 0:098463de4c5d 3779 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
group-onsemi 0:098463de4c5d 3780 }
group-onsemi 0:098463de4c5d 3781 break;
group-onsemi 0:098463de4c5d 3782 case TIM_DMA_TRIGGER:
group-onsemi 0:098463de4c5d 3783 {
group-onsemi 0:098463de4c5d 3784 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
group-onsemi 0:098463de4c5d 3785 }
group-onsemi 0:098463de4c5d 3786 break;
group-onsemi 0:098463de4c5d 3787 default:
group-onsemi 0:098463de4c5d 3788 break;
group-onsemi 0:098463de4c5d 3789 }
group-onsemi 0:098463de4c5d 3790
group-onsemi 0:098463de4c5d 3791 /* Disable the TIM Update DMA request */
group-onsemi 0:098463de4c5d 3792 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
group-onsemi 0:098463de4c5d 3793
group-onsemi 0:098463de4c5d 3794 /* Return function status */
group-onsemi 0:098463de4c5d 3795 return HAL_OK;
group-onsemi 0:098463de4c5d 3796 }
group-onsemi 0:098463de4c5d 3797
group-onsemi 0:098463de4c5d 3798 /**
group-onsemi 0:098463de4c5d 3799 * @brief Generate a software event
group-onsemi 0:098463de4c5d 3800 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 3801 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 3802 * @param EventSource: specifies the event source.
group-onsemi 0:098463de4c5d 3803 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 3804 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
group-onsemi 0:098463de4c5d 3805 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
group-onsemi 0:098463de4c5d 3806 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
group-onsemi 0:098463de4c5d 3807 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
group-onsemi 0:098463de4c5d 3808 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
group-onsemi 0:098463de4c5d 3809 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
group-onsemi 0:098463de4c5d 3810 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
group-onsemi 0:098463de4c5d 3811 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
group-onsemi 0:098463de4c5d 3812 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
group-onsemi 0:098463de4c5d 3813 * @note TIM6 and TIM7 can only generate an update event.
group-onsemi 0:098463de4c5d 3814 * @note TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8.
group-onsemi 0:098463de4c5d 3815 * @retval HAL status
group-onsemi 0:098463de4c5d 3816 */
group-onsemi 0:098463de4c5d 3817
group-onsemi 0:098463de4c5d 3818 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
group-onsemi 0:098463de4c5d 3819 {
group-onsemi 0:098463de4c5d 3820 /* Check the parameters */
group-onsemi 0:098463de4c5d 3821 assert_param(IS_TIM_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3822 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
group-onsemi 0:098463de4c5d 3823
group-onsemi 0:098463de4c5d 3824 /* Process Locked */
group-onsemi 0:098463de4c5d 3825 __HAL_LOCK(htim);
group-onsemi 0:098463de4c5d 3826
group-onsemi 0:098463de4c5d 3827 /* Change the TIM state */
group-onsemi 0:098463de4c5d 3828 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 3829
group-onsemi 0:098463de4c5d 3830 /* Set the event sources */
group-onsemi 0:098463de4c5d 3831 htim->Instance->EGR = EventSource;
group-onsemi 0:098463de4c5d 3832
group-onsemi 0:098463de4c5d 3833 /* Change the TIM state */
group-onsemi 0:098463de4c5d 3834 htim->State = HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 3835
group-onsemi 0:098463de4c5d 3836 __HAL_UNLOCK(htim);
group-onsemi 0:098463de4c5d 3837
group-onsemi 0:098463de4c5d 3838 /* Return function status */
group-onsemi 0:098463de4c5d 3839 return HAL_OK;
group-onsemi 0:098463de4c5d 3840 }
group-onsemi 0:098463de4c5d 3841
group-onsemi 0:098463de4c5d 3842 /**
group-onsemi 0:098463de4c5d 3843 * @brief Configures the OCRef clear feature
group-onsemi 0:098463de4c5d 3844 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 3845 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 3846 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
group-onsemi 0:098463de4c5d 3847 * contains the OCREF clear feature and parameters for the TIM peripheral.
group-onsemi 0:098463de4c5d 3848 * @param Channel: specifies the TIM Channel.
group-onsemi 0:098463de4c5d 3849 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 3850 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 3851 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 3852 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 3853 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 3854 * @retval HAL status
group-onsemi 0:098463de4c5d 3855 */
group-onsemi 0:098463de4c5d 3856 __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
group-onsemi 0:098463de4c5d 3857 {
group-onsemi 0:098463de4c5d 3858 /* Check the parameters */
group-onsemi 0:098463de4c5d 3859 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3860 assert_param(IS_TIM_CHANNELS(Channel));
group-onsemi 0:098463de4c5d 3861 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
group-onsemi 0:098463de4c5d 3862
group-onsemi 0:098463de4c5d 3863 /* Process Locked */
group-onsemi 0:098463de4c5d 3864 __HAL_LOCK(htim);
group-onsemi 0:098463de4c5d 3865
group-onsemi 0:098463de4c5d 3866 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 3867
group-onsemi 0:098463de4c5d 3868 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
group-onsemi 0:098463de4c5d 3869 {
group-onsemi 0:098463de4c5d 3870 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
group-onsemi 0:098463de4c5d 3871 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
group-onsemi 0:098463de4c5d 3872 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
group-onsemi 0:098463de4c5d 3873
group-onsemi 0:098463de4c5d 3874 TIM_ETR_SetConfig(htim->Instance,
group-onsemi 0:098463de4c5d 3875 sClearInputConfig->ClearInputPrescaler,
group-onsemi 0:098463de4c5d 3876 sClearInputConfig->ClearInputPolarity,
group-onsemi 0:098463de4c5d 3877 sClearInputConfig->ClearInputFilter);
group-onsemi 0:098463de4c5d 3878 }
group-onsemi 0:098463de4c5d 3879
group-onsemi 0:098463de4c5d 3880 switch (Channel)
group-onsemi 0:098463de4c5d 3881 {
group-onsemi 0:098463de4c5d 3882 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 3883 {
group-onsemi 0:098463de4c5d 3884 if(sClearInputConfig->ClearInputState != RESET)
group-onsemi 0:098463de4c5d 3885 {
group-onsemi 0:098463de4c5d 3886 /* Enable the Ocref clear feature for Channel 1 */
group-onsemi 0:098463de4c5d 3887 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
group-onsemi 0:098463de4c5d 3888 }
group-onsemi 0:098463de4c5d 3889 else
group-onsemi 0:098463de4c5d 3890 {
group-onsemi 0:098463de4c5d 3891 /* Disable the Ocref clear feature for Channel 1 */
group-onsemi 0:098463de4c5d 3892 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
group-onsemi 0:098463de4c5d 3893 }
group-onsemi 0:098463de4c5d 3894 }
group-onsemi 0:098463de4c5d 3895 break;
group-onsemi 0:098463de4c5d 3896 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 3897 {
group-onsemi 0:098463de4c5d 3898 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3899 if(sClearInputConfig->ClearInputState != RESET)
group-onsemi 0:098463de4c5d 3900 {
group-onsemi 0:098463de4c5d 3901 /* Enable the Ocref clear feature for Channel 2 */
group-onsemi 0:098463de4c5d 3902 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
group-onsemi 0:098463de4c5d 3903 }
group-onsemi 0:098463de4c5d 3904 else
group-onsemi 0:098463de4c5d 3905 {
group-onsemi 0:098463de4c5d 3906 /* Disable the Ocref clear feature for Channel 2 */
group-onsemi 0:098463de4c5d 3907 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
group-onsemi 0:098463de4c5d 3908 }
group-onsemi 0:098463de4c5d 3909 }
group-onsemi 0:098463de4c5d 3910 break;
group-onsemi 0:098463de4c5d 3911 case TIM_CHANNEL_3:
group-onsemi 0:098463de4c5d 3912 {
group-onsemi 0:098463de4c5d 3913 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3914 if(sClearInputConfig->ClearInputState != RESET)
group-onsemi 0:098463de4c5d 3915 {
group-onsemi 0:098463de4c5d 3916 /* Enable the Ocref clear feature for Channel 3 */
group-onsemi 0:098463de4c5d 3917 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
group-onsemi 0:098463de4c5d 3918 }
group-onsemi 0:098463de4c5d 3919 else
group-onsemi 0:098463de4c5d 3920 {
group-onsemi 0:098463de4c5d 3921 /* Disable the Ocref clear feature for Channel 3 */
group-onsemi 0:098463de4c5d 3922 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
group-onsemi 0:098463de4c5d 3923 }
group-onsemi 0:098463de4c5d 3924 }
group-onsemi 0:098463de4c5d 3925 break;
group-onsemi 0:098463de4c5d 3926 case TIM_CHANNEL_4:
group-onsemi 0:098463de4c5d 3927 {
group-onsemi 0:098463de4c5d 3928 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3929 if(sClearInputConfig->ClearInputState != RESET)
group-onsemi 0:098463de4c5d 3930 {
group-onsemi 0:098463de4c5d 3931 /* Enable the Ocref clear feature for Channel 4 */
group-onsemi 0:098463de4c5d 3932 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
group-onsemi 0:098463de4c5d 3933 }
group-onsemi 0:098463de4c5d 3934 else
group-onsemi 0:098463de4c5d 3935 {
group-onsemi 0:098463de4c5d 3936 /* Disable the Ocref clear feature for Channel 4 */
group-onsemi 0:098463de4c5d 3937 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
group-onsemi 0:098463de4c5d 3938 }
group-onsemi 0:098463de4c5d 3939 }
group-onsemi 0:098463de4c5d 3940 break;
group-onsemi 0:098463de4c5d 3941 default:
group-onsemi 0:098463de4c5d 3942 break;
group-onsemi 0:098463de4c5d 3943 }
group-onsemi 0:098463de4c5d 3944
group-onsemi 0:098463de4c5d 3945 htim->State = HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 3946
group-onsemi 0:098463de4c5d 3947 __HAL_UNLOCK(htim);
group-onsemi 0:098463de4c5d 3948
group-onsemi 0:098463de4c5d 3949 return HAL_OK;
group-onsemi 0:098463de4c5d 3950 }
group-onsemi 0:098463de4c5d 3951
group-onsemi 0:098463de4c5d 3952 /**
group-onsemi 0:098463de4c5d 3953 * @brief Configures the clock source to be used
group-onsemi 0:098463de4c5d 3954 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 3955 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 3956 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
group-onsemi 0:098463de4c5d 3957 * contains the clock source information for the TIM peripheral.
group-onsemi 0:098463de4c5d 3958 * @retval HAL status
group-onsemi 0:098463de4c5d 3959 */
group-onsemi 0:098463de4c5d 3960 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
group-onsemi 0:098463de4c5d 3961 {
group-onsemi 0:098463de4c5d 3962 uint32_t tmpsmcr = 0;
group-onsemi 0:098463de4c5d 3963
group-onsemi 0:098463de4c5d 3964 /* Process Locked */
group-onsemi 0:098463de4c5d 3965 __HAL_LOCK(htim);
group-onsemi 0:098463de4c5d 3966
group-onsemi 0:098463de4c5d 3967 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 3968
group-onsemi 0:098463de4c5d 3969 /* Check the parameters */
group-onsemi 0:098463de4c5d 3970 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
group-onsemi 0:098463de4c5d 3971
group-onsemi 0:098463de4c5d 3972 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
group-onsemi 0:098463de4c5d 3973 tmpsmcr = htim->Instance->SMCR;
group-onsemi 0:098463de4c5d 3974 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
group-onsemi 0:098463de4c5d 3975 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
group-onsemi 0:098463de4c5d 3976 htim->Instance->SMCR = tmpsmcr;
group-onsemi 0:098463de4c5d 3977
group-onsemi 0:098463de4c5d 3978 switch (sClockSourceConfig->ClockSource)
group-onsemi 0:098463de4c5d 3979 {
group-onsemi 0:098463de4c5d 3980 case TIM_CLOCKSOURCE_INTERNAL:
group-onsemi 0:098463de4c5d 3981 {
group-onsemi 0:098463de4c5d 3982 assert_param(IS_TIM_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3983 /* Disable slave mode to clock the prescaler directly with the internal clock */
group-onsemi 0:098463de4c5d 3984 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
group-onsemi 0:098463de4c5d 3985 }
group-onsemi 0:098463de4c5d 3986 break;
group-onsemi 0:098463de4c5d 3987
group-onsemi 0:098463de4c5d 3988 case TIM_CLOCKSOURCE_ETRMODE1:
group-onsemi 0:098463de4c5d 3989 {
group-onsemi 0:098463de4c5d 3990 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 3991 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
group-onsemi 0:098463de4c5d 3992 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
group-onsemi 0:098463de4c5d 3993 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
group-onsemi 0:098463de4c5d 3994 /* Configure the ETR Clock source */
group-onsemi 0:098463de4c5d 3995 TIM_ETR_SetConfig(htim->Instance,
group-onsemi 0:098463de4c5d 3996 sClockSourceConfig->ClockPrescaler,
group-onsemi 0:098463de4c5d 3997 sClockSourceConfig->ClockPolarity,
group-onsemi 0:098463de4c5d 3998 sClockSourceConfig->ClockFilter);
group-onsemi 0:098463de4c5d 3999 /* Get the TIMx SMCR register value */
group-onsemi 0:098463de4c5d 4000 tmpsmcr = htim->Instance->SMCR;
group-onsemi 0:098463de4c5d 4001 /* Reset the SMS and TS Bits */
group-onsemi 0:098463de4c5d 4002 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
group-onsemi 0:098463de4c5d 4003 /* Select the External clock mode1 and the ETRF trigger */
group-onsemi 0:098463de4c5d 4004 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
group-onsemi 0:098463de4c5d 4005 /* Write to TIMx SMCR */
group-onsemi 0:098463de4c5d 4006 htim->Instance->SMCR = tmpsmcr;
group-onsemi 0:098463de4c5d 4007 }
group-onsemi 0:098463de4c5d 4008 break;
group-onsemi 0:098463de4c5d 4009
group-onsemi 0:098463de4c5d 4010 case TIM_CLOCKSOURCE_ETRMODE2:
group-onsemi 0:098463de4c5d 4011 {
group-onsemi 0:098463de4c5d 4012 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4013 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
group-onsemi 0:098463de4c5d 4014 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
group-onsemi 0:098463de4c5d 4015 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
group-onsemi 0:098463de4c5d 4016
group-onsemi 0:098463de4c5d 4017 /* Configure the ETR Clock source */
group-onsemi 0:098463de4c5d 4018 TIM_ETR_SetConfig(htim->Instance,
group-onsemi 0:098463de4c5d 4019 sClockSourceConfig->ClockPrescaler,
group-onsemi 0:098463de4c5d 4020 sClockSourceConfig->ClockPolarity,
group-onsemi 0:098463de4c5d 4021 sClockSourceConfig->ClockFilter);
group-onsemi 0:098463de4c5d 4022 /* Enable the External clock mode2 */
group-onsemi 0:098463de4c5d 4023 htim->Instance->SMCR |= TIM_SMCR_ECE;
group-onsemi 0:098463de4c5d 4024 }
group-onsemi 0:098463de4c5d 4025 break;
group-onsemi 0:098463de4c5d 4026
group-onsemi 0:098463de4c5d 4027 case TIM_CLOCKSOURCE_TI1:
group-onsemi 0:098463de4c5d 4028 {
group-onsemi 0:098463de4c5d 4029 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4030
group-onsemi 0:098463de4c5d 4031 /* Check TI1 input conditioning related parameters */
group-onsemi 0:098463de4c5d 4032 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
group-onsemi 0:098463de4c5d 4033 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
group-onsemi 0:098463de4c5d 4034
group-onsemi 0:098463de4c5d 4035 TIM_TI1_ConfigInputStage(htim->Instance,
group-onsemi 0:098463de4c5d 4036 sClockSourceConfig->ClockPolarity,
group-onsemi 0:098463de4c5d 4037 sClockSourceConfig->ClockFilter);
group-onsemi 0:098463de4c5d 4038 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
group-onsemi 0:098463de4c5d 4039 }
group-onsemi 0:098463de4c5d 4040 break;
group-onsemi 0:098463de4c5d 4041 case TIM_CLOCKSOURCE_TI2:
group-onsemi 0:098463de4c5d 4042 {
group-onsemi 0:098463de4c5d 4043 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4044
group-onsemi 0:098463de4c5d 4045 /* Check TI1 input conditioning related parameters */
group-onsemi 0:098463de4c5d 4046 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
group-onsemi 0:098463de4c5d 4047 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
group-onsemi 0:098463de4c5d 4048
group-onsemi 0:098463de4c5d 4049 TIM_TI2_ConfigInputStage(htim->Instance,
group-onsemi 0:098463de4c5d 4050 sClockSourceConfig->ClockPolarity,
group-onsemi 0:098463de4c5d 4051 sClockSourceConfig->ClockFilter);
group-onsemi 0:098463de4c5d 4052 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
group-onsemi 0:098463de4c5d 4053 }
group-onsemi 0:098463de4c5d 4054 break;
group-onsemi 0:098463de4c5d 4055 case TIM_CLOCKSOURCE_TI1ED:
group-onsemi 0:098463de4c5d 4056 {
group-onsemi 0:098463de4c5d 4057 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4058 /* Check TI1 input conditioning related parameters */
group-onsemi 0:098463de4c5d 4059 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
group-onsemi 0:098463de4c5d 4060 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
group-onsemi 0:098463de4c5d 4061
group-onsemi 0:098463de4c5d 4062 TIM_TI1_ConfigInputStage(htim->Instance,
group-onsemi 0:098463de4c5d 4063 sClockSourceConfig->ClockPolarity,
group-onsemi 0:098463de4c5d 4064 sClockSourceConfig->ClockFilter);
group-onsemi 0:098463de4c5d 4065 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
group-onsemi 0:098463de4c5d 4066 }
group-onsemi 0:098463de4c5d 4067 break;
group-onsemi 0:098463de4c5d 4068 case TIM_CLOCKSOURCE_ITR0:
group-onsemi 0:098463de4c5d 4069 {
group-onsemi 0:098463de4c5d 4070 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4071 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
group-onsemi 0:098463de4c5d 4072 }
group-onsemi 0:098463de4c5d 4073 break;
group-onsemi 0:098463de4c5d 4074 case TIM_CLOCKSOURCE_ITR1:
group-onsemi 0:098463de4c5d 4075 {
group-onsemi 0:098463de4c5d 4076 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4077 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
group-onsemi 0:098463de4c5d 4078 }
group-onsemi 0:098463de4c5d 4079 break;
group-onsemi 0:098463de4c5d 4080 case TIM_CLOCKSOURCE_ITR2:
group-onsemi 0:098463de4c5d 4081 {
group-onsemi 0:098463de4c5d 4082 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4083 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
group-onsemi 0:098463de4c5d 4084 }
group-onsemi 0:098463de4c5d 4085 break;
group-onsemi 0:098463de4c5d 4086 case TIM_CLOCKSOURCE_ITR3:
group-onsemi 0:098463de4c5d 4087 {
group-onsemi 0:098463de4c5d 4088 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4089 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
group-onsemi 0:098463de4c5d 4090 }
group-onsemi 0:098463de4c5d 4091 break;
group-onsemi 0:098463de4c5d 4092
group-onsemi 0:098463de4c5d 4093 default:
group-onsemi 0:098463de4c5d 4094 break;
group-onsemi 0:098463de4c5d 4095 }
group-onsemi 0:098463de4c5d 4096 htim->State = HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 4097
group-onsemi 0:098463de4c5d 4098 __HAL_UNLOCK(htim);
group-onsemi 0:098463de4c5d 4099
group-onsemi 0:098463de4c5d 4100 return HAL_OK;
group-onsemi 0:098463de4c5d 4101 }
group-onsemi 0:098463de4c5d 4102
group-onsemi 0:098463de4c5d 4103 /**
group-onsemi 0:098463de4c5d 4104 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
group-onsemi 0:098463de4c5d 4105 * or a XOR combination between CH1_input, CH2_input & CH3_input
group-onsemi 0:098463de4c5d 4106 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4107 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 4108 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
group-onsemi 0:098463de4c5d 4109 * output of a XOR gate.
group-onsemi 0:098463de4c5d 4110 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 4111 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
group-onsemi 0:098463de4c5d 4112 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
group-onsemi 0:098463de4c5d 4113 * pins are connected to the TI1 input (XOR combination)
group-onsemi 0:098463de4c5d 4114 * @retval HAL status
group-onsemi 0:098463de4c5d 4115 */
group-onsemi 0:098463de4c5d 4116 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
group-onsemi 0:098463de4c5d 4117 {
group-onsemi 0:098463de4c5d 4118 uint32_t tmpcr2 = 0;
group-onsemi 0:098463de4c5d 4119
group-onsemi 0:098463de4c5d 4120 /* Check the parameters */
group-onsemi 0:098463de4c5d 4121 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4122 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
group-onsemi 0:098463de4c5d 4123
group-onsemi 0:098463de4c5d 4124 /* Get the TIMx CR2 register value */
group-onsemi 0:098463de4c5d 4125 tmpcr2 = htim->Instance->CR2;
group-onsemi 0:098463de4c5d 4126
group-onsemi 0:098463de4c5d 4127 /* Reset the TI1 selection */
group-onsemi 0:098463de4c5d 4128 tmpcr2 &= ~TIM_CR2_TI1S;
group-onsemi 0:098463de4c5d 4129
group-onsemi 0:098463de4c5d 4130 /* Set the TI1 selection */
group-onsemi 0:098463de4c5d 4131 tmpcr2 |= TI1_Selection;
group-onsemi 0:098463de4c5d 4132
group-onsemi 0:098463de4c5d 4133 /* Write to TIMxCR2 */
group-onsemi 0:098463de4c5d 4134 htim->Instance->CR2 = tmpcr2;
group-onsemi 0:098463de4c5d 4135
group-onsemi 0:098463de4c5d 4136 return HAL_OK;
group-onsemi 0:098463de4c5d 4137 }
group-onsemi 0:098463de4c5d 4138
group-onsemi 0:098463de4c5d 4139 /**
group-onsemi 0:098463de4c5d 4140 * @brief Configures the TIM in Slave mode
group-onsemi 0:098463de4c5d 4141 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4142 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 4143 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
group-onsemi 0:098463de4c5d 4144 * contains the selected trigger (internal trigger input, filtered
group-onsemi 0:098463de4c5d 4145 * timer input or external trigger input) and the ) and the Slave
group-onsemi 0:098463de4c5d 4146 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
group-onsemi 0:098463de4c5d 4147 * @retval HAL status
group-onsemi 0:098463de4c5d 4148 */
group-onsemi 0:098463de4c5d 4149 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
group-onsemi 0:098463de4c5d 4150 {
group-onsemi 0:098463de4c5d 4151 uint32_t tmpsmcr = 0;
group-onsemi 0:098463de4c5d 4152 uint32_t tmpccmr1 = 0;
group-onsemi 0:098463de4c5d 4153 uint32_t tmpccer = 0;
group-onsemi 0:098463de4c5d 4154
group-onsemi 0:098463de4c5d 4155 /* Check the parameters */
group-onsemi 0:098463de4c5d 4156 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4157 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
group-onsemi 0:098463de4c5d 4158 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
group-onsemi 0:098463de4c5d 4159
group-onsemi 0:098463de4c5d 4160 __HAL_LOCK(htim);
group-onsemi 0:098463de4c5d 4161
group-onsemi 0:098463de4c5d 4162 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 4163
group-onsemi 0:098463de4c5d 4164 /* Get the TIMx SMCR register value */
group-onsemi 0:098463de4c5d 4165 tmpsmcr = htim->Instance->SMCR;
group-onsemi 0:098463de4c5d 4166
group-onsemi 0:098463de4c5d 4167 /* Reset the Trigger Selection Bits */
group-onsemi 0:098463de4c5d 4168 tmpsmcr &= ~TIM_SMCR_TS;
group-onsemi 0:098463de4c5d 4169 /* Set the Input Trigger source */
group-onsemi 0:098463de4c5d 4170 tmpsmcr |= sSlaveConfig->InputTrigger;
group-onsemi 0:098463de4c5d 4171
group-onsemi 0:098463de4c5d 4172 /* Reset the slave mode Bits */
group-onsemi 0:098463de4c5d 4173 tmpsmcr &= ~TIM_SMCR_SMS;
group-onsemi 0:098463de4c5d 4174 /* Set the slave mode */
group-onsemi 0:098463de4c5d 4175 tmpsmcr |= sSlaveConfig->SlaveMode;
group-onsemi 0:098463de4c5d 4176
group-onsemi 0:098463de4c5d 4177 /* Write to TIMx SMCR */
group-onsemi 0:098463de4c5d 4178 htim->Instance->SMCR = tmpsmcr;
group-onsemi 0:098463de4c5d 4179
group-onsemi 0:098463de4c5d 4180 /* Configure the trigger prescaler, filter, and polarity */
group-onsemi 0:098463de4c5d 4181 switch (sSlaveConfig->InputTrigger)
group-onsemi 0:098463de4c5d 4182 {
group-onsemi 0:098463de4c5d 4183 case TIM_TS_ETRF:
group-onsemi 0:098463de4c5d 4184 {
group-onsemi 0:098463de4c5d 4185 /* Check the parameters */
group-onsemi 0:098463de4c5d 4186 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4187 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
group-onsemi 0:098463de4c5d 4188 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
group-onsemi 0:098463de4c5d 4189 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
group-onsemi 0:098463de4c5d 4190 /* Configure the ETR Trigger source */
group-onsemi 0:098463de4c5d 4191 TIM_ETR_SetConfig(htim->Instance,
group-onsemi 0:098463de4c5d 4192 sSlaveConfig->TriggerPrescaler,
group-onsemi 0:098463de4c5d 4193 sSlaveConfig->TriggerPolarity,
group-onsemi 0:098463de4c5d 4194 sSlaveConfig->TriggerFilter);
group-onsemi 0:098463de4c5d 4195 }
group-onsemi 0:098463de4c5d 4196 break;
group-onsemi 0:098463de4c5d 4197
group-onsemi 0:098463de4c5d 4198 case TIM_TS_TI1F_ED:
group-onsemi 0:098463de4c5d 4199 {
group-onsemi 0:098463de4c5d 4200 /* Check the parameters */
group-onsemi 0:098463de4c5d 4201 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4202 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
group-onsemi 0:098463de4c5d 4203
group-onsemi 0:098463de4c5d 4204 /* Disable the Channel 1: Reset the CC1E Bit */
group-onsemi 0:098463de4c5d 4205 tmpccer = htim->Instance->CCER;
group-onsemi 0:098463de4c5d 4206 htim->Instance->CCER &= ~TIM_CCER_CC1E;
group-onsemi 0:098463de4c5d 4207 tmpccmr1 = htim->Instance->CCMR1;
group-onsemi 0:098463de4c5d 4208
group-onsemi 0:098463de4c5d 4209 /* Set the filter */
group-onsemi 0:098463de4c5d 4210 tmpccmr1 &= ~TIM_CCMR1_IC1F;
group-onsemi 0:098463de4c5d 4211 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
group-onsemi 0:098463de4c5d 4212
group-onsemi 0:098463de4c5d 4213 /* Write to TIMx CCMR1 and CCER registers */
group-onsemi 0:098463de4c5d 4214 htim->Instance->CCMR1 = tmpccmr1;
group-onsemi 0:098463de4c5d 4215 htim->Instance->CCER = tmpccer;
group-onsemi 0:098463de4c5d 4216
group-onsemi 0:098463de4c5d 4217 }
group-onsemi 0:098463de4c5d 4218 break;
group-onsemi 0:098463de4c5d 4219
group-onsemi 0:098463de4c5d 4220 case TIM_TS_TI1FP1:
group-onsemi 0:098463de4c5d 4221 {
group-onsemi 0:098463de4c5d 4222 /* Check the parameters */
group-onsemi 0:098463de4c5d 4223 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4224 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
group-onsemi 0:098463de4c5d 4225 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
group-onsemi 0:098463de4c5d 4226
group-onsemi 0:098463de4c5d 4227 /* Configure TI1 Filter and Polarity */
group-onsemi 0:098463de4c5d 4228 TIM_TI1_ConfigInputStage(htim->Instance,
group-onsemi 0:098463de4c5d 4229 sSlaveConfig->TriggerPolarity,
group-onsemi 0:098463de4c5d 4230 sSlaveConfig->TriggerFilter);
group-onsemi 0:098463de4c5d 4231 }
group-onsemi 0:098463de4c5d 4232 break;
group-onsemi 0:098463de4c5d 4233
group-onsemi 0:098463de4c5d 4234 case TIM_TS_TI2FP2:
group-onsemi 0:098463de4c5d 4235 {
group-onsemi 0:098463de4c5d 4236 /* Check the parameters */
group-onsemi 0:098463de4c5d 4237 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4238 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
group-onsemi 0:098463de4c5d 4239 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
group-onsemi 0:098463de4c5d 4240
group-onsemi 0:098463de4c5d 4241 /* Configure TI2 Filter and Polarity */
group-onsemi 0:098463de4c5d 4242 TIM_TI2_ConfigInputStage(htim->Instance,
group-onsemi 0:098463de4c5d 4243 sSlaveConfig->TriggerPolarity,
group-onsemi 0:098463de4c5d 4244 sSlaveConfig->TriggerFilter);
group-onsemi 0:098463de4c5d 4245 }
group-onsemi 0:098463de4c5d 4246 break;
group-onsemi 0:098463de4c5d 4247
group-onsemi 0:098463de4c5d 4248 case TIM_TS_ITR0:
group-onsemi 0:098463de4c5d 4249 {
group-onsemi 0:098463de4c5d 4250 /* Check the parameter */
group-onsemi 0:098463de4c5d 4251 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4252 }
group-onsemi 0:098463de4c5d 4253 break;
group-onsemi 0:098463de4c5d 4254
group-onsemi 0:098463de4c5d 4255 case TIM_TS_ITR1:
group-onsemi 0:098463de4c5d 4256 {
group-onsemi 0:098463de4c5d 4257 /* Check the parameter */
group-onsemi 0:098463de4c5d 4258 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4259 }
group-onsemi 0:098463de4c5d 4260 break;
group-onsemi 0:098463de4c5d 4261
group-onsemi 0:098463de4c5d 4262 case TIM_TS_ITR2:
group-onsemi 0:098463de4c5d 4263 {
group-onsemi 0:098463de4c5d 4264 /* Check the parameter */
group-onsemi 0:098463de4c5d 4265 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4266 }
group-onsemi 0:098463de4c5d 4267 break;
group-onsemi 0:098463de4c5d 4268
group-onsemi 0:098463de4c5d 4269 case TIM_TS_ITR3:
group-onsemi 0:098463de4c5d 4270 {
group-onsemi 0:098463de4c5d 4271 /* Check the parameter */
group-onsemi 0:098463de4c5d 4272 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4273 }
group-onsemi 0:098463de4c5d 4274 break;
group-onsemi 0:098463de4c5d 4275
group-onsemi 0:098463de4c5d 4276 default:
group-onsemi 0:098463de4c5d 4277 break;
group-onsemi 0:098463de4c5d 4278 }
group-onsemi 0:098463de4c5d 4279
group-onsemi 0:098463de4c5d 4280 htim->State = HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 4281
group-onsemi 0:098463de4c5d 4282 __HAL_UNLOCK(htim);
group-onsemi 0:098463de4c5d 4283
group-onsemi 0:098463de4c5d 4284 return HAL_OK;
group-onsemi 0:098463de4c5d 4285 }
group-onsemi 0:098463de4c5d 4286
group-onsemi 0:098463de4c5d 4287 /**
group-onsemi 0:098463de4c5d 4288 * @brief Configures the TIM in Slave mode in interrupt mode
group-onsemi 0:098463de4c5d 4289 * @param htim: TIM handle.
group-onsemi 0:098463de4c5d 4290 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
group-onsemi 0:098463de4c5d 4291 * contains the selected trigger (internal trigger input, filtered
group-onsemi 0:098463de4c5d 4292 * timer input or external trigger input) and the ) and the Slave
group-onsemi 0:098463de4c5d 4293 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
group-onsemi 0:098463de4c5d 4294 * @retval HAL status
group-onsemi 0:098463de4c5d 4295 */
group-onsemi 0:098463de4c5d 4296 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
group-onsemi 0:098463de4c5d 4297 TIM_SlaveConfigTypeDef * sSlaveConfig)
group-onsemi 0:098463de4c5d 4298 {
group-onsemi 0:098463de4c5d 4299 /* Check the parameters */
group-onsemi 0:098463de4c5d 4300 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4301 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
group-onsemi 0:098463de4c5d 4302 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
group-onsemi 0:098463de4c5d 4303
group-onsemi 0:098463de4c5d 4304 __HAL_LOCK(htim);
group-onsemi 0:098463de4c5d 4305
group-onsemi 0:098463de4c5d 4306 htim->State = HAL_TIM_STATE_BUSY;
group-onsemi 0:098463de4c5d 4307
group-onsemi 0:098463de4c5d 4308 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
group-onsemi 0:098463de4c5d 4309
group-onsemi 0:098463de4c5d 4310 /* Enable Trigger Interrupt */
group-onsemi 0:098463de4c5d 4311 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
group-onsemi 0:098463de4c5d 4312
group-onsemi 0:098463de4c5d 4313 /* Disable Trigger DMA request */
group-onsemi 0:098463de4c5d 4314 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
group-onsemi 0:098463de4c5d 4315
group-onsemi 0:098463de4c5d 4316 htim->State = HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 4317
group-onsemi 0:098463de4c5d 4318 __HAL_UNLOCK(htim);
group-onsemi 0:098463de4c5d 4319
group-onsemi 0:098463de4c5d 4320 return HAL_OK;
group-onsemi 0:098463de4c5d 4321 }
group-onsemi 0:098463de4c5d 4322
group-onsemi 0:098463de4c5d 4323 /**
group-onsemi 0:098463de4c5d 4324 * @brief Read the captured value from Capture Compare unit
group-onsemi 0:098463de4c5d 4325 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4326 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 4327 * @param Channel: TIM Channels to be enabled.
group-onsemi 0:098463de4c5d 4328 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 4329 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
group-onsemi 0:098463de4c5d 4330 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
group-onsemi 0:098463de4c5d 4331 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
group-onsemi 0:098463de4c5d 4332 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
group-onsemi 0:098463de4c5d 4333 * @retval Captured value
group-onsemi 0:098463de4c5d 4334 */
group-onsemi 0:098463de4c5d 4335 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
group-onsemi 0:098463de4c5d 4336 {
group-onsemi 0:098463de4c5d 4337 uint32_t tmpreg = 0;
group-onsemi 0:098463de4c5d 4338
group-onsemi 0:098463de4c5d 4339 __HAL_LOCK(htim);
group-onsemi 0:098463de4c5d 4340
group-onsemi 0:098463de4c5d 4341 switch (Channel)
group-onsemi 0:098463de4c5d 4342 {
group-onsemi 0:098463de4c5d 4343 case TIM_CHANNEL_1:
group-onsemi 0:098463de4c5d 4344 {
group-onsemi 0:098463de4c5d 4345 /* Check the parameters */
group-onsemi 0:098463de4c5d 4346 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4347
group-onsemi 0:098463de4c5d 4348 /* Return the capture 1 value */
group-onsemi 0:098463de4c5d 4349 tmpreg = htim->Instance->CCR1;
group-onsemi 0:098463de4c5d 4350
group-onsemi 0:098463de4c5d 4351 break;
group-onsemi 0:098463de4c5d 4352 }
group-onsemi 0:098463de4c5d 4353 case TIM_CHANNEL_2:
group-onsemi 0:098463de4c5d 4354 {
group-onsemi 0:098463de4c5d 4355 /* Check the parameters */
group-onsemi 0:098463de4c5d 4356 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4357
group-onsemi 0:098463de4c5d 4358 /* Return the capture 2 value */
group-onsemi 0:098463de4c5d 4359 tmpreg = htim->Instance->CCR2;
group-onsemi 0:098463de4c5d 4360
group-onsemi 0:098463de4c5d 4361 break;
group-onsemi 0:098463de4c5d 4362 }
group-onsemi 0:098463de4c5d 4363
group-onsemi 0:098463de4c5d 4364 case TIM_CHANNEL_3:
group-onsemi 0:098463de4c5d 4365 {
group-onsemi 0:098463de4c5d 4366 /* Check the parameters */
group-onsemi 0:098463de4c5d 4367 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4368
group-onsemi 0:098463de4c5d 4369 /* Return the capture 3 value */
group-onsemi 0:098463de4c5d 4370 tmpreg = htim->Instance->CCR3;
group-onsemi 0:098463de4c5d 4371
group-onsemi 0:098463de4c5d 4372 break;
group-onsemi 0:098463de4c5d 4373 }
group-onsemi 0:098463de4c5d 4374
group-onsemi 0:098463de4c5d 4375 case TIM_CHANNEL_4:
group-onsemi 0:098463de4c5d 4376 {
group-onsemi 0:098463de4c5d 4377 /* Check the parameters */
group-onsemi 0:098463de4c5d 4378 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 4379
group-onsemi 0:098463de4c5d 4380 /* Return the capture 4 value */
group-onsemi 0:098463de4c5d 4381 tmpreg = htim->Instance->CCR4;
group-onsemi 0:098463de4c5d 4382
group-onsemi 0:098463de4c5d 4383 break;
group-onsemi 0:098463de4c5d 4384 }
group-onsemi 0:098463de4c5d 4385
group-onsemi 0:098463de4c5d 4386 default:
group-onsemi 0:098463de4c5d 4387 break;
group-onsemi 0:098463de4c5d 4388 }
group-onsemi 0:098463de4c5d 4389
group-onsemi 0:098463de4c5d 4390 __HAL_UNLOCK(htim);
group-onsemi 0:098463de4c5d 4391 return tmpreg;
group-onsemi 0:098463de4c5d 4392 }
group-onsemi 0:098463de4c5d 4393
group-onsemi 0:098463de4c5d 4394 /**
group-onsemi 0:098463de4c5d 4395 * @}
group-onsemi 0:098463de4c5d 4396 */
group-onsemi 0:098463de4c5d 4397
group-onsemi 0:098463de4c5d 4398 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
group-onsemi 0:098463de4c5d 4399 * @brief TIM Callbacks functions
group-onsemi 0:098463de4c5d 4400 *
group-onsemi 0:098463de4c5d 4401 @verbatim
group-onsemi 0:098463de4c5d 4402 ==============================================================================
group-onsemi 0:098463de4c5d 4403 ##### TIM Callbacks functions #####
group-onsemi 0:098463de4c5d 4404 ==============================================================================
group-onsemi 0:098463de4c5d 4405 [..]
group-onsemi 0:098463de4c5d 4406 This section provides TIM callback functions:
group-onsemi 0:098463de4c5d 4407 (+) Timer Period elapsed callback
group-onsemi 0:098463de4c5d 4408 (+) Timer Output Compare callback
group-onsemi 0:098463de4c5d 4409 (+) Timer Input capture callback
group-onsemi 0:098463de4c5d 4410 (+) Timer Trigger callback
group-onsemi 0:098463de4c5d 4411 (+) Timer Error callback
group-onsemi 0:098463de4c5d 4412
group-onsemi 0:098463de4c5d 4413 @endverbatim
group-onsemi 0:098463de4c5d 4414 * @{
group-onsemi 0:098463de4c5d 4415 */
group-onsemi 0:098463de4c5d 4416
group-onsemi 0:098463de4c5d 4417 /**
group-onsemi 0:098463de4c5d 4418 * @brief Period elapsed callback in non blocking mode
group-onsemi 0:098463de4c5d 4419 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4420 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 4421 * @retval None
group-onsemi 0:098463de4c5d 4422 */
group-onsemi 0:098463de4c5d 4423 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 4424 {
group-onsemi 0:098463de4c5d 4425 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 4426 UNUSED(htim);
group-onsemi 0:098463de4c5d 4427
group-onsemi 0:098463de4c5d 4428 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 4429 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
group-onsemi 0:098463de4c5d 4430 */
group-onsemi 0:098463de4c5d 4431
group-onsemi 0:098463de4c5d 4432 }
group-onsemi 0:098463de4c5d 4433 /**
group-onsemi 0:098463de4c5d 4434 * @brief Output Compare callback in non blocking mode
group-onsemi 0:098463de4c5d 4435 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4436 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 4437 * @retval None
group-onsemi 0:098463de4c5d 4438 */
group-onsemi 0:098463de4c5d 4439 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 4440 {
group-onsemi 0:098463de4c5d 4441 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 4442 UNUSED(htim);
group-onsemi 0:098463de4c5d 4443
group-onsemi 0:098463de4c5d 4444 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 4445 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
group-onsemi 0:098463de4c5d 4446 */
group-onsemi 0:098463de4c5d 4447 }
group-onsemi 0:098463de4c5d 4448 /**
group-onsemi 0:098463de4c5d 4449 * @brief Input Capture callback in non blocking mode
group-onsemi 0:098463de4c5d 4450 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4451 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 4452 * @retval None
group-onsemi 0:098463de4c5d 4453 */
group-onsemi 0:098463de4c5d 4454 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 4455 {
group-onsemi 0:098463de4c5d 4456 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 4457 UNUSED(htim);
group-onsemi 0:098463de4c5d 4458
group-onsemi 0:098463de4c5d 4459 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 4460 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
group-onsemi 0:098463de4c5d 4461 */
group-onsemi 0:098463de4c5d 4462 }
group-onsemi 0:098463de4c5d 4463
group-onsemi 0:098463de4c5d 4464 /**
group-onsemi 0:098463de4c5d 4465 * @brief PWM Pulse finished callback in non blocking mode
group-onsemi 0:098463de4c5d 4466 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4467 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 4468 * @retval None
group-onsemi 0:098463de4c5d 4469 */
group-onsemi 0:098463de4c5d 4470 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 4471 {
group-onsemi 0:098463de4c5d 4472 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 4473 UNUSED(htim);
group-onsemi 0:098463de4c5d 4474
group-onsemi 0:098463de4c5d 4475 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 4476 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
group-onsemi 0:098463de4c5d 4477 */
group-onsemi 0:098463de4c5d 4478 }
group-onsemi 0:098463de4c5d 4479
group-onsemi 0:098463de4c5d 4480 /**
group-onsemi 0:098463de4c5d 4481 * @brief Hall Trigger detection callback in non blocking mode
group-onsemi 0:098463de4c5d 4482 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4483 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 4484 * @retval None
group-onsemi 0:098463de4c5d 4485 */
group-onsemi 0:098463de4c5d 4486 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 4487 {
group-onsemi 0:098463de4c5d 4488 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 4489 UNUSED(htim);
group-onsemi 0:098463de4c5d 4490
group-onsemi 0:098463de4c5d 4491 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 4492 the HAL_TIM_TriggerCallback could be implemented in the user file
group-onsemi 0:098463de4c5d 4493 */
group-onsemi 0:098463de4c5d 4494 }
group-onsemi 0:098463de4c5d 4495
group-onsemi 0:098463de4c5d 4496 /**
group-onsemi 0:098463de4c5d 4497 * @brief Timer error callback in non blocking mode
group-onsemi 0:098463de4c5d 4498 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4499 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 4500 * @retval None
group-onsemi 0:098463de4c5d 4501 */
group-onsemi 0:098463de4c5d 4502 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 4503 {
group-onsemi 0:098463de4c5d 4504 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 4505 UNUSED(htim);
group-onsemi 0:098463de4c5d 4506
group-onsemi 0:098463de4c5d 4507 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 4508 the HAL_TIM_ErrorCallback could be implemented in the user file
group-onsemi 0:098463de4c5d 4509 */
group-onsemi 0:098463de4c5d 4510 }
group-onsemi 0:098463de4c5d 4511
group-onsemi 0:098463de4c5d 4512 /**
group-onsemi 0:098463de4c5d 4513 * @}
group-onsemi 0:098463de4c5d 4514 */
group-onsemi 0:098463de4c5d 4515
group-onsemi 0:098463de4c5d 4516 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
group-onsemi 0:098463de4c5d 4517 * @brief Peripheral State functions
group-onsemi 0:098463de4c5d 4518 *
group-onsemi 0:098463de4c5d 4519 @verbatim
group-onsemi 0:098463de4c5d 4520 ==============================================================================
group-onsemi 0:098463de4c5d 4521 ##### Peripheral State functions #####
group-onsemi 0:098463de4c5d 4522 ==============================================================================
group-onsemi 0:098463de4c5d 4523 [..]
group-onsemi 0:098463de4c5d 4524 This subsection permits to get in run-time the status of the peripheral
group-onsemi 0:098463de4c5d 4525 and the data flow.
group-onsemi 0:098463de4c5d 4526
group-onsemi 0:098463de4c5d 4527 @endverbatim
group-onsemi 0:098463de4c5d 4528 * @{
group-onsemi 0:098463de4c5d 4529 */
group-onsemi 0:098463de4c5d 4530
group-onsemi 0:098463de4c5d 4531 /**
group-onsemi 0:098463de4c5d 4532 * @brief Return the TIM Base state
group-onsemi 0:098463de4c5d 4533 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4534 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 4535 * @retval HAL state
group-onsemi 0:098463de4c5d 4536 */
group-onsemi 0:098463de4c5d 4537 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 4538 {
group-onsemi 0:098463de4c5d 4539 return htim->State;
group-onsemi 0:098463de4c5d 4540 }
group-onsemi 0:098463de4c5d 4541
group-onsemi 0:098463de4c5d 4542 /**
group-onsemi 0:098463de4c5d 4543 * @brief Return the TIM OC state
group-onsemi 0:098463de4c5d 4544 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4545 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 4546 * @retval HAL state
group-onsemi 0:098463de4c5d 4547 */
group-onsemi 0:098463de4c5d 4548 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 4549 {
group-onsemi 0:098463de4c5d 4550 return htim->State;
group-onsemi 0:098463de4c5d 4551 }
group-onsemi 0:098463de4c5d 4552
group-onsemi 0:098463de4c5d 4553 /**
group-onsemi 0:098463de4c5d 4554 * @brief Return the TIM PWM state
group-onsemi 0:098463de4c5d 4555 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4556 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 4557 * @retval HAL state
group-onsemi 0:098463de4c5d 4558 */
group-onsemi 0:098463de4c5d 4559 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 4560 {
group-onsemi 0:098463de4c5d 4561 return htim->State;
group-onsemi 0:098463de4c5d 4562 }
group-onsemi 0:098463de4c5d 4563
group-onsemi 0:098463de4c5d 4564 /**
group-onsemi 0:098463de4c5d 4565 * @brief Return the TIM Input Capture state
group-onsemi 0:098463de4c5d 4566 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4567 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 4568 * @retval HAL state
group-onsemi 0:098463de4c5d 4569 */
group-onsemi 0:098463de4c5d 4570 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 4571 {
group-onsemi 0:098463de4c5d 4572 return htim->State;
group-onsemi 0:098463de4c5d 4573 }
group-onsemi 0:098463de4c5d 4574
group-onsemi 0:098463de4c5d 4575 /**
group-onsemi 0:098463de4c5d 4576 * @brief Return the TIM One Pulse Mode state
group-onsemi 0:098463de4c5d 4577 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4578 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 4579 * @retval HAL state
group-onsemi 0:098463de4c5d 4580 */
group-onsemi 0:098463de4c5d 4581 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 4582 {
group-onsemi 0:098463de4c5d 4583 return htim->State;
group-onsemi 0:098463de4c5d 4584 }
group-onsemi 0:098463de4c5d 4585
group-onsemi 0:098463de4c5d 4586 /**
group-onsemi 0:098463de4c5d 4587 * @brief Return the TIM Encoder Mode state
group-onsemi 0:098463de4c5d 4588 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4589 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 4590 * @retval HAL state
group-onsemi 0:098463de4c5d 4591 */
group-onsemi 0:098463de4c5d 4592 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
group-onsemi 0:098463de4c5d 4593 {
group-onsemi 0:098463de4c5d 4594 return htim->State;
group-onsemi 0:098463de4c5d 4595 }
group-onsemi 0:098463de4c5d 4596
group-onsemi 0:098463de4c5d 4597 /**
group-onsemi 0:098463de4c5d 4598 * @}
group-onsemi 0:098463de4c5d 4599 */
group-onsemi 0:098463de4c5d 4600
group-onsemi 0:098463de4c5d 4601 /**
group-onsemi 0:098463de4c5d 4602 * @brief TIM DMA error callback
group-onsemi 0:098463de4c5d 4603 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4604 * the configuration information for the specified DMA module.
group-onsemi 0:098463de4c5d 4605 * @retval None
group-onsemi 0:098463de4c5d 4606 */
group-onsemi 0:098463de4c5d 4607 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
group-onsemi 0:098463de4c5d 4608 {
group-onsemi 0:098463de4c5d 4609 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
group-onsemi 0:098463de4c5d 4610
group-onsemi 0:098463de4c5d 4611 htim->State= HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 4612
group-onsemi 0:098463de4c5d 4613 HAL_TIM_ErrorCallback(htim);
group-onsemi 0:098463de4c5d 4614 }
group-onsemi 0:098463de4c5d 4615
group-onsemi 0:098463de4c5d 4616 /**
group-onsemi 0:098463de4c5d 4617 * @brief TIM DMA Delay Pulse complete callback.
group-onsemi 0:098463de4c5d 4618 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4619 * the configuration information for the specified DMA module.
group-onsemi 0:098463de4c5d 4620 * @retval None
group-onsemi 0:098463de4c5d 4621 */
group-onsemi 0:098463de4c5d 4622 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
group-onsemi 0:098463de4c5d 4623 {
group-onsemi 0:098463de4c5d 4624 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
group-onsemi 0:098463de4c5d 4625
group-onsemi 0:098463de4c5d 4626 htim->State= HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 4627
group-onsemi 0:098463de4c5d 4628 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
group-onsemi 0:098463de4c5d 4629 {
group-onsemi 0:098463de4c5d 4630 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
group-onsemi 0:098463de4c5d 4631 }
group-onsemi 0:098463de4c5d 4632 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
group-onsemi 0:098463de4c5d 4633 {
group-onsemi 0:098463de4c5d 4634 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
group-onsemi 0:098463de4c5d 4635 }
group-onsemi 0:098463de4c5d 4636 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
group-onsemi 0:098463de4c5d 4637 {
group-onsemi 0:098463de4c5d 4638 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
group-onsemi 0:098463de4c5d 4639 }
group-onsemi 0:098463de4c5d 4640 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
group-onsemi 0:098463de4c5d 4641 {
group-onsemi 0:098463de4c5d 4642 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
group-onsemi 0:098463de4c5d 4643 }
group-onsemi 0:098463de4c5d 4644
group-onsemi 0:098463de4c5d 4645 HAL_TIM_PWM_PulseFinishedCallback(htim);
group-onsemi 0:098463de4c5d 4646
group-onsemi 0:098463de4c5d 4647 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
group-onsemi 0:098463de4c5d 4648 }
group-onsemi 0:098463de4c5d 4649 /**
group-onsemi 0:098463de4c5d 4650 * @brief TIM DMA Capture complete callback.
group-onsemi 0:098463de4c5d 4651 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4652 * the configuration information for the specified DMA module.
group-onsemi 0:098463de4c5d 4653 * @retval None
group-onsemi 0:098463de4c5d 4654 */
group-onsemi 0:098463de4c5d 4655 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
group-onsemi 0:098463de4c5d 4656 {
group-onsemi 0:098463de4c5d 4657 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
group-onsemi 0:098463de4c5d 4658
group-onsemi 0:098463de4c5d 4659 htim->State= HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 4660
group-onsemi 0:098463de4c5d 4661 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
group-onsemi 0:098463de4c5d 4662 {
group-onsemi 0:098463de4c5d 4663 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
group-onsemi 0:098463de4c5d 4664 }
group-onsemi 0:098463de4c5d 4665 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
group-onsemi 0:098463de4c5d 4666 {
group-onsemi 0:098463de4c5d 4667 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
group-onsemi 0:098463de4c5d 4668 }
group-onsemi 0:098463de4c5d 4669 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
group-onsemi 0:098463de4c5d 4670 {
group-onsemi 0:098463de4c5d 4671 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
group-onsemi 0:098463de4c5d 4672 }
group-onsemi 0:098463de4c5d 4673 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
group-onsemi 0:098463de4c5d 4674 {
group-onsemi 0:098463de4c5d 4675 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
group-onsemi 0:098463de4c5d 4676 }
group-onsemi 0:098463de4c5d 4677
group-onsemi 0:098463de4c5d 4678 HAL_TIM_IC_CaptureCallback(htim);
group-onsemi 0:098463de4c5d 4679
group-onsemi 0:098463de4c5d 4680 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
group-onsemi 0:098463de4c5d 4681
group-onsemi 0:098463de4c5d 4682 }
group-onsemi 0:098463de4c5d 4683
group-onsemi 0:098463de4c5d 4684 /**
group-onsemi 0:098463de4c5d 4685 * @brief TIM DMA Period Elapse complete callback.
group-onsemi 0:098463de4c5d 4686 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4687 * the configuration information for the specified DMA module.
group-onsemi 0:098463de4c5d 4688 * @retval None
group-onsemi 0:098463de4c5d 4689 */
group-onsemi 0:098463de4c5d 4690 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
group-onsemi 0:098463de4c5d 4691 {
group-onsemi 0:098463de4c5d 4692 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
group-onsemi 0:098463de4c5d 4693
group-onsemi 0:098463de4c5d 4694 htim->State= HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 4695
group-onsemi 0:098463de4c5d 4696 HAL_TIM_PeriodElapsedCallback(htim);
group-onsemi 0:098463de4c5d 4697 }
group-onsemi 0:098463de4c5d 4698
group-onsemi 0:098463de4c5d 4699 /**
group-onsemi 0:098463de4c5d 4700 * @brief TIM DMA Trigger callback.
group-onsemi 0:098463de4c5d 4701 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 4702 * the configuration information for the specified DMA module.
group-onsemi 0:098463de4c5d 4703 * @retval None
group-onsemi 0:098463de4c5d 4704 */
group-onsemi 0:098463de4c5d 4705 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
group-onsemi 0:098463de4c5d 4706 {
group-onsemi 0:098463de4c5d 4707 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
group-onsemi 0:098463de4c5d 4708
group-onsemi 0:098463de4c5d 4709 htim->State= HAL_TIM_STATE_READY;
group-onsemi 0:098463de4c5d 4710
group-onsemi 0:098463de4c5d 4711 HAL_TIM_TriggerCallback(htim);
group-onsemi 0:098463de4c5d 4712 }
group-onsemi 0:098463de4c5d 4713
group-onsemi 0:098463de4c5d 4714 /**
group-onsemi 0:098463de4c5d 4715 * @brief Time Base configuration
group-onsemi 0:098463de4c5d 4716 * @param TIMx: TIM peripheral
group-onsemi 0:098463de4c5d 4717 * @param Structure: pointer on TIM Time Base required parameters
group-onsemi 0:098463de4c5d 4718 * @retval None
group-onsemi 0:098463de4c5d 4719 */
group-onsemi 0:098463de4c5d 4720 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
group-onsemi 0:098463de4c5d 4721 {
group-onsemi 0:098463de4c5d 4722 uint32_t tmpcr1 = 0;
group-onsemi 0:098463de4c5d 4723 tmpcr1 = TIMx->CR1;
group-onsemi 0:098463de4c5d 4724
group-onsemi 0:098463de4c5d 4725 /* Set TIM Time Base Unit parameters ---------------------------------------*/
group-onsemi 0:098463de4c5d 4726 if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
group-onsemi 0:098463de4c5d 4727 {
group-onsemi 0:098463de4c5d 4728 /* Select the Counter Mode */
group-onsemi 0:098463de4c5d 4729 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
group-onsemi 0:098463de4c5d 4730 tmpcr1 |= Structure->CounterMode;
group-onsemi 0:098463de4c5d 4731 }
group-onsemi 0:098463de4c5d 4732
group-onsemi 0:098463de4c5d 4733 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
group-onsemi 0:098463de4c5d 4734 {
group-onsemi 0:098463de4c5d 4735 /* Set the clock division */
group-onsemi 0:098463de4c5d 4736 tmpcr1 &= ~TIM_CR1_CKD;
group-onsemi 0:098463de4c5d 4737 tmpcr1 |= (uint32_t)Structure->ClockDivision;
group-onsemi 0:098463de4c5d 4738 }
group-onsemi 0:098463de4c5d 4739
group-onsemi 0:098463de4c5d 4740 TIMx->CR1 = tmpcr1;
group-onsemi 0:098463de4c5d 4741
group-onsemi 0:098463de4c5d 4742 /* Set the Auto-reload value */
group-onsemi 0:098463de4c5d 4743 TIMx->ARR = (uint32_t)Structure->Period ;
group-onsemi 0:098463de4c5d 4744
group-onsemi 0:098463de4c5d 4745 /* Set the Prescaler value */
group-onsemi 0:098463de4c5d 4746 TIMx->PSC = (uint32_t)Structure->Prescaler;
group-onsemi 0:098463de4c5d 4747
group-onsemi 0:098463de4c5d 4748 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
group-onsemi 0:098463de4c5d 4749 {
group-onsemi 0:098463de4c5d 4750 /* Set the Repetition Counter value */
group-onsemi 0:098463de4c5d 4751 TIMx->RCR = Structure->RepetitionCounter;
group-onsemi 0:098463de4c5d 4752 }
group-onsemi 0:098463de4c5d 4753
group-onsemi 0:098463de4c5d 4754 /* Generate an update event to reload the Prescaler
group-onsemi 0:098463de4c5d 4755 and the repetition counter(only for TIM1 and TIM8) value immediately */
group-onsemi 0:098463de4c5d 4756 TIMx->EGR = TIM_EGR_UG;
group-onsemi 0:098463de4c5d 4757 }
group-onsemi 0:098463de4c5d 4758
group-onsemi 0:098463de4c5d 4759 /**
group-onsemi 0:098463de4c5d 4760 * @brief Time Output Compare 1 configuration
group-onsemi 0:098463de4c5d 4761 * @param TIMx to select the TIM peripheral
group-onsemi 0:098463de4c5d 4762 * @param OC_Config: The output configuration structure
group-onsemi 0:098463de4c5d 4763 * @retval None
group-onsemi 0:098463de4c5d 4764 */
group-onsemi 0:098463de4c5d 4765 void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
group-onsemi 0:098463de4c5d 4766 {
group-onsemi 0:098463de4c5d 4767 uint32_t tmpccmrx = 0;
group-onsemi 0:098463de4c5d 4768 uint32_t tmpccer = 0;
group-onsemi 0:098463de4c5d 4769 uint32_t tmpcr2 = 0;
group-onsemi 0:098463de4c5d 4770
group-onsemi 0:098463de4c5d 4771 /* Disable the Channel 1: Reset the CC1E Bit */
group-onsemi 0:098463de4c5d 4772 TIMx->CCER &= ~TIM_CCER_CC1E;
group-onsemi 0:098463de4c5d 4773
group-onsemi 0:098463de4c5d 4774 /* Get the TIMx CCER register value */
group-onsemi 0:098463de4c5d 4775 tmpccer = TIMx->CCER;
group-onsemi 0:098463de4c5d 4776 /* Get the TIMx CR2 register value */
group-onsemi 0:098463de4c5d 4777 tmpcr2 = TIMx->CR2;
group-onsemi 0:098463de4c5d 4778
group-onsemi 0:098463de4c5d 4779 /* Get the TIMx CCMR1 register value */
group-onsemi 0:098463de4c5d 4780 tmpccmrx = TIMx->CCMR1;
group-onsemi 0:098463de4c5d 4781
group-onsemi 0:098463de4c5d 4782 /* Reset the Output Compare Mode Bits */
group-onsemi 0:098463de4c5d 4783 tmpccmrx &= ~TIM_CCMR1_OC1M;
group-onsemi 0:098463de4c5d 4784 tmpccmrx &= ~TIM_CCMR1_CC1S;
group-onsemi 0:098463de4c5d 4785 /* Select the Output Compare Mode */
group-onsemi 0:098463de4c5d 4786 tmpccmrx |= OC_Config->OCMode;
group-onsemi 0:098463de4c5d 4787
group-onsemi 0:098463de4c5d 4788 /* Reset the Output Polarity level */
group-onsemi 0:098463de4c5d 4789 tmpccer &= ~TIM_CCER_CC1P;
group-onsemi 0:098463de4c5d 4790 /* Set the Output Compare Polarity */
group-onsemi 0:098463de4c5d 4791 tmpccer |= OC_Config->OCPolarity;
group-onsemi 0:098463de4c5d 4792
group-onsemi 0:098463de4c5d 4793
group-onsemi 0:098463de4c5d 4794 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
group-onsemi 0:098463de4c5d 4795 {
group-onsemi 0:098463de4c5d 4796 /* Reset the Output N Polarity level */
group-onsemi 0:098463de4c5d 4797 tmpccer &= ~TIM_CCER_CC1NP;
group-onsemi 0:098463de4c5d 4798 /* Set the Output N Polarity */
group-onsemi 0:098463de4c5d 4799 tmpccer |= OC_Config->OCNPolarity;
group-onsemi 0:098463de4c5d 4800 /* Reset the Output N State */
group-onsemi 0:098463de4c5d 4801 tmpccer &= ~TIM_CCER_CC1NE;
group-onsemi 0:098463de4c5d 4802
group-onsemi 0:098463de4c5d 4803 /* Reset the Output Compare and Output Compare N IDLE State */
group-onsemi 0:098463de4c5d 4804 tmpcr2 &= ~TIM_CR2_OIS1;
group-onsemi 0:098463de4c5d 4805 tmpcr2 &= ~TIM_CR2_OIS1N;
group-onsemi 0:098463de4c5d 4806 /* Set the Output Idle state */
group-onsemi 0:098463de4c5d 4807 tmpcr2 |= OC_Config->OCIdleState;
group-onsemi 0:098463de4c5d 4808 /* Set the Output N Idle state */
group-onsemi 0:098463de4c5d 4809 tmpcr2 |= OC_Config->OCNIdleState;
group-onsemi 0:098463de4c5d 4810 }
group-onsemi 0:098463de4c5d 4811 /* Write to TIMx CR2 */
group-onsemi 0:098463de4c5d 4812 TIMx->CR2 = tmpcr2;
group-onsemi 0:098463de4c5d 4813
group-onsemi 0:098463de4c5d 4814 /* Write to TIMx CCMR1 */
group-onsemi 0:098463de4c5d 4815 TIMx->CCMR1 = tmpccmrx;
group-onsemi 0:098463de4c5d 4816
group-onsemi 0:098463de4c5d 4817 /* Set the Capture Compare Register value */
group-onsemi 0:098463de4c5d 4818 TIMx->CCR1 = OC_Config->Pulse;
group-onsemi 0:098463de4c5d 4819
group-onsemi 0:098463de4c5d 4820 /* Write to TIMx CCER */
group-onsemi 0:098463de4c5d 4821 TIMx->CCER = tmpccer;
group-onsemi 0:098463de4c5d 4822 }
group-onsemi 0:098463de4c5d 4823
group-onsemi 0:098463de4c5d 4824 /**
group-onsemi 0:098463de4c5d 4825 * @brief Time Output Compare 2 configuration
group-onsemi 0:098463de4c5d 4826 * @param TIMx to select the TIM peripheral
group-onsemi 0:098463de4c5d 4827 * @param OC_Config: The output configuration structure
group-onsemi 0:098463de4c5d 4828 * @retval None
group-onsemi 0:098463de4c5d 4829 */
group-onsemi 0:098463de4c5d 4830 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
group-onsemi 0:098463de4c5d 4831 {
group-onsemi 0:098463de4c5d 4832 uint32_t tmpccmrx = 0;
group-onsemi 0:098463de4c5d 4833 uint32_t tmpccer = 0;
group-onsemi 0:098463de4c5d 4834 uint32_t tmpcr2 = 0;
group-onsemi 0:098463de4c5d 4835
group-onsemi 0:098463de4c5d 4836 /* Disable the Channel 2: Reset the CC2E Bit */
group-onsemi 0:098463de4c5d 4837 TIMx->CCER &= ~TIM_CCER_CC2E;
group-onsemi 0:098463de4c5d 4838
group-onsemi 0:098463de4c5d 4839 /* Get the TIMx CCER register value */
group-onsemi 0:098463de4c5d 4840 tmpccer = TIMx->CCER;
group-onsemi 0:098463de4c5d 4841 /* Get the TIMx CR2 register value */
group-onsemi 0:098463de4c5d 4842 tmpcr2 = TIMx->CR2;
group-onsemi 0:098463de4c5d 4843
group-onsemi 0:098463de4c5d 4844 /* Get the TIMx CCMR1 register value */
group-onsemi 0:098463de4c5d 4845 tmpccmrx = TIMx->CCMR1;
group-onsemi 0:098463de4c5d 4846
group-onsemi 0:098463de4c5d 4847 /* Reset the Output Compare mode and Capture/Compare selection Bits */
group-onsemi 0:098463de4c5d 4848 tmpccmrx &= ~TIM_CCMR1_OC2M;
group-onsemi 0:098463de4c5d 4849 tmpccmrx &= ~TIM_CCMR1_CC2S;
group-onsemi 0:098463de4c5d 4850
group-onsemi 0:098463de4c5d 4851 /* Select the Output Compare Mode */
group-onsemi 0:098463de4c5d 4852 tmpccmrx |= (OC_Config->OCMode << 8);
group-onsemi 0:098463de4c5d 4853
group-onsemi 0:098463de4c5d 4854 /* Reset the Output Polarity level */
group-onsemi 0:098463de4c5d 4855 tmpccer &= ~TIM_CCER_CC2P;
group-onsemi 0:098463de4c5d 4856 /* Set the Output Compare Polarity */
group-onsemi 0:098463de4c5d 4857 tmpccer |= (OC_Config->OCPolarity << 4);
group-onsemi 0:098463de4c5d 4858
group-onsemi 0:098463de4c5d 4859 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
group-onsemi 0:098463de4c5d 4860 {
group-onsemi 0:098463de4c5d 4861 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
group-onsemi 0:098463de4c5d 4862
group-onsemi 0:098463de4c5d 4863 /* Reset the Output N Polarity level */
group-onsemi 0:098463de4c5d 4864 tmpccer &= ~TIM_CCER_CC2NP;
group-onsemi 0:098463de4c5d 4865 /* Set the Output N Polarity */
group-onsemi 0:098463de4c5d 4866 tmpccer |= (OC_Config->OCNPolarity << 4);
group-onsemi 0:098463de4c5d 4867 /* Reset the Output N State */
group-onsemi 0:098463de4c5d 4868 tmpccer &= ~TIM_CCER_CC2NE;
group-onsemi 0:098463de4c5d 4869
group-onsemi 0:098463de4c5d 4870 /* Reset the Output Compare and Output Compare N IDLE State */
group-onsemi 0:098463de4c5d 4871 tmpcr2 &= ~TIM_CR2_OIS2;
group-onsemi 0:098463de4c5d 4872 tmpcr2 &= ~TIM_CR2_OIS2N;
group-onsemi 0:098463de4c5d 4873 /* Set the Output Idle state */
group-onsemi 0:098463de4c5d 4874 tmpcr2 |= (OC_Config->OCIdleState << 2);
group-onsemi 0:098463de4c5d 4875 /* Set the Output N Idle state */
group-onsemi 0:098463de4c5d 4876 tmpcr2 |= (OC_Config->OCNIdleState << 2);
group-onsemi 0:098463de4c5d 4877 }
group-onsemi 0:098463de4c5d 4878 /* Write to TIMx CR2 */
group-onsemi 0:098463de4c5d 4879 TIMx->CR2 = tmpcr2;
group-onsemi 0:098463de4c5d 4880
group-onsemi 0:098463de4c5d 4881 /* Write to TIMx CCMR1 */
group-onsemi 0:098463de4c5d 4882 TIMx->CCMR1 = tmpccmrx;
group-onsemi 0:098463de4c5d 4883
group-onsemi 0:098463de4c5d 4884 /* Set the Capture Compare Register value */
group-onsemi 0:098463de4c5d 4885 TIMx->CCR2 = OC_Config->Pulse;
group-onsemi 0:098463de4c5d 4886
group-onsemi 0:098463de4c5d 4887 /* Write to TIMx CCER */
group-onsemi 0:098463de4c5d 4888 TIMx->CCER = tmpccer;
group-onsemi 0:098463de4c5d 4889 }
group-onsemi 0:098463de4c5d 4890
group-onsemi 0:098463de4c5d 4891 /**
group-onsemi 0:098463de4c5d 4892 * @brief Time Output Compare 3 configuration
group-onsemi 0:098463de4c5d 4893 * @param TIMx to select the TIM peripheral
group-onsemi 0:098463de4c5d 4894 * @param OC_Config: The output configuration structure
group-onsemi 0:098463de4c5d 4895 * @retval None
group-onsemi 0:098463de4c5d 4896 */
group-onsemi 0:098463de4c5d 4897 void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
group-onsemi 0:098463de4c5d 4898 {
group-onsemi 0:098463de4c5d 4899 uint32_t tmpccmrx = 0;
group-onsemi 0:098463de4c5d 4900 uint32_t tmpccer = 0;
group-onsemi 0:098463de4c5d 4901 uint32_t tmpcr2 = 0;
group-onsemi 0:098463de4c5d 4902
group-onsemi 0:098463de4c5d 4903 /* Disable the Channel 3: Reset the CC2E Bit */
group-onsemi 0:098463de4c5d 4904 TIMx->CCER &= ~TIM_CCER_CC3E;
group-onsemi 0:098463de4c5d 4905
group-onsemi 0:098463de4c5d 4906 /* Get the TIMx CCER register value */
group-onsemi 0:098463de4c5d 4907 tmpccer = TIMx->CCER;
group-onsemi 0:098463de4c5d 4908 /* Get the TIMx CR2 register value */
group-onsemi 0:098463de4c5d 4909 tmpcr2 = TIMx->CR2;
group-onsemi 0:098463de4c5d 4910
group-onsemi 0:098463de4c5d 4911 /* Get the TIMx CCMR2 register value */
group-onsemi 0:098463de4c5d 4912 tmpccmrx = TIMx->CCMR2;
group-onsemi 0:098463de4c5d 4913
group-onsemi 0:098463de4c5d 4914 /* Reset the Output Compare mode and Capture/Compare selection Bits */
group-onsemi 0:098463de4c5d 4915 tmpccmrx &= ~TIM_CCMR2_OC3M;
group-onsemi 0:098463de4c5d 4916 tmpccmrx &= ~TIM_CCMR2_CC3S;
group-onsemi 0:098463de4c5d 4917 /* Select the Output Compare Mode */
group-onsemi 0:098463de4c5d 4918 tmpccmrx |= OC_Config->OCMode;
group-onsemi 0:098463de4c5d 4919
group-onsemi 0:098463de4c5d 4920 /* Reset the Output Polarity level */
group-onsemi 0:098463de4c5d 4921 tmpccer &= ~TIM_CCER_CC3P;
group-onsemi 0:098463de4c5d 4922 /* Set the Output Compare Polarity */
group-onsemi 0:098463de4c5d 4923 tmpccer |= (OC_Config->OCPolarity << 8);
group-onsemi 0:098463de4c5d 4924
group-onsemi 0:098463de4c5d 4925 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
group-onsemi 0:098463de4c5d 4926 {
group-onsemi 0:098463de4c5d 4927 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
group-onsemi 0:098463de4c5d 4928
group-onsemi 0:098463de4c5d 4929 /* Reset the Output N Polarity level */
group-onsemi 0:098463de4c5d 4930 tmpccer &= ~TIM_CCER_CC3NP;
group-onsemi 0:098463de4c5d 4931 /* Set the Output N Polarity */
group-onsemi 0:098463de4c5d 4932 tmpccer |= (OC_Config->OCNPolarity << 8);
group-onsemi 0:098463de4c5d 4933 /* Reset the Output N State */
group-onsemi 0:098463de4c5d 4934 tmpccer &= ~TIM_CCER_CC3NE;
group-onsemi 0:098463de4c5d 4935
group-onsemi 0:098463de4c5d 4936 /* Reset the Output Compare and Output Compare N IDLE State */
group-onsemi 0:098463de4c5d 4937 tmpcr2 &= ~TIM_CR2_OIS3;
group-onsemi 0:098463de4c5d 4938 tmpcr2 &= ~TIM_CR2_OIS3N;
group-onsemi 0:098463de4c5d 4939 /* Set the Output Idle state */
group-onsemi 0:098463de4c5d 4940 tmpcr2 |= (OC_Config->OCIdleState << 4);
group-onsemi 0:098463de4c5d 4941 /* Set the Output N Idle state */
group-onsemi 0:098463de4c5d 4942 tmpcr2 |= (OC_Config->OCNIdleState << 4);
group-onsemi 0:098463de4c5d 4943 }
group-onsemi 0:098463de4c5d 4944 /* Write to TIMx CR2 */
group-onsemi 0:098463de4c5d 4945 TIMx->CR2 = tmpcr2;
group-onsemi 0:098463de4c5d 4946
group-onsemi 0:098463de4c5d 4947 /* Write to TIMx CCMR2 */
group-onsemi 0:098463de4c5d 4948 TIMx->CCMR2 = tmpccmrx;
group-onsemi 0:098463de4c5d 4949
group-onsemi 0:098463de4c5d 4950 /* Set the Capture Compare Register value */
group-onsemi 0:098463de4c5d 4951 TIMx->CCR3 = OC_Config->Pulse;
group-onsemi 0:098463de4c5d 4952
group-onsemi 0:098463de4c5d 4953 /* Write to TIMx CCER */
group-onsemi 0:098463de4c5d 4954 TIMx->CCER = tmpccer;
group-onsemi 0:098463de4c5d 4955 }
group-onsemi 0:098463de4c5d 4956
group-onsemi 0:098463de4c5d 4957 /**
group-onsemi 0:098463de4c5d 4958 * @brief Time Output Compare 4 configuration
group-onsemi 0:098463de4c5d 4959 * @param TIMx to select the TIM peripheral
group-onsemi 0:098463de4c5d 4960 * @param OC_Config: The output configuration structure
group-onsemi 0:098463de4c5d 4961 * @retval None
group-onsemi 0:098463de4c5d 4962 */
group-onsemi 0:098463de4c5d 4963 void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
group-onsemi 0:098463de4c5d 4964 {
group-onsemi 0:098463de4c5d 4965 uint32_t tmpccmrx = 0;
group-onsemi 0:098463de4c5d 4966 uint32_t tmpccer = 0;
group-onsemi 0:098463de4c5d 4967 uint32_t tmpcr2 = 0;
group-onsemi 0:098463de4c5d 4968
group-onsemi 0:098463de4c5d 4969 /* Disable the Channel 4: Reset the CC4E Bit */
group-onsemi 0:098463de4c5d 4970 TIMx->CCER &= ~TIM_CCER_CC4E;
group-onsemi 0:098463de4c5d 4971
group-onsemi 0:098463de4c5d 4972 /* Get the TIMx CCER register value */
group-onsemi 0:098463de4c5d 4973 tmpccer = TIMx->CCER;
group-onsemi 0:098463de4c5d 4974 /* Get the TIMx CR2 register value */
group-onsemi 0:098463de4c5d 4975 tmpcr2 = TIMx->CR2;
group-onsemi 0:098463de4c5d 4976
group-onsemi 0:098463de4c5d 4977 /* Get the TIMx CCMR2 register value */
group-onsemi 0:098463de4c5d 4978 tmpccmrx = TIMx->CCMR2;
group-onsemi 0:098463de4c5d 4979
group-onsemi 0:098463de4c5d 4980 /* Reset the Output Compare mode and Capture/Compare selection Bits */
group-onsemi 0:098463de4c5d 4981 tmpccmrx &= ~TIM_CCMR2_OC4M;
group-onsemi 0:098463de4c5d 4982 tmpccmrx &= ~TIM_CCMR2_CC4S;
group-onsemi 0:098463de4c5d 4983
group-onsemi 0:098463de4c5d 4984 /* Select the Output Compare Mode */
group-onsemi 0:098463de4c5d 4985 tmpccmrx |= (OC_Config->OCMode << 8);
group-onsemi 0:098463de4c5d 4986
group-onsemi 0:098463de4c5d 4987 /* Reset the Output Polarity level */
group-onsemi 0:098463de4c5d 4988 tmpccer &= ~TIM_CCER_CC4P;
group-onsemi 0:098463de4c5d 4989 /* Set the Output Compare Polarity */
group-onsemi 0:098463de4c5d 4990 tmpccer |= (OC_Config->OCPolarity << 12);
group-onsemi 0:098463de4c5d 4991
group-onsemi 0:098463de4c5d 4992 /*if((TIMx == TIM1) || (TIMx == TIM8))*/
group-onsemi 0:098463de4c5d 4993 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
group-onsemi 0:098463de4c5d 4994 {
group-onsemi 0:098463de4c5d 4995 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
group-onsemi 0:098463de4c5d 4996 /* Reset the Output Compare IDLE State */
group-onsemi 0:098463de4c5d 4997 tmpcr2 &= ~TIM_CR2_OIS4;
group-onsemi 0:098463de4c5d 4998 /* Set the Output Idle state */
group-onsemi 0:098463de4c5d 4999 tmpcr2 |= (OC_Config->OCIdleState << 6);
group-onsemi 0:098463de4c5d 5000 }
group-onsemi 0:098463de4c5d 5001 /* Write to TIMx CR2 */
group-onsemi 0:098463de4c5d 5002 TIMx->CR2 = tmpcr2;
group-onsemi 0:098463de4c5d 5003
group-onsemi 0:098463de4c5d 5004 /* Write to TIMx CCMR2 */
group-onsemi 0:098463de4c5d 5005 TIMx->CCMR2 = tmpccmrx;
group-onsemi 0:098463de4c5d 5006
group-onsemi 0:098463de4c5d 5007 /* Set the Capture Compare Register value */
group-onsemi 0:098463de4c5d 5008 TIMx->CCR4 = OC_Config->Pulse;
group-onsemi 0:098463de4c5d 5009
group-onsemi 0:098463de4c5d 5010 /* Write to TIMx CCER */
group-onsemi 0:098463de4c5d 5011 TIMx->CCER = tmpccer;
group-onsemi 0:098463de4c5d 5012 }
group-onsemi 0:098463de4c5d 5013
group-onsemi 0:098463de4c5d 5014 /**
group-onsemi 0:098463de4c5d 5015 * @brief Time Output Compare 4 configuration
group-onsemi 0:098463de4c5d 5016 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 5017 * the configuration information for TIM module.
group-onsemi 0:098463de4c5d 5018 * @param sSlaveConfig: The slave configuration structure
group-onsemi 0:098463de4c5d 5019 * @retval None
group-onsemi 0:098463de4c5d 5020 */
group-onsemi 0:098463de4c5d 5021 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
group-onsemi 0:098463de4c5d 5022 TIM_SlaveConfigTypeDef * sSlaveConfig)
group-onsemi 0:098463de4c5d 5023 {
group-onsemi 0:098463de4c5d 5024 uint32_t tmpsmcr = 0;
group-onsemi 0:098463de4c5d 5025 uint32_t tmpccmr1 = 0;
group-onsemi 0:098463de4c5d 5026 uint32_t tmpccer = 0;
group-onsemi 0:098463de4c5d 5027
group-onsemi 0:098463de4c5d 5028 /* Get the TIMx SMCR register value */
group-onsemi 0:098463de4c5d 5029 tmpsmcr = htim->Instance->SMCR;
group-onsemi 0:098463de4c5d 5030
group-onsemi 0:098463de4c5d 5031 /* Reset the Trigger Selection Bits */
group-onsemi 0:098463de4c5d 5032 tmpsmcr &= ~TIM_SMCR_TS;
group-onsemi 0:098463de4c5d 5033 /* Set the Input Trigger source */
group-onsemi 0:098463de4c5d 5034 tmpsmcr |= sSlaveConfig->InputTrigger;
group-onsemi 0:098463de4c5d 5035
group-onsemi 0:098463de4c5d 5036 /* Reset the slave mode Bits */
group-onsemi 0:098463de4c5d 5037 tmpsmcr &= ~TIM_SMCR_SMS;
group-onsemi 0:098463de4c5d 5038 /* Set the slave mode */
group-onsemi 0:098463de4c5d 5039 tmpsmcr |= sSlaveConfig->SlaveMode;
group-onsemi 0:098463de4c5d 5040
group-onsemi 0:098463de4c5d 5041 /* Write to TIMx SMCR */
group-onsemi 0:098463de4c5d 5042 htim->Instance->SMCR = tmpsmcr;
group-onsemi 0:098463de4c5d 5043
group-onsemi 0:098463de4c5d 5044 /* Configure the trigger prescaler, filter, and polarity */
group-onsemi 0:098463de4c5d 5045 switch (sSlaveConfig->InputTrigger)
group-onsemi 0:098463de4c5d 5046 {
group-onsemi 0:098463de4c5d 5047 case TIM_TS_ETRF:
group-onsemi 0:098463de4c5d 5048 {
group-onsemi 0:098463de4c5d 5049 /* Check the parameters */
group-onsemi 0:098463de4c5d 5050 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 5051 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
group-onsemi 0:098463de4c5d 5052 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
group-onsemi 0:098463de4c5d 5053 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
group-onsemi 0:098463de4c5d 5054 /* Configure the ETR Trigger source */
group-onsemi 0:098463de4c5d 5055 TIM_ETR_SetConfig(htim->Instance,
group-onsemi 0:098463de4c5d 5056 sSlaveConfig->TriggerPrescaler,
group-onsemi 0:098463de4c5d 5057 sSlaveConfig->TriggerPolarity,
group-onsemi 0:098463de4c5d 5058 sSlaveConfig->TriggerFilter);
group-onsemi 0:098463de4c5d 5059 }
group-onsemi 0:098463de4c5d 5060 break;
group-onsemi 0:098463de4c5d 5061
group-onsemi 0:098463de4c5d 5062 case TIM_TS_TI1F_ED:
group-onsemi 0:098463de4c5d 5063 {
group-onsemi 0:098463de4c5d 5064 /* Check the parameters */
group-onsemi 0:098463de4c5d 5065 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 5066 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
group-onsemi 0:098463de4c5d 5067 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
group-onsemi 0:098463de4c5d 5068
group-onsemi 0:098463de4c5d 5069 /* Disable the Channel 1: Reset the CC1E Bit */
group-onsemi 0:098463de4c5d 5070 tmpccer = htim->Instance->CCER;
group-onsemi 0:098463de4c5d 5071 htim->Instance->CCER &= ~TIM_CCER_CC1E;
group-onsemi 0:098463de4c5d 5072 tmpccmr1 = htim->Instance->CCMR1;
group-onsemi 0:098463de4c5d 5073
group-onsemi 0:098463de4c5d 5074 /* Set the filter */
group-onsemi 0:098463de4c5d 5075 tmpccmr1 &= ~TIM_CCMR1_IC1F;
group-onsemi 0:098463de4c5d 5076 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
group-onsemi 0:098463de4c5d 5077
group-onsemi 0:098463de4c5d 5078 /* Write to TIMx CCMR1 and CCER registers */
group-onsemi 0:098463de4c5d 5079 htim->Instance->CCMR1 = tmpccmr1;
group-onsemi 0:098463de4c5d 5080 htim->Instance->CCER = tmpccer;
group-onsemi 0:098463de4c5d 5081
group-onsemi 0:098463de4c5d 5082 }
group-onsemi 0:098463de4c5d 5083 break;
group-onsemi 0:098463de4c5d 5084
group-onsemi 0:098463de4c5d 5085 case TIM_TS_TI1FP1:
group-onsemi 0:098463de4c5d 5086 {
group-onsemi 0:098463de4c5d 5087 /* Check the parameters */
group-onsemi 0:098463de4c5d 5088 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 5089 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
group-onsemi 0:098463de4c5d 5090 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
group-onsemi 0:098463de4c5d 5091
group-onsemi 0:098463de4c5d 5092 /* Configure TI1 Filter and Polarity */
group-onsemi 0:098463de4c5d 5093 TIM_TI1_ConfigInputStage(htim->Instance,
group-onsemi 0:098463de4c5d 5094 sSlaveConfig->TriggerPolarity,
group-onsemi 0:098463de4c5d 5095 sSlaveConfig->TriggerFilter);
group-onsemi 0:098463de4c5d 5096 }
group-onsemi 0:098463de4c5d 5097 break;
group-onsemi 0:098463de4c5d 5098
group-onsemi 0:098463de4c5d 5099 case TIM_TS_TI2FP2:
group-onsemi 0:098463de4c5d 5100 {
group-onsemi 0:098463de4c5d 5101 /* Check the parameters */
group-onsemi 0:098463de4c5d 5102 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 5103 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
group-onsemi 0:098463de4c5d 5104 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
group-onsemi 0:098463de4c5d 5105
group-onsemi 0:098463de4c5d 5106 /* Configure TI2 Filter and Polarity */
group-onsemi 0:098463de4c5d 5107 TIM_TI2_ConfigInputStage(htim->Instance,
group-onsemi 0:098463de4c5d 5108 sSlaveConfig->TriggerPolarity,
group-onsemi 0:098463de4c5d 5109 sSlaveConfig->TriggerFilter);
group-onsemi 0:098463de4c5d 5110 }
group-onsemi 0:098463de4c5d 5111 break;
group-onsemi 0:098463de4c5d 5112
group-onsemi 0:098463de4c5d 5113 case TIM_TS_ITR0:
group-onsemi 0:098463de4c5d 5114 {
group-onsemi 0:098463de4c5d 5115 /* Check the parameter */
group-onsemi 0:098463de4c5d 5116 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 5117 }
group-onsemi 0:098463de4c5d 5118 break;
group-onsemi 0:098463de4c5d 5119
group-onsemi 0:098463de4c5d 5120 case TIM_TS_ITR1:
group-onsemi 0:098463de4c5d 5121 {
group-onsemi 0:098463de4c5d 5122 /* Check the parameter */
group-onsemi 0:098463de4c5d 5123 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 5124 }
group-onsemi 0:098463de4c5d 5125 break;
group-onsemi 0:098463de4c5d 5126
group-onsemi 0:098463de4c5d 5127 case TIM_TS_ITR2:
group-onsemi 0:098463de4c5d 5128 {
group-onsemi 0:098463de4c5d 5129 /* Check the parameter */
group-onsemi 0:098463de4c5d 5130 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 5131 }
group-onsemi 0:098463de4c5d 5132 break;
group-onsemi 0:098463de4c5d 5133
group-onsemi 0:098463de4c5d 5134 case TIM_TS_ITR3:
group-onsemi 0:098463de4c5d 5135 {
group-onsemi 0:098463de4c5d 5136 /* Check the parameter */
group-onsemi 0:098463de4c5d 5137 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
group-onsemi 0:098463de4c5d 5138 }
group-onsemi 0:098463de4c5d 5139 break;
group-onsemi 0:098463de4c5d 5140
group-onsemi 0:098463de4c5d 5141 default:
group-onsemi 0:098463de4c5d 5142 break;
group-onsemi 0:098463de4c5d 5143 }
group-onsemi 0:098463de4c5d 5144 }
group-onsemi 0:098463de4c5d 5145
group-onsemi 0:098463de4c5d 5146 /**
group-onsemi 0:098463de4c5d 5147 * @brief Configure the TI1 as Input.
group-onsemi 0:098463de4c5d 5148 * @param TIMx to select the TIM peripheral.
group-onsemi 0:098463de4c5d 5149 * @param TIM_ICPolarity : The Input Polarity.
group-onsemi 0:098463de4c5d 5150 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 5151 * @arg TIM_ICPolarity_Rising
group-onsemi 0:098463de4c5d 5152 * @arg TIM_ICPolarity_Falling
group-onsemi 0:098463de4c5d 5153 * @arg TIM_ICPolarity_BothEdge
group-onsemi 0:098463de4c5d 5154 * @param TIM_ICSelection: specifies the input to be used.
group-onsemi 0:098463de4c5d 5155 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 5156 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
group-onsemi 0:098463de4c5d 5157 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
group-onsemi 0:098463de4c5d 5158 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
group-onsemi 0:098463de4c5d 5159 * @param TIM_ICFilter: Specifies the Input Capture Filter.
group-onsemi 0:098463de4c5d 5160 * This parameter must be a value between 0x00 and 0x0F.
group-onsemi 0:098463de4c5d 5161 * @retval None
group-onsemi 0:098463de4c5d 5162 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
group-onsemi 0:098463de4c5d 5163 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
group-onsemi 0:098463de4c5d 5164 * protected against un-initialized filter and polarity values.
group-onsemi 0:098463de4c5d 5165 */
group-onsemi 0:098463de4c5d 5166 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
group-onsemi 0:098463de4c5d 5167 uint32_t TIM_ICFilter)
group-onsemi 0:098463de4c5d 5168 {
group-onsemi 0:098463de4c5d 5169 uint32_t tmpccmr1 = 0;
group-onsemi 0:098463de4c5d 5170 uint32_t tmpccer = 0;
group-onsemi 0:098463de4c5d 5171
group-onsemi 0:098463de4c5d 5172 /* Disable the Channel 1: Reset the CC1E Bit */
group-onsemi 0:098463de4c5d 5173 TIMx->CCER &= ~TIM_CCER_CC1E;
group-onsemi 0:098463de4c5d 5174 tmpccmr1 = TIMx->CCMR1;
group-onsemi 0:098463de4c5d 5175 tmpccer = TIMx->CCER;
group-onsemi 0:098463de4c5d 5176
group-onsemi 0:098463de4c5d 5177 /* Select the Input */
group-onsemi 0:098463de4c5d 5178 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
group-onsemi 0:098463de4c5d 5179 {
group-onsemi 0:098463de4c5d 5180 tmpccmr1 &= ~TIM_CCMR1_CC1S;
group-onsemi 0:098463de4c5d 5181 tmpccmr1 |= TIM_ICSelection;
group-onsemi 0:098463de4c5d 5182 }
group-onsemi 0:098463de4c5d 5183 else
group-onsemi 0:098463de4c5d 5184 {
group-onsemi 0:098463de4c5d 5185 tmpccmr1 |= TIM_CCMR1_CC1S_0;
group-onsemi 0:098463de4c5d 5186 }
group-onsemi 0:098463de4c5d 5187
group-onsemi 0:098463de4c5d 5188 /* Set the filter */
group-onsemi 0:098463de4c5d 5189 tmpccmr1 &= ~TIM_CCMR1_IC1F;
group-onsemi 0:098463de4c5d 5190 tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
group-onsemi 0:098463de4c5d 5191
group-onsemi 0:098463de4c5d 5192 /* Select the Polarity and set the CC1E Bit */
group-onsemi 0:098463de4c5d 5193 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
group-onsemi 0:098463de4c5d 5194 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
group-onsemi 0:098463de4c5d 5195
group-onsemi 0:098463de4c5d 5196 /* Write to TIMx CCMR1 and CCER registers */
group-onsemi 0:098463de4c5d 5197 TIMx->CCMR1 = tmpccmr1;
group-onsemi 0:098463de4c5d 5198 TIMx->CCER = tmpccer;
group-onsemi 0:098463de4c5d 5199 }
group-onsemi 0:098463de4c5d 5200
group-onsemi 0:098463de4c5d 5201 /**
group-onsemi 0:098463de4c5d 5202 * @brief Configure the Polarity and Filter for TI1.
group-onsemi 0:098463de4c5d 5203 * @param TIMx to select the TIM peripheral.
group-onsemi 0:098463de4c5d 5204 * @param TIM_ICPolarity : The Input Polarity.
group-onsemi 0:098463de4c5d 5205 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 5206 * @arg TIM_ICPolarity_Rising
group-onsemi 0:098463de4c5d 5207 * @arg TIM_ICPolarity_Falling
group-onsemi 0:098463de4c5d 5208 * @arg TIM_ICPolarity_BothEdge
group-onsemi 0:098463de4c5d 5209 * @param TIM_ICFilter: Specifies the Input Capture Filter.
group-onsemi 0:098463de4c5d 5210 * This parameter must be a value between 0x00 and 0x0F.
group-onsemi 0:098463de4c5d 5211 * @retval None
group-onsemi 0:098463de4c5d 5212 */
group-onsemi 0:098463de4c5d 5213 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
group-onsemi 0:098463de4c5d 5214 {
group-onsemi 0:098463de4c5d 5215 uint32_t tmpccmr1 = 0;
group-onsemi 0:098463de4c5d 5216 uint32_t tmpccer = 0;
group-onsemi 0:098463de4c5d 5217
group-onsemi 0:098463de4c5d 5218 /* Disable the Channel 1: Reset the CC1E Bit */
group-onsemi 0:098463de4c5d 5219 tmpccer = TIMx->CCER;
group-onsemi 0:098463de4c5d 5220 TIMx->CCER &= ~TIM_CCER_CC1E;
group-onsemi 0:098463de4c5d 5221 tmpccmr1 = TIMx->CCMR1;
group-onsemi 0:098463de4c5d 5222
group-onsemi 0:098463de4c5d 5223 /* Set the filter */
group-onsemi 0:098463de4c5d 5224 tmpccmr1 &= ~TIM_CCMR1_IC1F;
group-onsemi 0:098463de4c5d 5225 tmpccmr1 |= (TIM_ICFilter << 4);
group-onsemi 0:098463de4c5d 5226
group-onsemi 0:098463de4c5d 5227 /* Select the Polarity and set the CC1E Bit */
group-onsemi 0:098463de4c5d 5228 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
group-onsemi 0:098463de4c5d 5229 tmpccer |= TIM_ICPolarity;
group-onsemi 0:098463de4c5d 5230
group-onsemi 0:098463de4c5d 5231 /* Write to TIMx CCMR1 and CCER registers */
group-onsemi 0:098463de4c5d 5232 TIMx->CCMR1 = tmpccmr1;
group-onsemi 0:098463de4c5d 5233 TIMx->CCER = tmpccer;
group-onsemi 0:098463de4c5d 5234 }
group-onsemi 0:098463de4c5d 5235
group-onsemi 0:098463de4c5d 5236 /**
group-onsemi 0:098463de4c5d 5237 * @brief Configure the TI2 as Input.
group-onsemi 0:098463de4c5d 5238 * @param TIMx to select the TIM peripheral
group-onsemi 0:098463de4c5d 5239 * @param TIM_ICPolarity : The Input Polarity.
group-onsemi 0:098463de4c5d 5240 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 5241 * @arg TIM_ICPolarity_Rising
group-onsemi 0:098463de4c5d 5242 * @arg TIM_ICPolarity_Falling
group-onsemi 0:098463de4c5d 5243 * @arg TIM_ICPolarity_BothEdge
group-onsemi 0:098463de4c5d 5244 * @param TIM_ICSelection: specifies the input to be used.
group-onsemi 0:098463de4c5d 5245 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 5246 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
group-onsemi 0:098463de4c5d 5247 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
group-onsemi 0:098463de4c5d 5248 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
group-onsemi 0:098463de4c5d 5249 * @param TIM_ICFilter: Specifies the Input Capture Filter.
group-onsemi 0:098463de4c5d 5250 * This parameter must be a value between 0x00 and 0x0F.
group-onsemi 0:098463de4c5d 5251 * @retval None
group-onsemi 0:098463de4c5d 5252 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
group-onsemi 0:098463de4c5d 5253 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
group-onsemi 0:098463de4c5d 5254 * protected against un-initialized filter and polarity values.
group-onsemi 0:098463de4c5d 5255 */
group-onsemi 0:098463de4c5d 5256 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
group-onsemi 0:098463de4c5d 5257 uint32_t TIM_ICFilter)
group-onsemi 0:098463de4c5d 5258 {
group-onsemi 0:098463de4c5d 5259 uint32_t tmpccmr1 = 0;
group-onsemi 0:098463de4c5d 5260 uint32_t tmpccer = 0;
group-onsemi 0:098463de4c5d 5261
group-onsemi 0:098463de4c5d 5262 /* Disable the Channel 2: Reset the CC2E Bit */
group-onsemi 0:098463de4c5d 5263 TIMx->CCER &= ~TIM_CCER_CC2E;
group-onsemi 0:098463de4c5d 5264 tmpccmr1 = TIMx->CCMR1;
group-onsemi 0:098463de4c5d 5265 tmpccer = TIMx->CCER;
group-onsemi 0:098463de4c5d 5266
group-onsemi 0:098463de4c5d 5267 /* Select the Input */
group-onsemi 0:098463de4c5d 5268 tmpccmr1 &= ~TIM_CCMR1_CC2S;
group-onsemi 0:098463de4c5d 5269 tmpccmr1 |= (TIM_ICSelection << 8);
group-onsemi 0:098463de4c5d 5270
group-onsemi 0:098463de4c5d 5271 /* Set the filter */
group-onsemi 0:098463de4c5d 5272 tmpccmr1 &= ~TIM_CCMR1_IC2F;
group-onsemi 0:098463de4c5d 5273 tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
group-onsemi 0:098463de4c5d 5274
group-onsemi 0:098463de4c5d 5275 /* Select the Polarity and set the CC2E Bit */
group-onsemi 0:098463de4c5d 5276 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
group-onsemi 0:098463de4c5d 5277 tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
group-onsemi 0:098463de4c5d 5278
group-onsemi 0:098463de4c5d 5279 /* Write to TIMx CCMR1 and CCER registers */
group-onsemi 0:098463de4c5d 5280 TIMx->CCMR1 = tmpccmr1 ;
group-onsemi 0:098463de4c5d 5281 TIMx->CCER = tmpccer;
group-onsemi 0:098463de4c5d 5282 }
group-onsemi 0:098463de4c5d 5283
group-onsemi 0:098463de4c5d 5284 /**
group-onsemi 0:098463de4c5d 5285 * @brief Configure the Polarity and Filter for TI2.
group-onsemi 0:098463de4c5d 5286 * @param TIMx to select the TIM peripheral.
group-onsemi 0:098463de4c5d 5287 * @param TIM_ICPolarity : The Input Polarity.
group-onsemi 0:098463de4c5d 5288 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 5289 * @arg TIM_ICPolarity_Rising
group-onsemi 0:098463de4c5d 5290 * @arg TIM_ICPolarity_Falling
group-onsemi 0:098463de4c5d 5291 * @arg TIM_ICPolarity_BothEdge
group-onsemi 0:098463de4c5d 5292 * @param TIM_ICFilter: Specifies the Input Capture Filter.
group-onsemi 0:098463de4c5d 5293 * This parameter must be a value between 0x00 and 0x0F.
group-onsemi 0:098463de4c5d 5294 * @retval None
group-onsemi 0:098463de4c5d 5295 */
group-onsemi 0:098463de4c5d 5296 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
group-onsemi 0:098463de4c5d 5297 {
group-onsemi 0:098463de4c5d 5298 uint32_t tmpccmr1 = 0;
group-onsemi 0:098463de4c5d 5299 uint32_t tmpccer = 0;
group-onsemi 0:098463de4c5d 5300
group-onsemi 0:098463de4c5d 5301 /* Disable the Channel 2: Reset the CC2E Bit */
group-onsemi 0:098463de4c5d 5302 TIMx->CCER &= ~TIM_CCER_CC2E;
group-onsemi 0:098463de4c5d 5303 tmpccmr1 = TIMx->CCMR1;
group-onsemi 0:098463de4c5d 5304 tmpccer = TIMx->CCER;
group-onsemi 0:098463de4c5d 5305
group-onsemi 0:098463de4c5d 5306 /* Set the filter */
group-onsemi 0:098463de4c5d 5307 tmpccmr1 &= ~TIM_CCMR1_IC2F;
group-onsemi 0:098463de4c5d 5308 tmpccmr1 |= (TIM_ICFilter << 12);
group-onsemi 0:098463de4c5d 5309
group-onsemi 0:098463de4c5d 5310 /* Select the Polarity and set the CC2E Bit */
group-onsemi 0:098463de4c5d 5311 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
group-onsemi 0:098463de4c5d 5312 tmpccer |= (TIM_ICPolarity << 4);
group-onsemi 0:098463de4c5d 5313
group-onsemi 0:098463de4c5d 5314 /* Write to TIMx CCMR1 and CCER registers */
group-onsemi 0:098463de4c5d 5315 TIMx->CCMR1 = tmpccmr1 ;
group-onsemi 0:098463de4c5d 5316 TIMx->CCER = tmpccer;
group-onsemi 0:098463de4c5d 5317 }
group-onsemi 0:098463de4c5d 5318
group-onsemi 0:098463de4c5d 5319 /**
group-onsemi 0:098463de4c5d 5320 * @brief Configure the TI3 as Input.
group-onsemi 0:098463de4c5d 5321 * @param TIMx to select the TIM peripheral
group-onsemi 0:098463de4c5d 5322 * @param TIM_ICPolarity : The Input Polarity.
group-onsemi 0:098463de4c5d 5323 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 5324 * @arg TIM_ICPolarity_Rising
group-onsemi 0:098463de4c5d 5325 * @arg TIM_ICPolarity_Falling
group-onsemi 0:098463de4c5d 5326 * @arg TIM_ICPolarity_BothEdge
group-onsemi 0:098463de4c5d 5327 * @param TIM_ICSelection: specifies the input to be used.
group-onsemi 0:098463de4c5d 5328 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 5329 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
group-onsemi 0:098463de4c5d 5330 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
group-onsemi 0:098463de4c5d 5331 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
group-onsemi 0:098463de4c5d 5332 * @param TIM_ICFilter: Specifies the Input Capture Filter.
group-onsemi 0:098463de4c5d 5333 * This parameter must be a value between 0x00 and 0x0F.
group-onsemi 0:098463de4c5d 5334 * @retval None
group-onsemi 0:098463de4c5d 5335 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
group-onsemi 0:098463de4c5d 5336 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
group-onsemi 0:098463de4c5d 5337 * protected against un-initialized filter and polarity values.
group-onsemi 0:098463de4c5d 5338 */
group-onsemi 0:098463de4c5d 5339 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
group-onsemi 0:098463de4c5d 5340 uint32_t TIM_ICFilter)
group-onsemi 0:098463de4c5d 5341 {
group-onsemi 0:098463de4c5d 5342 uint32_t tmpccmr2 = 0;
group-onsemi 0:098463de4c5d 5343 uint32_t tmpccer = 0;
group-onsemi 0:098463de4c5d 5344
group-onsemi 0:098463de4c5d 5345 /* Disable the Channel 3: Reset the CC3E Bit */
group-onsemi 0:098463de4c5d 5346 TIMx->CCER &= ~TIM_CCER_CC3E;
group-onsemi 0:098463de4c5d 5347 tmpccmr2 = TIMx->CCMR2;
group-onsemi 0:098463de4c5d 5348 tmpccer = TIMx->CCER;
group-onsemi 0:098463de4c5d 5349
group-onsemi 0:098463de4c5d 5350 /* Select the Input */
group-onsemi 0:098463de4c5d 5351 tmpccmr2 &= ~TIM_CCMR2_CC3S;
group-onsemi 0:098463de4c5d 5352 tmpccmr2 |= TIM_ICSelection;
group-onsemi 0:098463de4c5d 5353
group-onsemi 0:098463de4c5d 5354 /* Set the filter */
group-onsemi 0:098463de4c5d 5355 tmpccmr2 &= ~TIM_CCMR2_IC3F;
group-onsemi 0:098463de4c5d 5356 tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
group-onsemi 0:098463de4c5d 5357
group-onsemi 0:098463de4c5d 5358 /* Select the Polarity and set the CC3E Bit */
group-onsemi 0:098463de4c5d 5359 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
group-onsemi 0:098463de4c5d 5360 tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
group-onsemi 0:098463de4c5d 5361
group-onsemi 0:098463de4c5d 5362 /* Write to TIMx CCMR2 and CCER registers */
group-onsemi 0:098463de4c5d 5363 TIMx->CCMR2 = tmpccmr2;
group-onsemi 0:098463de4c5d 5364 TIMx->CCER = tmpccer;
group-onsemi 0:098463de4c5d 5365 }
group-onsemi 0:098463de4c5d 5366
group-onsemi 0:098463de4c5d 5367 /**
group-onsemi 0:098463de4c5d 5368 * @brief Configure the TI4 as Input.
group-onsemi 0:098463de4c5d 5369 * @param TIMx to select the TIM peripheral
group-onsemi 0:098463de4c5d 5370 * @param TIM_ICPolarity : The Input Polarity.
group-onsemi 0:098463de4c5d 5371 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 5372 * @arg TIM_ICPolarity_Rising
group-onsemi 0:098463de4c5d 5373 * @arg TIM_ICPolarity_Falling
group-onsemi 0:098463de4c5d 5374 * @arg TIM_ICPolarity_BothEdge
group-onsemi 0:098463de4c5d 5375 * @param TIM_ICSelection: specifies the input to be used.
group-onsemi 0:098463de4c5d 5376 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 5377 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
group-onsemi 0:098463de4c5d 5378 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
group-onsemi 0:098463de4c5d 5379 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
group-onsemi 0:098463de4c5d 5380 * @param TIM_ICFilter: Specifies the Input Capture Filter.
group-onsemi 0:098463de4c5d 5381 * This parameter must be a value between 0x00 and 0x0F.
group-onsemi 0:098463de4c5d 5382 * @retval None
group-onsemi 0:098463de4c5d 5383 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
group-onsemi 0:098463de4c5d 5384 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
group-onsemi 0:098463de4c5d 5385 * protected against un-initialized filter and polarity values.
group-onsemi 0:098463de4c5d 5386 */
group-onsemi 0:098463de4c5d 5387 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
group-onsemi 0:098463de4c5d 5388 uint32_t TIM_ICFilter)
group-onsemi 0:098463de4c5d 5389 {
group-onsemi 0:098463de4c5d 5390 uint32_t tmpccmr2 = 0;
group-onsemi 0:098463de4c5d 5391 uint32_t tmpccer = 0;
group-onsemi 0:098463de4c5d 5392
group-onsemi 0:098463de4c5d 5393 /* Disable the Channel 4: Reset the CC4E Bit */
group-onsemi 0:098463de4c5d 5394 TIMx->CCER &= ~TIM_CCER_CC4E;
group-onsemi 0:098463de4c5d 5395 tmpccmr2 = TIMx->CCMR2;
group-onsemi 0:098463de4c5d 5396 tmpccer = TIMx->CCER;
group-onsemi 0:098463de4c5d 5397
group-onsemi 0:098463de4c5d 5398 /* Select the Input */
group-onsemi 0:098463de4c5d 5399 tmpccmr2 &= ~TIM_CCMR2_CC4S;
group-onsemi 0:098463de4c5d 5400 tmpccmr2 |= (TIM_ICSelection << 8);
group-onsemi 0:098463de4c5d 5401
group-onsemi 0:098463de4c5d 5402 /* Set the filter */
group-onsemi 0:098463de4c5d 5403 tmpccmr2 &= ~TIM_CCMR2_IC4F;
group-onsemi 0:098463de4c5d 5404 tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
group-onsemi 0:098463de4c5d 5405
group-onsemi 0:098463de4c5d 5406 /* Select the Polarity and set the CC4E Bit */
group-onsemi 0:098463de4c5d 5407 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
group-onsemi 0:098463de4c5d 5408 tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
group-onsemi 0:098463de4c5d 5409
group-onsemi 0:098463de4c5d 5410 /* Write to TIMx CCMR2 and CCER registers */
group-onsemi 0:098463de4c5d 5411 TIMx->CCMR2 = tmpccmr2;
group-onsemi 0:098463de4c5d 5412 TIMx->CCER = tmpccer ;
group-onsemi 0:098463de4c5d 5413 }
group-onsemi 0:098463de4c5d 5414
group-onsemi 0:098463de4c5d 5415 /**
group-onsemi 0:098463de4c5d 5416 * @brief Selects the Input Trigger source
group-onsemi 0:098463de4c5d 5417 * @param TIMx to select the TIM peripheral
group-onsemi 0:098463de4c5d 5418 * @param TIM_ITRx: The Input Trigger source.
group-onsemi 0:098463de4c5d 5419 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 5420 * @arg TIM_TS_ITR0: Internal Trigger 0
group-onsemi 0:098463de4c5d 5421 * @arg TIM_TS_ITR1: Internal Trigger 1
group-onsemi 0:098463de4c5d 5422 * @arg TIM_TS_ITR2: Internal Trigger 2
group-onsemi 0:098463de4c5d 5423 * @arg TIM_TS_ITR3: Internal Trigger 3
group-onsemi 0:098463de4c5d 5424 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
group-onsemi 0:098463de4c5d 5425 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
group-onsemi 0:098463de4c5d 5426 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
group-onsemi 0:098463de4c5d 5427 * @arg TIM_TS_ETRF: External Trigger input
group-onsemi 0:098463de4c5d 5428 * @retval None
group-onsemi 0:098463de4c5d 5429 */
group-onsemi 0:098463de4c5d 5430 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
group-onsemi 0:098463de4c5d 5431 {
group-onsemi 0:098463de4c5d 5432 uint32_t tmpsmcr = 0;
group-onsemi 0:098463de4c5d 5433
group-onsemi 0:098463de4c5d 5434 /* Get the TIMx SMCR register value */
group-onsemi 0:098463de4c5d 5435 tmpsmcr = TIMx->SMCR;
group-onsemi 0:098463de4c5d 5436 /* Reset the TS Bits */
group-onsemi 0:098463de4c5d 5437 tmpsmcr &= ~TIM_SMCR_TS;
group-onsemi 0:098463de4c5d 5438 /* Set the Input Trigger source and the slave mode*/
group-onsemi 0:098463de4c5d 5439 tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
group-onsemi 0:098463de4c5d 5440 /* Write to TIMx SMCR */
group-onsemi 0:098463de4c5d 5441 TIMx->SMCR = tmpsmcr;
group-onsemi 0:098463de4c5d 5442 }
group-onsemi 0:098463de4c5d 5443
group-onsemi 0:098463de4c5d 5444 /**
group-onsemi 0:098463de4c5d 5445 * @brief Configures the TIMx External Trigger (ETR).
group-onsemi 0:098463de4c5d 5446 * @param TIMx to select the TIM peripheral
group-onsemi 0:098463de4c5d 5447 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
group-onsemi 0:098463de4c5d 5448 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 5449 * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
group-onsemi 0:098463de4c5d 5450 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
group-onsemi 0:098463de4c5d 5451 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
group-onsemi 0:098463de4c5d 5452 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
group-onsemi 0:098463de4c5d 5453 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
group-onsemi 0:098463de4c5d 5454 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 5455 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
group-onsemi 0:098463de4c5d 5456 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
group-onsemi 0:098463de4c5d 5457 * @param ExtTRGFilter: External Trigger Filter.
group-onsemi 0:098463de4c5d 5458 * This parameter must be a value between 0x00 and 0x0F
group-onsemi 0:098463de4c5d 5459 * @retval None
group-onsemi 0:098463de4c5d 5460 */
group-onsemi 0:098463de4c5d 5461 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
group-onsemi 0:098463de4c5d 5462 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
group-onsemi 0:098463de4c5d 5463 {
group-onsemi 0:098463de4c5d 5464 uint32_t tmpsmcr = 0;
group-onsemi 0:098463de4c5d 5465
group-onsemi 0:098463de4c5d 5466 tmpsmcr = TIMx->SMCR;
group-onsemi 0:098463de4c5d 5467
group-onsemi 0:098463de4c5d 5468 /* Reset the ETR Bits */
group-onsemi 0:098463de4c5d 5469 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
group-onsemi 0:098463de4c5d 5470
group-onsemi 0:098463de4c5d 5471 /* Set the Prescaler, the Filter value and the Polarity */
group-onsemi 0:098463de4c5d 5472 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
group-onsemi 0:098463de4c5d 5473
group-onsemi 0:098463de4c5d 5474 /* Write to TIMx SMCR */
group-onsemi 0:098463de4c5d 5475 TIMx->SMCR = tmpsmcr;
group-onsemi 0:098463de4c5d 5476 }
group-onsemi 0:098463de4c5d 5477
group-onsemi 0:098463de4c5d 5478 /**
group-onsemi 0:098463de4c5d 5479 * @brief Enables or disables the TIM Capture Compare Channel x.
group-onsemi 0:098463de4c5d 5480 * @param TIMx to select the TIM peripheral
group-onsemi 0:098463de4c5d 5481 * @param Channel: specifies the TIM Channel
group-onsemi 0:098463de4c5d 5482 * This parameter can be one of the following values:
group-onsemi 0:098463de4c5d 5483 * @arg TIM_Channel_1: TIM Channel 1
group-onsemi 0:098463de4c5d 5484 * @arg TIM_Channel_2: TIM Channel 2
group-onsemi 0:098463de4c5d 5485 * @arg TIM_Channel_3: TIM Channel 3
group-onsemi 0:098463de4c5d 5486 * @arg TIM_Channel_4: TIM Channel 4
group-onsemi 0:098463de4c5d 5487 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
group-onsemi 0:098463de4c5d 5488 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
group-onsemi 0:098463de4c5d 5489 * @retval None
group-onsemi 0:098463de4c5d 5490 */
group-onsemi 0:098463de4c5d 5491 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
group-onsemi 0:098463de4c5d 5492 {
group-onsemi 0:098463de4c5d 5493 uint32_t tmp = 0;
group-onsemi 0:098463de4c5d 5494
group-onsemi 0:098463de4c5d 5495 /* Check the parameters */
group-onsemi 0:098463de4c5d 5496 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
group-onsemi 0:098463de4c5d 5497 assert_param(IS_TIM_CHANNELS(Channel));
group-onsemi 0:098463de4c5d 5498
group-onsemi 0:098463de4c5d 5499 tmp = TIM_CCER_CC1E << Channel;
group-onsemi 0:098463de4c5d 5500
group-onsemi 0:098463de4c5d 5501 /* Reset the CCxE Bit */
group-onsemi 0:098463de4c5d 5502 TIMx->CCER &= ~tmp;
group-onsemi 0:098463de4c5d 5503
group-onsemi 0:098463de4c5d 5504 /* Set or reset the CCxE Bit */
group-onsemi 0:098463de4c5d 5505 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
group-onsemi 0:098463de4c5d 5506 }
group-onsemi 0:098463de4c5d 5507
group-onsemi 0:098463de4c5d 5508
group-onsemi 0:098463de4c5d 5509 /**
group-onsemi 0:098463de4c5d 5510 * @}
group-onsemi 0:098463de4c5d 5511 */
group-onsemi 0:098463de4c5d 5512
group-onsemi 0:098463de4c5d 5513 #endif /* HAL_TIM_MODULE_ENABLED */
group-onsemi 0:098463de4c5d 5514 /**
group-onsemi 0:098463de4c5d 5515 * @}
group-onsemi 0:098463de4c5d 5516 */
group-onsemi 0:098463de4c5d 5517
group-onsemi 0:098463de4c5d 5518 /**
group-onsemi 0:098463de4c5d 5519 * @}
group-onsemi 0:098463de4c5d 5520 */
group-onsemi 0:098463de4c5d 5521 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/