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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /**
group-onsemi 0:098463de4c5d 2 ******************************************************************************
group-onsemi 0:098463de4c5d 3 * @file rtc_map.h
group-onsemi 0:098463de4c5d 4 * @brief Real Time Clock HW register map
group-onsemi 0:098463de4c5d 5 * @internal
group-onsemi 0:098463de4c5d 6 * @author ON Semiconductor.
group-onsemi 0:098463de4c5d 7 * $Rev: 3008 $
group-onsemi 0:098463de4c5d 8 * $Date: 2014-10-16 18:42:48 +0530 (Thu, 16 Oct 2014) $
group-onsemi 0:098463de4c5d 9 ******************************************************************************
group-onsemi 0:098463de4c5d 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
group-onsemi 0:098463de4c5d 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
group-onsemi 0:098463de4c5d 12 * under limited terms and conditions. The terms and conditions pertaining to the software
group-onsemi 0:098463de4c5d 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
group-onsemi 0:098463de4c5d 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
group-onsemi 0:098463de4c5d 15 * if applicable the software license agreement. Do not use this software and/or
group-onsemi 0:098463de4c5d 16 * documentation unless you have carefully read and you agree to the limited terms and
group-onsemi 0:098463de4c5d 17 * conditions. By using this software and/or documentation, you agree to the limited
group-onsemi 0:098463de4c5d 18 * terms and conditions.
group-onsemi 0:098463de4c5d 19 *
group-onsemi 0:098463de4c5d 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
group-onsemi 0:098463de4c5d 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
group-onsemi 0:098463de4c5d 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
group-onsemi 0:098463de4c5d 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
group-onsemi 0:098463de4c5d 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
group-onsemi 0:098463de4c5d 25 * @endinternal
group-onsemi 0:098463de4c5d 26 *
group-onsemi 0:098463de4c5d 27 * @ingroup rtc
group-onsemi 0:098463de4c5d 28 *
group-onsemi 0:098463de4c5d 29 * @details
group-onsemi 0:098463de4c5d 30 * <p>
group-onsemi 0:098463de4c5d 31 * Teal Time Clock HW register map description
group-onsemi 0:098463de4c5d 32 * </p>
group-onsemi 0:098463de4c5d 33 *
group-onsemi 0:098463de4c5d 34 * <h1> Reference document(s) </h1>
group-onsemi 0:098463de4c5d 35 * <p>
group-onsemi 0:098463de4c5d 36 * <a HOURef="../pdf/IPC7206_RTC_APB_DS_v1P0.pdf" target="_blank">
group-onsemi 0:098463de4c5d 37 * IPC7206 APB RTC Design Specification v1.0 </a>
group-onsemi 0:098463de4c5d 38 * </p>
group-onsemi 0:098463de4c5d 39 */
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 #ifndef RTC_MAP_H_
group-onsemi 0:098463de4c5d 42 #define RTC_MAP_H_
group-onsemi 0:098463de4c5d 43
group-onsemi 0:098463de4c5d 44 #include "architecture.h"
group-onsemi 0:098463de4c5d 45
group-onsemi 0:098463de4c5d 46 /** Real Time Clock Control HW Structure Overlay */
group-onsemi 0:098463de4c5d 47 typedef struct {
group-onsemi 0:098463de4c5d 48 __IO uint32_t SUB_SECOND_COUNTER; /**<SUB SECOND Counter */ /* 0x4000F000 */
group-onsemi 0:098463de4c5d 49 __IO uint32_t SECOND_COUNTER; /**<SECOND Counter */ /* 0x4000F004 */
group-onsemi 0:098463de4c5d 50 __IO uint32_t SUB_SECOND_ALARM; /**< SUB SECOND alarm */ /* 0x4000F008 */
group-onsemi 0:098463de4c5d 51 __IO uint32_t SECOND_ALARM; /**< SECOND alarm */ /* 0x4000F00c */
group-onsemi 0:098463de4c5d 52 union {
group-onsemi 0:098463de4c5d 53 struct {
group-onsemi 0:098463de4c5d 54 __IO uint32_t SUB_SEC_COUNTER_EN :1; /**<Sub-second counter enable. (1=count is enabled, 0=retain count value) */
group-onsemi 0:098463de4c5d 55 __IO uint32_t SEC_COUNTER_EN :1; /**<Second counter enable. (1=count is enabled, 0=retain count value) */
group-onsemi 0:098463de4c5d 56 __IO uint32_t SUB_SECOND_INT_EN :1; /**<Sub-second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
group-onsemi 0:098463de4c5d 57 __IO uint32_t SECOND_INT_EN :1; /**<Second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
group-onsemi 0:098463de4c5d 58 } BITS;
group-onsemi 0:098463de4c5d 59 __IO uint32_t WORD;
group-onsemi 0:098463de4c5d 60 } CONTROL; /* 0x4000F010 */
group-onsemi 0:098463de4c5d 61 union {
group-onsemi 0:098463de4c5d 62 struct {
group-onsemi 0:098463de4c5d 63 /**<Any write to the status register will clear the error bit. */
group-onsemi 0:098463de4c5d 64 __IO uint32_t SUB_SECOND_INT:1; /**<Sub-second interrupt status. (1=interrupt active, 0=no interrupt)*/
group-onsemi 0:098463de4c5d 65 __IO uint32_t SECOND_INT :1; /**<Second interrupt status. (1=interrupt active, 0=no interrupt)*/
group-onsemi 0:098463de4c5d 66 __IO uint32_t WRITE_ERROR :1; /**<Reads error bit which is set when a write occurs before a previous write to the same register has completed. */
group-onsemi 0:098463de4c5d 67 __IO uint32_t BSY_ANY_WRT :1; /**<Busy with any write.*/
group-onsemi 0:098463de4c5d 68 __IO uint32_t BSY_SUB_SEC_CNTR_REG_WRT :1; /**<Busy with a sub-second counter register write.*/
group-onsemi 0:098463de4c5d 69 __IO uint32_t BSY_SEC_CNTR_REG_WRT :1; /**<Busy with a second counter register write.*/
group-onsemi 0:098463de4c5d 70 __IO uint32_t BSY_SUB_SEC_ALRM_REG_WRT :1; /**<Busy with a sub-second alarm register write.*/
group-onsemi 0:098463de4c5d 71 __IO uint32_t BSY_SEC_ALRM_REG_WRT:1; /**<Busy with a second alarm register write.*/
group-onsemi 0:098463de4c5d 72 __IO uint32_t BSY_CTRL_REG_WRT :1; /**<Busy with a control register write.*/
group-onsemi 0:098463de4c5d 73 __IO uint32_t BSY_SUB_SEC_INT_CLR_WRT :1; /**<Busy with a sub-second interrupt clear write.*/
group-onsemi 0:098463de4c5d 74 __IO uint32_t BSY_SEC_INT_CLR_WRT :1; /**<Busy with a second interrupt clear write.*/
group-onsemi 0:098463de4c5d 75 } BITS;
group-onsemi 0:098463de4c5d 76 __IO uint32_t WORD;
group-onsemi 0:098463de4c5d 77 } STATUS; /* 0x4000F014 */
group-onsemi 0:098463de4c5d 78 union {
group-onsemi 0:098463de4c5d 79 struct {
group-onsemi 0:098463de4c5d 80 __O uint32_t SUB_SECOND :1; /**<Write 1 to this register to clear the sub-second interrupt.*/
group-onsemi 0:098463de4c5d 81 __O uint32_t SECOND :1; /**<Write 1 to this register to clear the second interrupt.*/
group-onsemi 0:098463de4c5d 82 } BITS;
group-onsemi 0:098463de4c5d 83 __O uint32_t WORD;
group-onsemi 0:098463de4c5d 84 } INT_CLEAR; /* 0x4000F018 */
group-onsemi 0:098463de4c5d 85 } RtcReg_t, *RtcReg_pt;
group-onsemi 0:098463de4c5d 86
group-onsemi 0:098463de4c5d 87 #endif /* RTC_MAP_H_ */