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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /**
group-onsemi 0:098463de4c5d 2 ******************************************************************************
group-onsemi 0:098463de4c5d 3 * @file rfAna.c
group-onsemi 0:098463de4c5d 4 * @brief Implementation of rfAna hw module functions
group-onsemi 0:098463de4c5d 5 * @internal
group-onsemi 0:098463de4c5d 6 * @author ON Semiconductor
group-onsemi 0:098463de4c5d 7 * $Rev: 3445 $
group-onsemi 0:098463de4c5d 8 * $Date: 2015-06-22 13:51:24 +0530 (Mon, 22 Jun 2015) $
group-onsemi 0:098463de4c5d 9 ******************************************************************************
group-onsemi 0:098463de4c5d 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
group-onsemi 0:098463de4c5d 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
group-onsemi 0:098463de4c5d 12 * under limited terms and conditions. The terms and conditions pertaining to the software
group-onsemi 0:098463de4c5d 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
group-onsemi 0:098463de4c5d 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
group-onsemi 0:098463de4c5d 15 * if applicable the software license agreement. Do not use this software and/or
group-onsemi 0:098463de4c5d 16 * documentation unless you have carefully read and you agree to the limited terms and
group-onsemi 0:098463de4c5d 17 * conditions. By using this software and/or documentation, you agree to the limited
group-onsemi 0:098463de4c5d 18 * terms and conditions.
group-onsemi 0:098463de4c5d 19 *
group-onsemi 0:098463de4c5d 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
group-onsemi 0:098463de4c5d 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
group-onsemi 0:098463de4c5d 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
group-onsemi 0:098463de4c5d 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
group-onsemi 0:098463de4c5d 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
group-onsemi 0:098463de4c5d 25 * @endinternal
group-onsemi 0:098463de4c5d 26 *
group-onsemi 0:098463de4c5d 27 * @ingroup rfAna
group-onsemi 0:098463de4c5d 28 *
group-onsemi 0:098463de4c5d 29 * @details
group-onsemi 0:098463de4c5d 30 *
group-onsemi 0:098463de4c5d 31 * <h1> Reference document(s) </h1>
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 /*************************************************************************************************
group-onsemi 0:098463de4c5d 35 * *
group-onsemi 0:098463de4c5d 36 * Header files *
group-onsemi 0:098463de4c5d 37 * *
group-onsemi 0:098463de4c5d 38 *************************************************************************************************/
group-onsemi 0:098463de4c5d 39
group-onsemi 0:098463de4c5d 40 #include "memory_map.h"
group-onsemi 0:098463de4c5d 41 #include "rfAna.h"
group-onsemi 0:098463de4c5d 42 #include "clock.h"
group-onsemi 0:098463de4c5d 43
group-onsemi 0:098463de4c5d 44 /*************************************************************************************************
group-onsemi 0:098463de4c5d 45 * *
group-onsemi 0:098463de4c5d 46 * Global variables *
group-onsemi 0:098463de4c5d 47 * *
group-onsemi 0:098463de4c5d 48 *************************************************************************************************/
group-onsemi 0:098463de4c5d 49
group-onsemi 0:098463de4c5d 50 /** Rf channel and tx power lookup tables (constant)
group-onsemi 0:098463de4c5d 51 * @details
group-onsemi 0:098463de4c5d 52 *
group-onsemi 0:098463de4c5d 53 * The rf channel table is used to program internal hardware register for different 15.4 rf channels.
group-onsemi 0:098463de4c5d 54 * It has 16 entries corresponding to 16 15.4 channels.
group-onsemi 0:098463de4c5d 55 * Entry 1 <-> Channel 11
group-onsemi 0:098463de4c5d 56 * ...
group-onsemi 0:098463de4c5d 57 * Entry 16 <-> Channel 26
group-onsemi 0:098463de4c5d 58 *
group-onsemi 0:098463de4c5d 59 * Each entry is compound of 4 items.
group-onsemi 0:098463de4c5d 60 * Item 0: Rx Frequency integer divide portion
group-onsemi 0:098463de4c5d 61 * Item 1: Rx Frequency fractional divide portion
group-onsemi 0:098463de4c5d 62 * Item 2: Tx Frequency integer divide portion
group-onsemi 0:098463de4c5d 63 * Item 3: Tx Frequency fractional divide portion
group-onsemi 0:098463de4c5d 64 *
group-onsemi 0:098463de4c5d 65 * The tx power table is used to program internal hardware register for different 15.4 tx power levels.
group-onsemi 0:098463de4c5d 66 * It has 43 entries corresponding to tx power levels from -32dBm to +10dBm.
group-onsemi 0:098463de4c5d 67 * Entry 1 <-> -32dB
group-onsemi 0:098463de4c5d 68 * Entry 2 <-> -31dB
group-onsemi 0:098463de4c5d 69 * ...
group-onsemi 0:098463de4c5d 70 * Entry 2 <-> 9dB
group-onsemi 0:098463de4c5d 71 * Entry 43 <-> +10dB
group-onsemi 0:098463de4c5d 72 *
group-onsemi 0:098463de4c5d 73 * Each entry is compound of 1 byte.
group-onsemi 0:098463de4c5d 74 */
group-onsemi 0:098463de4c5d 75
group-onsemi 0:098463de4c5d 76 // RR: Making high side injection changes to RevD
group-onsemi 0:098463de4c5d 77
group-onsemi 0:098463de4c5d 78 /** This rf LUT is built for high side injection, using low side injection
group-onsemi 0:098463de4c5d 79 * would requiere to change this LUT. */
group-onsemi 0:098463de4c5d 80 const uint32_t rfLut[16][4] = {{0x50,0x00D4A7,0x4B,0x00A000},
group-onsemi 0:098463de4c5d 81 {0x50,0x017F52,0x4B,0x014001},
group-onsemi 0:098463de4c5d 82 {0x51,0xFE29FB,0x4B,0x01E001},
group-onsemi 0:098463de4c5d 83 {0x51,0xFED4A6,0x4C,0xFE7FFF},
group-onsemi 0:098463de4c5d 84 {0x51,0xFF7F51,0x4C,0xFF1FFF},
group-onsemi 0:098463de4c5d 85 {0x51,0x0029FC,0x4C,0xFFC000},
group-onsemi 0:098463de4c5d 86 {0x51,0x00D4A7,0x4C,0x006000},
group-onsemi 0:098463de4c5d 87 {0x51,0x017F52,0x4C,0x010001},
group-onsemi 0:098463de4c5d 88 {0x52,0xFE29FB,0x4C,0x01A001},
group-onsemi 0:098463de4c5d 89 {0x52,0xFED4A6,0x4D,0xFE3FFF},
group-onsemi 0:098463de4c5d 90 {0x52,0xFF7F51,0x4D,0xFEDFFF},
group-onsemi 0:098463de4c5d 91 {0x52,0x0029FC,0x4D,0xFF8000},
group-onsemi 0:098463de4c5d 92 {0x52,0x00D4A7,0x4D,0x002000},
group-onsemi 0:098463de4c5d 93 {0x52,0x017F52,0x4D,0x00C001},
group-onsemi 0:098463de4c5d 94 {0x53,0xFE29FB,0x4D,0x016001},
group-onsemi 0:098463de4c5d 95 {0x53,0xFED4A6,0x4E,0xFDFFFE}
group-onsemi 0:098463de4c5d 96 };
group-onsemi 0:098463de4c5d 97
group-onsemi 0:098463de4c5d 98 const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
group-onsemi 0:098463de4c5d 99 0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
group-onsemi 0:098463de4c5d 100 0,0,0,0,0,0,0,0,1,2, // -19dBm to -10dBm
group-onsemi 0:098463de4c5d 101 3,4,5,6,7,8,9,10,11,12, // -9dBm to 0dBm
group-onsemi 0:098463de4c5d 102 13,14,15,16,17,18,19,20,20,20
group-onsemi 0:098463de4c5d 103 }; // +1dBm to +10 dBm
group-onsemi 0:098463de4c5d 104
group-onsemi 0:098463de4c5d 105 /*************************************************************************************************
group-onsemi 0:098463de4c5d 106 * *
group-onsemi 0:098463de4c5d 107 * Functions *
group-onsemi 0:098463de4c5d 108 * *
group-onsemi 0:098463de4c5d 109 *************************************************************************************************/
group-onsemi 0:098463de4c5d 110
group-onsemi 0:098463de4c5d 111 void fRfAnaInit()
group-onsemi 0:098463de4c5d 112 {
group-onsemi 0:098463de4c5d 113 // Enable rfana clock
group-onsemi 0:098463de4c5d 114 CLOCK_ENABLE(CLOCK_RFANA);
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 // Set PLL timing
group-onsemi 0:098463de4c5d 117 RFANAREG->PLL_TIMING.BITS.PLL_RESET_TIME = 0x1E; // 30us
group-onsemi 0:098463de4c5d 118 RFANAREG->PLL_TIMING.BITS.PLL_LOCK_TIME = 0x2F; // 47us
group-onsemi 0:098463de4c5d 119
group-onsemi 0:098463de4c5d 120 // Set other parameters
group-onsemi 0:098463de4c5d 121 RFANAREG->RX_CONTROL.BITS.LNA_GAIN_MODE = 0x1; // High Gain mode
group-onsemi 0:098463de4c5d 122 RFANAREG->RX_CONTROL.BITS.ADC_DITHER_MODE = 0x0; // Dither mode disabled
group-onsemi 0:098463de4c5d 123 }
group-onsemi 0:098463de4c5d 124
group-onsemi 0:098463de4c5d 125 boolean fRfAnaIoctl (uint32_t request, void *argument)
group-onsemi 0:098463de4c5d 126 {
group-onsemi 0:098463de4c5d 127 uint8_t channel, txPower;
group-onsemi 0:098463de4c5d 128
group-onsemi 0:098463de4c5d 129 // Enable rfana clock (in case fRfAnaIoctl is used before call of fRfAnaInit)
group-onsemi 0:098463de4c5d 130 CLOCK_ENABLE(CLOCK_RFANA);
group-onsemi 0:098463de4c5d 131
group-onsemi 0:098463de4c5d 132 switch(request) {
group-onsemi 0:098463de4c5d 133 case SET_RF_CHANNEL:
group-onsemi 0:098463de4c5d 134 channel = *(uint8_t*)argument;
group-onsemi 0:098463de4c5d 135
group-onsemi 0:098463de4c5d 136 // Set tx/rx integer/fractional divide portions
group-onsemi 0:098463de4c5d 137 RFANAREG->TX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][3];
group-onsemi 0:098463de4c5d 138 RFANAREG->TX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][2];
group-onsemi 0:098463de4c5d 139 RFANAREG->RX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][1];
group-onsemi 0:098463de4c5d 140 RFANAREG->RX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][0];
group-onsemi 0:098463de4c5d 141
group-onsemi 0:098463de4c5d 142 // Set tx/rx vco trims
group-onsemi 0:098463de4c5d 143 /** REVD is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
group-onsemi 0:098463de4c5d 144 * from trims stored in dedicated registers available in digital.*/
group-onsemi 0:098463de4c5d 145 if (channel < 19) {
group-onsemi 0:098463de4c5d 146 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
group-onsemi 0:098463de4c5d 147 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
group-onsemi 0:098463de4c5d 148 } else {
group-onsemi 0:098463de4c5d 149 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
group-onsemi 0:098463de4c5d 150 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
group-onsemi 0:098463de4c5d 151 }
group-onsemi 0:098463de4c5d 152 break;
group-onsemi 0:098463de4c5d 153 case SET_TX_POWER:
group-onsemi 0:098463de4c5d 154 txPower = *(uint8_t*)argument;
group-onsemi 0:098463de4c5d 155
group-onsemi 0:098463de4c5d 156 // Set tx power register
group-onsemi 0:098463de4c5d 157 if ((txPower & 0x20) == 0) {
group-onsemi 0:098463de4c5d 158 RFANAREG->TX_POWER = (txPowerLut[txPower + 32] & 0xFF);
group-onsemi 0:098463de4c5d 159 } else {
group-onsemi 0:098463de4c5d 160 RFANAREG->TX_POWER = (txPowerLut[txPower - 32] & 0xFF);
group-onsemi 0:098463de4c5d 161 }
group-onsemi 0:098463de4c5d 162
group-onsemi 0:098463de4c5d 163 break;
group-onsemi 0:098463de4c5d 164 default:
group-onsemi 0:098463de4c5d 165 return False;
group-onsemi 0:098463de4c5d 166 }
group-onsemi 0:098463de4c5d 167 return True;
group-onsemi 0:098463de4c5d 168 }