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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NXP/TARGET_LPC408X/gpio_irq_api.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2013 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 #include <stddef.h>
group-onsemi 0:098463de4c5d 17 #include "gpio_irq_api.h"
group-onsemi 0:098463de4c5d 18 #include "mbed_error.h"
group-onsemi 0:098463de4c5d 19 #include "cmsis.h"
group-onsemi 0:098463de4c5d 20
group-onsemi 0:098463de4c5d 21 #define CHANNEL_NUM 64
group-onsemi 0:098463de4c5d 22
group-onsemi 0:098463de4c5d 23 static uint32_t channel_ids[CHANNEL_NUM] = {0};
group-onsemi 0:098463de4c5d 24 static gpio_irq_handler irq_handler;
group-onsemi 0:098463de4c5d 25
group-onsemi 0:098463de4c5d 26 static void handle_interrupt_in(void) {
group-onsemi 0:098463de4c5d 27 // Read in all current interrupt registers. We do this once as the
group-onsemi 0:098463de4c5d 28 // GPIO interrupt registers are on the APB bus, and this is slow.
group-onsemi 0:098463de4c5d 29 uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
group-onsemi 0:098463de4c5d 30 uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
group-onsemi 0:098463de4c5d 31 uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
group-onsemi 0:098463de4c5d 32 uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 uint8_t bitloc;
group-onsemi 0:098463de4c5d 35
group-onsemi 0:098463de4c5d 36 // Continue as long as there are interrupts pending
group-onsemi 0:098463de4c5d 37 while(rise0 > 0) {
group-onsemi 0:098463de4c5d 38 // CLZ returns number of leading zeros, 31 minus that is location of
group-onsemi 0:098463de4c5d 39 // first pending interrupt
group-onsemi 0:098463de4c5d 40 bitloc = 31 - __CLZ(rise0);
group-onsemi 0:098463de4c5d 41 if (channel_ids[bitloc] != 0)
group-onsemi 0:098463de4c5d 42 irq_handler(channel_ids[bitloc], IRQ_RISE); //Run that interrupt
group-onsemi 0:098463de4c5d 43
group-onsemi 0:098463de4c5d 44 // Both clear the interrupt with clear register, and remove it from
group-onsemi 0:098463de4c5d 45 // our local copy of the interrupt pending register
group-onsemi 0:098463de4c5d 46 LPC_GPIOINT->IO0IntClr = 1 << bitloc;
group-onsemi 0:098463de4c5d 47 rise0 -= 1<<bitloc;
group-onsemi 0:098463de4c5d 48 }
group-onsemi 0:098463de4c5d 49
group-onsemi 0:098463de4c5d 50 // Continue as long as there are interrupts pending
group-onsemi 0:098463de4c5d 51 while(fall0 > 0) {
group-onsemi 0:098463de4c5d 52 // CLZ returns number of leading zeros, 31 minus that is location of
group-onsemi 0:098463de4c5d 53 // first pending interrupt
group-onsemi 0:098463de4c5d 54 bitloc = 31 - __CLZ(fall0);
group-onsemi 0:098463de4c5d 55 if (channel_ids[bitloc] != 0)
group-onsemi 0:098463de4c5d 56 irq_handler(channel_ids[bitloc], IRQ_FALL); //Run that interrupt
group-onsemi 0:098463de4c5d 57
group-onsemi 0:098463de4c5d 58 // Both clear the interrupt with clear register, and remove it from
group-onsemi 0:098463de4c5d 59 // our local copy of the interrupt pending register
group-onsemi 0:098463de4c5d 60 LPC_GPIOINT->IO0IntClr = 1 << bitloc;
group-onsemi 0:098463de4c5d 61 fall0 -= 1<<bitloc;
group-onsemi 0:098463de4c5d 62 }
group-onsemi 0:098463de4c5d 63
group-onsemi 0:098463de4c5d 64 // Same for port 2
group-onsemi 0:098463de4c5d 65
group-onsemi 0:098463de4c5d 66 // Continue as long as there are interrupts pending
group-onsemi 0:098463de4c5d 67 while(rise2 > 0) {
group-onsemi 0:098463de4c5d 68 // CLZ returns number of leading zeros, 31 minus that is location of
group-onsemi 0:098463de4c5d 69 // first pending interrupt
group-onsemi 0:098463de4c5d 70 bitloc = 31 - __CLZ(rise2);
group-onsemi 0:098463de4c5d 71 if (channel_ids[bitloc+32] != 0)
group-onsemi 0:098463de4c5d 72 irq_handler(channel_ids[bitloc+32], IRQ_RISE); //Run that interrupt
group-onsemi 0:098463de4c5d 73
group-onsemi 0:098463de4c5d 74 // Both clear the interrupt with clear register, and remove it from
group-onsemi 0:098463de4c5d 75 // our local copy of the interrupt pending register
group-onsemi 0:098463de4c5d 76 LPC_GPIOINT->IO2IntClr = 1 << bitloc;
group-onsemi 0:098463de4c5d 77 rise2 -= 1<<bitloc;
group-onsemi 0:098463de4c5d 78 }
group-onsemi 0:098463de4c5d 79
group-onsemi 0:098463de4c5d 80 // Continue as long as there are interrupts pending
group-onsemi 0:098463de4c5d 81 while(fall2 > 0) {
group-onsemi 0:098463de4c5d 82 // CLZ returns number of leading zeros, 31 minus that is location of
group-onsemi 0:098463de4c5d 83 // first pending interrupt
group-onsemi 0:098463de4c5d 84 bitloc = 31 - __CLZ(fall2);
group-onsemi 0:098463de4c5d 85 if (channel_ids[bitloc+32] != 0)
group-onsemi 0:098463de4c5d 86 irq_handler(channel_ids[bitloc+32], IRQ_FALL); //Run that interrupt
group-onsemi 0:098463de4c5d 87
group-onsemi 0:098463de4c5d 88 // Both clear the interrupt with clear register, and remove it from
group-onsemi 0:098463de4c5d 89 // our local copy of the interrupt pending register
group-onsemi 0:098463de4c5d 90 LPC_GPIOINT->IO2IntClr = 1 << bitloc;
group-onsemi 0:098463de4c5d 91 fall2 -= 1<<bitloc;
group-onsemi 0:098463de4c5d 92 }
group-onsemi 0:098463de4c5d 93 }
group-onsemi 0:098463de4c5d 94
group-onsemi 0:098463de4c5d 95 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
group-onsemi 0:098463de4c5d 96 if (pin == NC) return -1;
group-onsemi 0:098463de4c5d 97
group-onsemi 0:098463de4c5d 98 irq_handler = handler;
group-onsemi 0:098463de4c5d 99
group-onsemi 0:098463de4c5d 100 obj->port = ((int)(LPC_GPIO0_BASE+pin) & ~0x1F);
group-onsemi 0:098463de4c5d 101 obj->pin = (int)pin % 32;
group-onsemi 0:098463de4c5d 102
group-onsemi 0:098463de4c5d 103 // Interrupts available only on GPIO0 and GPIO2
group-onsemi 0:098463de4c5d 104 if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
group-onsemi 0:098463de4c5d 105 error("pins on this port cannot generate interrupts");
group-onsemi 0:098463de4c5d 106 }
group-onsemi 0:098463de4c5d 107
group-onsemi 0:098463de4c5d 108 // put us in the interrupt table
group-onsemi 0:098463de4c5d 109 int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
group-onsemi 0:098463de4c5d 110 channel_ids[index] = id;
group-onsemi 0:098463de4c5d 111 obj->ch = index;
group-onsemi 0:098463de4c5d 112
group-onsemi 0:098463de4c5d 113 NVIC_SetVector(GPIO_IRQn, (uint32_t)handle_interrupt_in);
group-onsemi 0:098463de4c5d 114 NVIC_EnableIRQ(GPIO_IRQn);
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 return 0;
group-onsemi 0:098463de4c5d 117 }
group-onsemi 0:098463de4c5d 118
group-onsemi 0:098463de4c5d 119 void gpio_irq_free(gpio_irq_t *obj) {
group-onsemi 0:098463de4c5d 120 channel_ids[obj->ch] = 0;
group-onsemi 0:098463de4c5d 121 }
group-onsemi 0:098463de4c5d 122
group-onsemi 0:098463de4c5d 123 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
group-onsemi 0:098463de4c5d 124 // ensure nothing is pending
group-onsemi 0:098463de4c5d 125 switch (obj->port) {
group-onsemi 0:098463de4c5d 126 case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
group-onsemi 0:098463de4c5d 127 case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
group-onsemi 0:098463de4c5d 128 }
group-onsemi 0:098463de4c5d 129
group-onsemi 0:098463de4c5d 130 // enable the pin interrupt
group-onsemi 0:098463de4c5d 131 if (event == IRQ_RISE) {
group-onsemi 0:098463de4c5d 132 switch (obj->port) {
group-onsemi 0:098463de4c5d 133 case LPC_GPIO0_BASE:
group-onsemi 0:098463de4c5d 134 if (enable) {
group-onsemi 0:098463de4c5d 135 LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
group-onsemi 0:098463de4c5d 136 } else {
group-onsemi 0:098463de4c5d 137 LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
group-onsemi 0:098463de4c5d 138 }
group-onsemi 0:098463de4c5d 139 break;
group-onsemi 0:098463de4c5d 140 case LPC_GPIO2_BASE:
group-onsemi 0:098463de4c5d 141 if (enable) {
group-onsemi 0:098463de4c5d 142 LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
group-onsemi 0:098463de4c5d 143 } else {
group-onsemi 0:098463de4c5d 144 LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
group-onsemi 0:098463de4c5d 145 }
group-onsemi 0:098463de4c5d 146 break;
group-onsemi 0:098463de4c5d 147 }
group-onsemi 0:098463de4c5d 148 } else {
group-onsemi 0:098463de4c5d 149 switch (obj->port) {
group-onsemi 0:098463de4c5d 150 case LPC_GPIO0_BASE:
group-onsemi 0:098463de4c5d 151 if (enable) {
group-onsemi 0:098463de4c5d 152 LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
group-onsemi 0:098463de4c5d 153 } else {
group-onsemi 0:098463de4c5d 154 LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
group-onsemi 0:098463de4c5d 155 }
group-onsemi 0:098463de4c5d 156 break;
group-onsemi 0:098463de4c5d 157 case LPC_GPIO2_BASE:
group-onsemi 0:098463de4c5d 158 if (enable) {
group-onsemi 0:098463de4c5d 159 LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
group-onsemi 0:098463de4c5d 160 } else {
group-onsemi 0:098463de4c5d 161 LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
group-onsemi 0:098463de4c5d 162 }
group-onsemi 0:098463de4c5d 163 break;
group-onsemi 0:098463de4c5d 164 }
group-onsemi 0:098463de4c5d 165 }
group-onsemi 0:098463de4c5d 166 }
group-onsemi 0:098463de4c5d 167
group-onsemi 0:098463de4c5d 168 void gpio_irq_enable(gpio_irq_t *obj) {
group-onsemi 0:098463de4c5d 169 NVIC_EnableIRQ(GPIO_IRQn);
group-onsemi 0:098463de4c5d 170 }
group-onsemi 0:098463de4c5d 171
group-onsemi 0:098463de4c5d 172 void gpio_irq_disable(gpio_irq_t *obj) {
group-onsemi 0:098463de4c5d 173 NVIC_DisableIRQ(GPIO_IRQn);
group-onsemi 0:098463de4c5d 174 }