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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NXP/TARGET_LPC15XX/serial_api.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2013 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 // math.h required for floating point operations for baud rate calculation
group-onsemi 0:098463de4c5d 17 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 18 #include <math.h>
group-onsemi 0:098463de4c5d 19 #include <string.h>
group-onsemi 0:098463de4c5d 20
group-onsemi 0:098463de4c5d 21 #include "serial_api.h"
group-onsemi 0:098463de4c5d 22 #include "cmsis.h"
group-onsemi 0:098463de4c5d 23 #include "pinmap.h"
group-onsemi 0:098463de4c5d 24 #include "mbed_error.h"
group-onsemi 0:098463de4c5d 25
group-onsemi 0:098463de4c5d 26 /******************************************************************************
group-onsemi 0:098463de4c5d 27 * INITIALIZATION
group-onsemi 0:098463de4c5d 28 ******************************************************************************/
group-onsemi 0:098463de4c5d 29 #define UART_NUM 3
group-onsemi 0:098463de4c5d 30
group-onsemi 0:098463de4c5d 31 static const SWM_Map SWM_UART_TX[] = {
group-onsemi 0:098463de4c5d 32 {0, 0}, // Pin assign register0, 7:0bit
group-onsemi 0:098463de4c5d 33 {1, 8}, // Pin assign register1, 15:8bit
group-onsemi 0:098463de4c5d 34 {2, 16}, // Pin assign register2, 23:16bit
group-onsemi 0:098463de4c5d 35 };
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 static const SWM_Map SWM_UART_RX[] = {
group-onsemi 0:098463de4c5d 38 {0, 8},
group-onsemi 0:098463de4c5d 39 {1, 16},
group-onsemi 0:098463de4c5d 40 {2, 24},
group-onsemi 0:098463de4c5d 41 };
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 static const SWM_Map SWM_UART_RTS[] = {
group-onsemi 0:098463de4c5d 44 {0, 16},
group-onsemi 0:098463de4c5d 45 {1, 24},
group-onsemi 0:098463de4c5d 46 {3, 0}, // not available
group-onsemi 0:098463de4c5d 47 };
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49 static const SWM_Map SWM_UART_CTS[] = {
group-onsemi 0:098463de4c5d 50 {0, 24},
group-onsemi 0:098463de4c5d 51 {2, 0},
group-onsemi 0:098463de4c5d 52 {3, 8} // not available
group-onsemi 0:098463de4c5d 53 };
group-onsemi 0:098463de4c5d 54
group-onsemi 0:098463de4c5d 55 // bit flags for used UARTs
group-onsemi 0:098463de4c5d 56 static unsigned char uart_used = 0;
group-onsemi 0:098463de4c5d 57 static int get_available_uart(void) {
group-onsemi 0:098463de4c5d 58 int i;
group-onsemi 0:098463de4c5d 59 for (i=0; i<3; i++) {
group-onsemi 0:098463de4c5d 60 if ((uart_used & (1 << i)) == 0)
group-onsemi 0:098463de4c5d 61 return i;
group-onsemi 0:098463de4c5d 62 }
group-onsemi 0:098463de4c5d 63 return -1;
group-onsemi 0:098463de4c5d 64 }
group-onsemi 0:098463de4c5d 65
group-onsemi 0:098463de4c5d 66 #define UART_EN (0x01<<0)
group-onsemi 0:098463de4c5d 67
group-onsemi 0:098463de4c5d 68 #define CTS_DELTA (0x01<<5)
group-onsemi 0:098463de4c5d 69 #define RXBRK (0x01<<10)
group-onsemi 0:098463de4c5d 70 #define DELTA_RXBRK (0x01<<11)
group-onsemi 0:098463de4c5d 71
group-onsemi 0:098463de4c5d 72 #define RXRDY (0x01<<0)
group-onsemi 0:098463de4c5d 73 #define TXRDY (0x01<<2)
group-onsemi 0:098463de4c5d 74
group-onsemi 0:098463de4c5d 75 #define TXBRKEN (0x01<<1)
group-onsemi 0:098463de4c5d 76 #define CTSEN (0x01<<9)
group-onsemi 0:098463de4c5d 77
group-onsemi 0:098463de4c5d 78 static uint32_t UARTSysClk;
group-onsemi 0:098463de4c5d 79
group-onsemi 0:098463de4c5d 80 static uint32_t serial_irq_ids[UART_NUM] = {0};
group-onsemi 0:098463de4c5d 81 static uart_irq_handler irq_handler;
group-onsemi 0:098463de4c5d 82
group-onsemi 0:098463de4c5d 83 int stdio_uart_inited = 0;
group-onsemi 0:098463de4c5d 84 serial_t stdio_uart;
group-onsemi 0:098463de4c5d 85
group-onsemi 0:098463de4c5d 86 static void switch_pin(const SWM_Map *swm, PinName pn)
group-onsemi 0:098463de4c5d 87 {
group-onsemi 0:098463de4c5d 88 uint32_t regVal;
group-onsemi 0:098463de4c5d 89 if (pn != NC)
group-onsemi 0:098463de4c5d 90 {
group-onsemi 0:098463de4c5d 91 // check if we have any function mapped to this pin already and remove it
group-onsemi 0:098463de4c5d 92 for (uint32_t n = 0; n < sizeof(LPC_SWM->PINASSIGN)/sizeof(*LPC_SWM->PINASSIGN); n ++) {
group-onsemi 0:098463de4c5d 93 regVal = LPC_SWM->PINASSIGN[n];
group-onsemi 0:098463de4c5d 94 for (uint32_t j = 0; j <= 24; j += 8) {
group-onsemi 0:098463de4c5d 95 if (((regVal >> j) & 0xFF) == (uint32_t)pn)
group-onsemi 0:098463de4c5d 96 regVal |= (0xFF << j);
group-onsemi 0:098463de4c5d 97 }
group-onsemi 0:098463de4c5d 98 LPC_SWM->PINASSIGN[n] = regVal;
group-onsemi 0:098463de4c5d 99 }
group-onsemi 0:098463de4c5d 100 }
group-onsemi 0:098463de4c5d 101 // now map it
group-onsemi 0:098463de4c5d 102 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
group-onsemi 0:098463de4c5d 103 LPC_SWM->PINASSIGN[swm->n] = regVal | (pn << swm->offset);
group-onsemi 0:098463de4c5d 104 }
group-onsemi 0:098463de4c5d 105
group-onsemi 0:098463de4c5d 106 void serial_init(serial_t *obj, PinName tx, PinName rx) {
group-onsemi 0:098463de4c5d 107 int is_stdio_uart = 0;
group-onsemi 0:098463de4c5d 108
group-onsemi 0:098463de4c5d 109 int uart_n = get_available_uart();
group-onsemi 0:098463de4c5d 110 if (uart_n == -1) {
group-onsemi 0:098463de4c5d 111 error("No available UART");
group-onsemi 0:098463de4c5d 112 }
group-onsemi 0:098463de4c5d 113 obj->index = uart_n;
group-onsemi 0:098463de4c5d 114 switch (uart_n) {
group-onsemi 0:098463de4c5d 115 case 0: obj->uart = (LPC_USART0_Type *)LPC_USART0_BASE; break;
group-onsemi 0:098463de4c5d 116 case 1: obj->uart = (LPC_USART0_Type *)LPC_USART1_BASE; break;
group-onsemi 0:098463de4c5d 117 case 2: obj->uart = (LPC_USART0_Type *)LPC_USART2_BASE; break;
group-onsemi 0:098463de4c5d 118 }
group-onsemi 0:098463de4c5d 119 uart_used |= (1 << uart_n);
group-onsemi 0:098463de4c5d 120
group-onsemi 0:098463de4c5d 121 switch_pin(&SWM_UART_TX[uart_n], tx);
group-onsemi 0:098463de4c5d 122 switch_pin(&SWM_UART_RX[uart_n], rx);
group-onsemi 0:098463de4c5d 123
group-onsemi 0:098463de4c5d 124 /* uart clock divided by 6 */
group-onsemi 0:098463de4c5d 125 LPC_SYSCON->UARTCLKDIV =6;
group-onsemi 0:098463de4c5d 126
group-onsemi 0:098463de4c5d 127 /* disable uart interrupts */
group-onsemi 0:098463de4c5d 128 NVIC_DisableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
group-onsemi 0:098463de4c5d 129
group-onsemi 0:098463de4c5d 130 /* Enable UART clock */
group-onsemi 0:098463de4c5d 131 LPC_SYSCON->SYSAHBCLKCTRL1 |= (1 << (17 + uart_n));
group-onsemi 0:098463de4c5d 132
group-onsemi 0:098463de4c5d 133 /* Peripheral reset control to UART, a "1" bring it out of reset. */
group-onsemi 0:098463de4c5d 134 LPC_SYSCON->PRESETCTRL1 |= (0x1 << (17 + uart_n));
group-onsemi 0:098463de4c5d 135 LPC_SYSCON->PRESETCTRL1 &= ~(0x1 << (17 + uart_n));
group-onsemi 0:098463de4c5d 136
group-onsemi 0:098463de4c5d 137 UARTSysClk = SystemCoreClock / LPC_SYSCON->UARTCLKDIV;
group-onsemi 0:098463de4c5d 138
group-onsemi 0:098463de4c5d 139 // set default baud rate and format
group-onsemi 0:098463de4c5d 140 serial_baud (obj, 9600);
group-onsemi 0:098463de4c5d 141 serial_format(obj, 8, ParityNone, 1);
group-onsemi 0:098463de4c5d 142
group-onsemi 0:098463de4c5d 143 /* Clear all status bits. */
group-onsemi 0:098463de4c5d 144 obj->uart->STAT = CTS_DELTA | DELTA_RXBRK;
group-onsemi 0:098463de4c5d 145
group-onsemi 0:098463de4c5d 146 /* enable uart interrupts */
group-onsemi 0:098463de4c5d 147 NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
group-onsemi 0:098463de4c5d 148
group-onsemi 0:098463de4c5d 149 /* Enable UART */
group-onsemi 0:098463de4c5d 150 obj->uart->CFG |= UART_EN;
group-onsemi 0:098463de4c5d 151
group-onsemi 0:098463de4c5d 152 is_stdio_uart = ((tx == USBTX) && (rx == USBRX));
group-onsemi 0:098463de4c5d 153
group-onsemi 0:098463de4c5d 154 if (is_stdio_uart) {
group-onsemi 0:098463de4c5d 155 stdio_uart_inited = 1;
group-onsemi 0:098463de4c5d 156 memcpy(&stdio_uart, obj, sizeof(serial_t));
group-onsemi 0:098463de4c5d 157 }
group-onsemi 0:098463de4c5d 158 }
group-onsemi 0:098463de4c5d 159
group-onsemi 0:098463de4c5d 160 void serial_free(serial_t *obj) {
group-onsemi 0:098463de4c5d 161 uart_used &= ~(1 << obj->index);
group-onsemi 0:098463de4c5d 162 serial_irq_ids[obj->index] = 0;
group-onsemi 0:098463de4c5d 163 }
group-onsemi 0:098463de4c5d 164
group-onsemi 0:098463de4c5d 165 // serial_baud
group-onsemi 0:098463de4c5d 166 // set the baud rate, taking in to account the current SystemFrequency
group-onsemi 0:098463de4c5d 167 void serial_baud(serial_t *obj, int baudrate) {
group-onsemi 0:098463de4c5d 168 /* Integer divider:
group-onsemi 0:098463de4c5d 169 BRG = UARTSysClk/(Baudrate * 16) - 1
group-onsemi 0:098463de4c5d 170
group-onsemi 0:098463de4c5d 171 Frational divider:
group-onsemi 0:098463de4c5d 172 FRG = ((UARTSysClk / (Baudrate * 16 * (BRG + 1))) - 1)
group-onsemi 0:098463de4c5d 173
group-onsemi 0:098463de4c5d 174 where
group-onsemi 0:098463de4c5d 175 FRG = (LPC_SYSCON->UARTFRDADD + 1) / (LPC_SYSCON->UARTFRDSUB + 1)
group-onsemi 0:098463de4c5d 176
group-onsemi 0:098463de4c5d 177 (1) The easiest way is set SUB value to 256, -1 encoded, thus SUB
group-onsemi 0:098463de4c5d 178 register is 0xFF.
group-onsemi 0:098463de4c5d 179 (2) In ADD register value, depending on the value of UartSysClk,
group-onsemi 0:098463de4c5d 180 baudrate, BRG register value, and SUB register value, be careful
group-onsemi 0:098463de4c5d 181 about the order of multiplier and divider and make sure any
group-onsemi 0:098463de4c5d 182 multiplier doesn't exceed 32-bit boundary and any divider doesn't get
group-onsemi 0:098463de4c5d 183 down below one(integer 0).
group-onsemi 0:098463de4c5d 184 (3) ADD should be always less than SUB.
group-onsemi 0:098463de4c5d 185 */
group-onsemi 0:098463de4c5d 186 obj->uart->BRG = UARTSysClk / 16 / baudrate - 1;
group-onsemi 0:098463de4c5d 187
group-onsemi 0:098463de4c5d 188 // To use of the fractional baud rate generator, you must write 0xFF to the DIV
group-onsemi 0:098463de4c5d 189 // value to yield a denominator value of 256. All other values are not supported.
group-onsemi 0:098463de4c5d 190 LPC_SYSCON->FRGCTRL = 0xFF;
group-onsemi 0:098463de4c5d 191
group-onsemi 0:098463de4c5d 192 LPC_SYSCON->FRGCTRL |= ( ( ((UARTSysClk / 16) * (0xFF + 1)) /
group-onsemi 0:098463de4c5d 193 (baudrate * (obj->uart->BRG + 1))
group-onsemi 0:098463de4c5d 194 ) - (0xFF + 1) ) << 8;
group-onsemi 0:098463de4c5d 195
group-onsemi 0:098463de4c5d 196 }
group-onsemi 0:098463de4c5d 197
group-onsemi 0:098463de4c5d 198 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
group-onsemi 0:098463de4c5d 199 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
group-onsemi 0:098463de4c5d 200 MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits
group-onsemi 0:098463de4c5d 201 MBED_ASSERT((parity == ParityNone) || (parity == ParityEven) || (parity == ParityOdd));
group-onsemi 0:098463de4c5d 202
group-onsemi 0:098463de4c5d 203 stop_bits -= 1;
group-onsemi 0:098463de4c5d 204 data_bits -= 7;
group-onsemi 0:098463de4c5d 205
group-onsemi 0:098463de4c5d 206 int paritysel;
group-onsemi 0:098463de4c5d 207 switch (parity) {
group-onsemi 0:098463de4c5d 208 case ParityNone: paritysel = 0; break;
group-onsemi 0:098463de4c5d 209 case ParityEven: paritysel = 2; break;
group-onsemi 0:098463de4c5d 210 case ParityOdd : paritysel = 3; break;
group-onsemi 0:098463de4c5d 211 default:
group-onsemi 0:098463de4c5d 212 break;
group-onsemi 0:098463de4c5d 213 }
group-onsemi 0:098463de4c5d 214
group-onsemi 0:098463de4c5d 215 // First disable the the usart as described in documentation and then enable while updating CFG
group-onsemi 0:098463de4c5d 216
group-onsemi 0:098463de4c5d 217 // 24.6.1 USART Configuration register
group-onsemi 0:098463de4c5d 218 // Remark: If software needs to change configuration values, the following sequence should
group-onsemi 0:098463de4c5d 219 // be used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable
group-onsemi 0:098463de4c5d 220 // the USART by writing a 0 to the Enable bit (0 may be written to the entire register). 3)
group-onsemi 0:098463de4c5d 221 // Write the new configuration value, with the ENABLE bit set to 1.
group-onsemi 0:098463de4c5d 222 obj->uart->CFG &= ~(1 << 0);
group-onsemi 0:098463de4c5d 223
group-onsemi 0:098463de4c5d 224 obj->uart->CFG = (1 << 0) // this will enable the usart
group-onsemi 0:098463de4c5d 225 | (data_bits << 2)
group-onsemi 0:098463de4c5d 226 | (paritysel << 4)
group-onsemi 0:098463de4c5d 227 | (stop_bits << 6);
group-onsemi 0:098463de4c5d 228 }
group-onsemi 0:098463de4c5d 229
group-onsemi 0:098463de4c5d 230 /******************************************************************************
group-onsemi 0:098463de4c5d 231 * INTERRUPTS HANDLING
group-onsemi 0:098463de4c5d 232 ******************************************************************************/
group-onsemi 0:098463de4c5d 233 static inline void uart_irq(SerialIrq irq_type, uint32_t index) {
group-onsemi 0:098463de4c5d 234 if (serial_irq_ids[index] != 0)
group-onsemi 0:098463de4c5d 235 irq_handler(serial_irq_ids[index], irq_type);
group-onsemi 0:098463de4c5d 236 }
group-onsemi 0:098463de4c5d 237
group-onsemi 0:098463de4c5d 238 void uart0_irq() {uart_irq((LPC_USART0->INTSTAT & 1) ? RxIrq : TxIrq, 0);}
group-onsemi 0:098463de4c5d 239 void uart1_irq() {uart_irq((LPC_USART1->INTSTAT & 1) ? RxIrq : TxIrq, 1);}
group-onsemi 0:098463de4c5d 240 void uart2_irq() {uart_irq((LPC_USART2->INTSTAT & 1) ? RxIrq : TxIrq, 2);}
group-onsemi 0:098463de4c5d 241
group-onsemi 0:098463de4c5d 242 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
group-onsemi 0:098463de4c5d 243 irq_handler = handler;
group-onsemi 0:098463de4c5d 244 serial_irq_ids[obj->index] = id;
group-onsemi 0:098463de4c5d 245 }
group-onsemi 0:098463de4c5d 246
group-onsemi 0:098463de4c5d 247 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
group-onsemi 0:098463de4c5d 248 IRQn_Type irq_n = (IRQn_Type)0;
group-onsemi 0:098463de4c5d 249 uint32_t vector = 0;
group-onsemi 0:098463de4c5d 250 switch ((int)obj->uart) {
group-onsemi 0:098463de4c5d 251 case LPC_USART0_BASE: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
group-onsemi 0:098463de4c5d 252 case LPC_USART1_BASE: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
group-onsemi 0:098463de4c5d 253 case LPC_USART2_BASE: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
group-onsemi 0:098463de4c5d 254 }
group-onsemi 0:098463de4c5d 255
group-onsemi 0:098463de4c5d 256 if (enable) {
group-onsemi 0:098463de4c5d 257 NVIC_DisableIRQ(irq_n);
group-onsemi 0:098463de4c5d 258 obj->uart->INTENSET |= (1 << ((irq == RxIrq) ? 0 : 2));
group-onsemi 0:098463de4c5d 259 NVIC_SetVector(irq_n, vector);
group-onsemi 0:098463de4c5d 260 NVIC_EnableIRQ(irq_n);
group-onsemi 0:098463de4c5d 261 } else { // disable
group-onsemi 0:098463de4c5d 262 int all_disabled = 0;
group-onsemi 0:098463de4c5d 263 SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
group-onsemi 0:098463de4c5d 264 obj->uart->INTENCLR |= (1 << ((irq == RxIrq) ? 0 : 2)); // disable the interrupt
group-onsemi 0:098463de4c5d 265 all_disabled = (obj->uart->INTENSET & (1 << ((other_irq == RxIrq) ? 0 : 2))) == 0;
group-onsemi 0:098463de4c5d 266 if (all_disabled)
group-onsemi 0:098463de4c5d 267 NVIC_DisableIRQ(irq_n);
group-onsemi 0:098463de4c5d 268 }
group-onsemi 0:098463de4c5d 269 }
group-onsemi 0:098463de4c5d 270
group-onsemi 0:098463de4c5d 271 /******************************************************************************
group-onsemi 0:098463de4c5d 272 * READ/WRITE
group-onsemi 0:098463de4c5d 273 ******************************************************************************/
group-onsemi 0:098463de4c5d 274 int serial_getc(serial_t *obj) {
group-onsemi 0:098463de4c5d 275 while (!serial_readable(obj));
group-onsemi 0:098463de4c5d 276 return obj->uart->RXDATA;
group-onsemi 0:098463de4c5d 277 }
group-onsemi 0:098463de4c5d 278
group-onsemi 0:098463de4c5d 279 void serial_putc(serial_t *obj, int c) {
group-onsemi 0:098463de4c5d 280 while (!serial_writable(obj));
group-onsemi 0:098463de4c5d 281 obj->uart->TXDATA = c;
group-onsemi 0:098463de4c5d 282 }
group-onsemi 0:098463de4c5d 283
group-onsemi 0:098463de4c5d 284 int serial_readable(serial_t *obj) {
group-onsemi 0:098463de4c5d 285 return obj->uart->STAT & RXRDY;
group-onsemi 0:098463de4c5d 286 }
group-onsemi 0:098463de4c5d 287
group-onsemi 0:098463de4c5d 288 int serial_writable(serial_t *obj) {
group-onsemi 0:098463de4c5d 289 return obj->uart->STAT & TXRDY;
group-onsemi 0:098463de4c5d 290 }
group-onsemi 0:098463de4c5d 291
group-onsemi 0:098463de4c5d 292 void serial_clear(serial_t *obj) {
group-onsemi 0:098463de4c5d 293 // [TODO]
group-onsemi 0:098463de4c5d 294 }
group-onsemi 0:098463de4c5d 295
group-onsemi 0:098463de4c5d 296 void serial_pinout_tx(PinName tx) {
group-onsemi 0:098463de4c5d 297
group-onsemi 0:098463de4c5d 298 }
group-onsemi 0:098463de4c5d 299
group-onsemi 0:098463de4c5d 300 void serial_break_set(serial_t *obj) {
group-onsemi 0:098463de4c5d 301 obj->uart->CTRL |= TXBRKEN;
group-onsemi 0:098463de4c5d 302 }
group-onsemi 0:098463de4c5d 303
group-onsemi 0:098463de4c5d 304 void serial_break_clear(serial_t *obj) {
group-onsemi 0:098463de4c5d 305 obj->uart->CTRL &= ~TXBRKEN;
group-onsemi 0:098463de4c5d 306 }
group-onsemi 0:098463de4c5d 307
group-onsemi 0:098463de4c5d 308 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
group-onsemi 0:098463de4c5d 309 if ((FlowControlNone == type || FlowControlRTS == type)) txflow = NC;
group-onsemi 0:098463de4c5d 310 if ((FlowControlNone == type || FlowControlCTS == type)) rxflow = NC;
group-onsemi 0:098463de4c5d 311 switch_pin(&SWM_UART_RTS[obj->index], rxflow);
group-onsemi 0:098463de4c5d 312 switch_pin(&SWM_UART_CTS[obj->index], txflow);
group-onsemi 0:098463de4c5d 313 if (txflow == NC) obj->uart->CFG &= ~CTSEN;
group-onsemi 0:098463de4c5d 314 else obj->uart->CFG |= CTSEN;
group-onsemi 0:098463de4c5d 315 }
group-onsemi 0:098463de4c5d 316