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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NXP/TARGET_LPC13XX/device/LPC13Uxx.h@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1
group-onsemi 0:098463de4c5d 2 /****************************************************************************************************//**
group-onsemi 0:098463de4c5d 3 * @file LPC13Uxx.h
group-onsemi 0:098463de4c5d 4 *
group-onsemi 0:098463de4c5d 5 *
group-onsemi 0:098463de4c5d 6 *
group-onsemi 0:098463de4c5d 7 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
group-onsemi 0:098463de4c5d 8 * default LPC13Uxx Device Series
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * @version V0.1
group-onsemi 0:098463de4c5d 11 * @date 18. Jan 2012
group-onsemi 0:098463de4c5d 12 *
group-onsemi 0:098463de4c5d 13 * @note Generated with SFDGen V2.6 Build 4f on Tuesday, 17.01.2012 13:39:52
group-onsemi 0:098463de4c5d 14 *
group-onsemi 0:098463de4c5d 15 * from CMSIS SVD File 'LPC13uxx_svd_v0.1.xml' Version 0.1,
group-onsemi 0:098463de4c5d 16 * created on Thurs, 01.19.2012 15:13:15, last modified on Thurs, 01.19.2012 15:53:09
group-onsemi 0:098463de4c5d 17 *
group-onsemi 0:098463de4c5d 18 *******************************************************************************************************/
group-onsemi 0:098463de4c5d 19
group-onsemi 0:098463de4c5d 20 /** @addtogroup NXP
group-onsemi 0:098463de4c5d 21 * @{
group-onsemi 0:098463de4c5d 22 */
group-onsemi 0:098463de4c5d 23
group-onsemi 0:098463de4c5d 24 /** @addtogroup LPC13Uxx
group-onsemi 0:098463de4c5d 25 * @{
group-onsemi 0:098463de4c5d 26 */
group-onsemi 0:098463de4c5d 27
group-onsemi 0:098463de4c5d 28 #ifndef __LPC13UXX_H__
group-onsemi 0:098463de4c5d 29 #define __LPC13UXX_H__
group-onsemi 0:098463de4c5d 30
group-onsemi 0:098463de4c5d 31 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 32 extern "C" {
group-onsemi 0:098463de4c5d 33 #endif
group-onsemi 0:098463de4c5d 34
group-onsemi 0:098463de4c5d 35
group-onsemi 0:098463de4c5d 36 #if defined ( __CC_ARM )
group-onsemi 0:098463de4c5d 37 #pragma anon_unions
group-onsemi 0:098463de4c5d 38 #endif
group-onsemi 0:098463de4c5d 39
group-onsemi 0:098463de4c5d 40 /* Interrupt Number Definition */
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 typedef enum {
group-onsemi 0:098463de4c5d 43 // ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
group-onsemi 0:098463de4c5d 44 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
group-onsemi 0:098463de4c5d 45 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
group-onsemi 0:098463de4c5d 46 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
group-onsemi 0:098463de4c5d 47 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
group-onsemi 0:098463de4c5d 48 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
group-onsemi 0:098463de4c5d 49 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
group-onsemi 0:098463de4c5d 50 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
group-onsemi 0:098463de4c5d 51 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
group-onsemi 0:098463de4c5d 52 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
group-onsemi 0:098463de4c5d 53 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
group-onsemi 0:098463de4c5d 54 // ---------------------------- LPC13Uxx Specific Interrupt Numbers --------------------------------
group-onsemi 0:098463de4c5d 55 PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
group-onsemi 0:098463de4c5d 56 PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
group-onsemi 0:098463de4c5d 57 PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
group-onsemi 0:098463de4c5d 58 PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
group-onsemi 0:098463de4c5d 59 PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
group-onsemi 0:098463de4c5d 60 PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
group-onsemi 0:098463de4c5d 61 PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
group-onsemi 0:098463de4c5d 62 PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
group-onsemi 0:098463de4c5d 63 GINT0_IRQn = 8, /*!< 8 GINT0 */
group-onsemi 0:098463de4c5d 64 GINT1_IRQn = 9, /*!< 9 GINT1 */
group-onsemi 0:098463de4c5d 65 Reserved0_IRQn = 10, /*!< 10 Reserved Interrupt */
group-onsemi 0:098463de4c5d 66 Reserved1_IRQn = 11, /*!< 11 Reserved Interrupt */
group-onsemi 0:098463de4c5d 67 RIT_IRQn = 12, /*!< 12 Repetitive Interrupt Timer */
group-onsemi 0:098463de4c5d 68 Reserved2_IRQn = 13, /*!< 13 Reserved Interrupt */
group-onsemi 0:098463de4c5d 69 SSP1_IRQn = 14, /*!< 14 SSP1 */
group-onsemi 0:098463de4c5d 70 I2C_IRQn = 15, /*!< 15 I2C */
group-onsemi 0:098463de4c5d 71 CT16B0_IRQn = 16, /*!< 16 CT16B0 */
group-onsemi 0:098463de4c5d 72 CT16B1_IRQn = 17, /*!< 17 CT16B1 */
group-onsemi 0:098463de4c5d 73 CT32B0_IRQn = 18, /*!< 18 CT32B0 */
group-onsemi 0:098463de4c5d 74 CT32B1_IRQn = 19, /*!< 19 CT32B1 */
group-onsemi 0:098463de4c5d 75 SSP0_IRQn = 20, /*!< 20 SSP0 */
group-onsemi 0:098463de4c5d 76 USART_IRQn = 21, /*!< 21 USART */
group-onsemi 0:098463de4c5d 77 USB_IRQ_IRQn = 22, /*!< 22 USB_IRQ */
group-onsemi 0:098463de4c5d 78 USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
group-onsemi 0:098463de4c5d 79 ADC_IRQn = 24, /*!< 24 ADC */
group-onsemi 0:098463de4c5d 80 WDT_IRQn = 25, /*!< 25 WDT */
group-onsemi 0:098463de4c5d 81 BOD_IRQn = 26, /*!< 26 BOD */
group-onsemi 0:098463de4c5d 82 FMC_IRQn = 27, /*!< 27 FMC */
group-onsemi 0:098463de4c5d 83 Reserved3_IRQn = 28, /*!< 28 Reserved Interrupt */
group-onsemi 0:098463de4c5d 84 Reserved4_IRQn = 29, /*!< 29 Reserved Interrupt */
group-onsemi 0:098463de4c5d 85 USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
group-onsemi 0:098463de4c5d 86 Reserved5_IRQn = 31, /*!< 31 Reserved Interrupt */
group-onsemi 0:098463de4c5d 87 } IRQn_Type;
group-onsemi 0:098463de4c5d 88
group-onsemi 0:098463de4c5d 89
group-onsemi 0:098463de4c5d 90 /** @addtogroup Configuration_of_CMSIS
group-onsemi 0:098463de4c5d 91 * @{
group-onsemi 0:098463de4c5d 92 */
group-onsemi 0:098463de4c5d 93
group-onsemi 0:098463de4c5d 94 /* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
group-onsemi 0:098463de4c5d 95
group-onsemi 0:098463de4c5d 96 #define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */
group-onsemi 0:098463de4c5d 97 #define __MPU_PRESENT 0 /*!< MPU present or not */
group-onsemi 0:098463de4c5d 98 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
group-onsemi 0:098463de4c5d 99 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
group-onsemi 0:098463de4c5d 100 /** @} */ /* End of group Configuration_of_CMSIS */
group-onsemi 0:098463de4c5d 101
group-onsemi 0:098463de4c5d 102 #include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
group-onsemi 0:098463de4c5d 103 #include "system_LPC13Uxx.h" /*!< LPC13Uxx System */
group-onsemi 0:098463de4c5d 104
group-onsemi 0:098463de4c5d 105 /** @addtogroup Device_Peripheral_Registers
group-onsemi 0:098463de4c5d 106 * @{
group-onsemi 0:098463de4c5d 107 */
group-onsemi 0:098463de4c5d 108
group-onsemi 0:098463de4c5d 109
group-onsemi 0:098463de4c5d 110 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 111 // ----- I2C -----
group-onsemi 0:098463de4c5d 112 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 113
group-onsemi 0:098463de4c5d 114
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 typedef struct { /*!< (@ 0x40000000) I2C Structure */
group-onsemi 0:098463de4c5d 117 __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
group-onsemi 0:098463de4c5d 118 __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
group-onsemi 0:098463de4c5d 119 __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
group-onsemi 0:098463de4c5d 120 __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
group-onsemi 0:098463de4c5d 121 __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
group-onsemi 0:098463de4c5d 122 __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
group-onsemi 0:098463de4c5d 123 __O uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
group-onsemi 0:098463de4c5d 124 __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register. */
group-onsemi 0:098463de4c5d 125 union{
group-onsemi 0:098463de4c5d 126 __IO uint32_t ADR[3]; /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
group-onsemi 0:098463de4c5d 127 struct{
group-onsemi 0:098463de4c5d 128 __IO uint32_t ADR1;
group-onsemi 0:098463de4c5d 129 __IO uint32_t ADR2;
group-onsemi 0:098463de4c5d 130 __IO uint32_t ADR3;
group-onsemi 0:098463de4c5d 131 };
group-onsemi 0:098463de4c5d 132 };
group-onsemi 0:098463de4c5d 133 __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
group-onsemi 0:098463de4c5d 134 union{
group-onsemi 0:098463de4c5d 135 __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
group-onsemi 0:098463de4c5d 136 struct{
group-onsemi 0:098463de4c5d 137 __IO uint32_t MASK0;
group-onsemi 0:098463de4c5d 138 __IO uint32_t MASK1;
group-onsemi 0:098463de4c5d 139 __IO uint32_t MASK2;
group-onsemi 0:098463de4c5d 140 __IO uint32_t MASK3;
group-onsemi 0:098463de4c5d 141 };
group-onsemi 0:098463de4c5d 142 };
group-onsemi 0:098463de4c5d 143 } LPC_I2C_Type;
group-onsemi 0:098463de4c5d 144
group-onsemi 0:098463de4c5d 145
group-onsemi 0:098463de4c5d 146 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 147 // ----- WWDT -----
group-onsemi 0:098463de4c5d 148 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 149
group-onsemi 0:098463de4c5d 150
group-onsemi 0:098463de4c5d 151 typedef struct { /*!< (@ 0x40004000) WWDT Structure */
group-onsemi 0:098463de4c5d 152 __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
group-onsemi 0:098463de4c5d 153 __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
group-onsemi 0:098463de4c5d 154 __O uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
group-onsemi 0:098463de4c5d 155 __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
group-onsemi 0:098463de4c5d 156 __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
group-onsemi 0:098463de4c5d 157 __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
group-onsemi 0:098463de4c5d 158 __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
group-onsemi 0:098463de4c5d 159 } LPC_WWDT_Type;
group-onsemi 0:098463de4c5d 160
group-onsemi 0:098463de4c5d 161
group-onsemi 0:098463de4c5d 162 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 163 // ----- USART -----
group-onsemi 0:098463de4c5d 164 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 165
group-onsemi 0:098463de4c5d 166
group-onsemi 0:098463de4c5d 167 typedef struct { /*!< (@ 0x40008000) USART Structure */
group-onsemi 0:098463de4c5d 168
group-onsemi 0:098463de4c5d 169 union {
group-onsemi 0:098463de4c5d 170 __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
group-onsemi 0:098463de4c5d 171 __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
group-onsemi 0:098463de4c5d 172 __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
group-onsemi 0:098463de4c5d 173 };
group-onsemi 0:098463de4c5d 174
group-onsemi 0:098463de4c5d 175 union {
group-onsemi 0:098463de4c5d 176 __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
group-onsemi 0:098463de4c5d 177 __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
group-onsemi 0:098463de4c5d 178 };
group-onsemi 0:098463de4c5d 179
group-onsemi 0:098463de4c5d 180 union {
group-onsemi 0:098463de4c5d 181 __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
group-onsemi 0:098463de4c5d 182 __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
group-onsemi 0:098463de4c5d 183 };
group-onsemi 0:098463de4c5d 184 __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
group-onsemi 0:098463de4c5d 185 __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
group-onsemi 0:098463de4c5d 186 __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
group-onsemi 0:098463de4c5d 187 __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
group-onsemi 0:098463de4c5d 188 __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
group-onsemi 0:098463de4c5d 189 __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
group-onsemi 0:098463de4c5d 190 __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
group-onsemi 0:098463de4c5d 191 __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
group-onsemi 0:098463de4c5d 192 __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
group-onsemi 0:098463de4c5d 193 __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
group-onsemi 0:098463de4c5d 194 __I uint32_t RESERVED0[3];
group-onsemi 0:098463de4c5d 195 __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
group-onsemi 0:098463de4c5d 196 __I uint32_t RESERVED1;
group-onsemi 0:098463de4c5d 197 __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
group-onsemi 0:098463de4c5d 198 __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
group-onsemi 0:098463de4c5d 199 __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
group-onsemi 0:098463de4c5d 200 __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
group-onsemi 0:098463de4c5d 201 __IO uint32_t SYNCCTRL; /*!< (@ 0x40008058) Synchronous mode control register. */
group-onsemi 0:098463de4c5d 202 } LPC_USART_Type;
group-onsemi 0:098463de4c5d 203
group-onsemi 0:098463de4c5d 204
group-onsemi 0:098463de4c5d 205 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 206 // ----- CT16B0 -----
group-onsemi 0:098463de4c5d 207 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 208
group-onsemi 0:098463de4c5d 209 typedef struct { /*!< (@ 0x4000C000) LPC_CTxxBx_Type Structure */
group-onsemi 0:098463de4c5d 210 __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
group-onsemi 0:098463de4c5d 211 __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
group-onsemi 0:098463de4c5d 212 __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
group-onsemi 0:098463de4c5d 213 __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
group-onsemi 0:098463de4c5d 214 __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
group-onsemi 0:098463de4c5d 215 __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
group-onsemi 0:098463de4c5d 216 union {
group-onsemi 0:098463de4c5d 217 __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
group-onsemi 0:098463de4c5d 218 struct{
group-onsemi 0:098463de4c5d 219 __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
group-onsemi 0:098463de4c5d 220 __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
group-onsemi 0:098463de4c5d 221 __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
group-onsemi 0:098463de4c5d 222 __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
group-onsemi 0:098463de4c5d 223 };
group-onsemi 0:098463de4c5d 224 };
group-onsemi 0:098463de4c5d 225 __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
group-onsemi 0:098463de4c5d 226 union{
group-onsemi 0:098463de4c5d 227 __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
group-onsemi 0:098463de4c5d 228 struct{
group-onsemi 0:098463de4c5d 229 __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
group-onsemi 0:098463de4c5d 230 __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
group-onsemi 0:098463de4c5d 231 __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
group-onsemi 0:098463de4c5d 232 __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
group-onsemi 0:098463de4c5d 233 };
group-onsemi 0:098463de4c5d 234 };
group-onsemi 0:098463de4c5d 235 __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
group-onsemi 0:098463de4c5d 236 __I uint32_t RESERVED0[12];
group-onsemi 0:098463de4c5d 237 __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
group-onsemi 0:098463de4c5d 238 __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
group-onsemi 0:098463de4c5d 239 } LPC_CTxxBx_Type;
group-onsemi 0:098463de4c5d 240
group-onsemi 0:098463de4c5d 241 typedef struct { /*!< (@ 0x4000C000) CT16B0 Structure */
group-onsemi 0:098463de4c5d 242 __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
group-onsemi 0:098463de4c5d 243 __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
group-onsemi 0:098463de4c5d 244 __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
group-onsemi 0:098463de4c5d 245 __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
group-onsemi 0:098463de4c5d 246 __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
group-onsemi 0:098463de4c5d 247 __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
group-onsemi 0:098463de4c5d 248 union {
group-onsemi 0:098463de4c5d 249 __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
group-onsemi 0:098463de4c5d 250 struct{
group-onsemi 0:098463de4c5d 251 __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
group-onsemi 0:098463de4c5d 252 __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
group-onsemi 0:098463de4c5d 253 __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
group-onsemi 0:098463de4c5d 254 __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
group-onsemi 0:098463de4c5d 255 };
group-onsemi 0:098463de4c5d 256 };
group-onsemi 0:098463de4c5d 257 __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
group-onsemi 0:098463de4c5d 258 union{
group-onsemi 0:098463de4c5d 259 __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
group-onsemi 0:098463de4c5d 260 struct{
group-onsemi 0:098463de4c5d 261 __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
group-onsemi 0:098463de4c5d 262 __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
group-onsemi 0:098463de4c5d 263 __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
group-onsemi 0:098463de4c5d 264 __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
group-onsemi 0:098463de4c5d 265 };
group-onsemi 0:098463de4c5d 266 };
group-onsemi 0:098463de4c5d 267 __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
group-onsemi 0:098463de4c5d 268 __I uint32_t RESERVED0[12];
group-onsemi 0:098463de4c5d 269 __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
group-onsemi 0:098463de4c5d 270 __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
group-onsemi 0:098463de4c5d 271 } LPC_CT16B0_Type;
group-onsemi 0:098463de4c5d 272
group-onsemi 0:098463de4c5d 273
group-onsemi 0:098463de4c5d 274 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 275 // ----- CT16B1 -----
group-onsemi 0:098463de4c5d 276 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 277
group-onsemi 0:098463de4c5d 278 typedef struct { /*!< (@ 0x40010000) CT16B1 Structure */
group-onsemi 0:098463de4c5d 279 __IO uint32_t IR; /*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
group-onsemi 0:098463de4c5d 280 __IO uint32_t TCR; /*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
group-onsemi 0:098463de4c5d 281 __IO uint32_t TC; /*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
group-onsemi 0:098463de4c5d 282 __IO uint32_t PR; /*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
group-onsemi 0:098463de4c5d 283 __IO uint32_t PC; /*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
group-onsemi 0:098463de4c5d 284 __IO uint32_t MCR; /*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
group-onsemi 0:098463de4c5d 285 union {
group-onsemi 0:098463de4c5d 286 __IO uint32_t MR[4]; /*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
group-onsemi 0:098463de4c5d 287 struct{
group-onsemi 0:098463de4c5d 288 __IO uint32_t MR0; /*!< (@ 0x40010018) Match Register. MR0 */
group-onsemi 0:098463de4c5d 289 __IO uint32_t MR1; /*!< (@ 0x4001001C) Match Register. MR1 */
group-onsemi 0:098463de4c5d 290 __IO uint32_t MR2; /*!< (@ 0x40010020) Match Register. MR2 */
group-onsemi 0:098463de4c5d 291 __IO uint32_t MR3; /*!< (@ 0x40010024) Match Register. MR3 */
group-onsemi 0:098463de4c5d 292 };
group-onsemi 0:098463de4c5d 293 };
group-onsemi 0:098463de4c5d 294 __IO uint32_t CCR; /*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
group-onsemi 0:098463de4c5d 295 union{
group-onsemi 0:098463de4c5d 296 __I uint32_t CR[4]; /*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
group-onsemi 0:098463de4c5d 297 struct{
group-onsemi 0:098463de4c5d 298 __I uint32_t CR0; /*!< (@ 0x4001002C) Capture Register. CR 0 */
group-onsemi 0:098463de4c5d 299 __I uint32_t CR1; /*!< (@ 0x40010030) Capture Register. CR 1 */
group-onsemi 0:098463de4c5d 300 __I uint32_t CR2; /*!< (@ 0x40010034) Capture Register. CR 2 */
group-onsemi 0:098463de4c5d 301 __I uint32_t CR3; /*!< (@ 0x40010038) Capture Register. CR 3 */
group-onsemi 0:098463de4c5d 302 };
group-onsemi 0:098463de4c5d 303 };
group-onsemi 0:098463de4c5d 304 __IO uint32_t EMR; /*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins */
group-onsemi 0:098463de4c5d 305 __I uint32_t RESERVED0[12];
group-onsemi 0:098463de4c5d 306 __IO uint32_t CTCR; /*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
group-onsemi 0:098463de4c5d 307 __IO uint32_t PWMC; /*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
group-onsemi 0:098463de4c5d 308 } LPC_CT16B1_Type;
group-onsemi 0:098463de4c5d 309
group-onsemi 0:098463de4c5d 310
group-onsemi 0:098463de4c5d 311 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 312 // ----- CT32B0 -----
group-onsemi 0:098463de4c5d 313 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 314 typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
group-onsemi 0:098463de4c5d 315 __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
group-onsemi 0:098463de4c5d 316 __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
group-onsemi 0:098463de4c5d 317 __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
group-onsemi 0:098463de4c5d 318 __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
group-onsemi 0:098463de4c5d 319 __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
group-onsemi 0:098463de4c5d 320 __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
group-onsemi 0:098463de4c5d 321 union {
group-onsemi 0:098463de4c5d 322 __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
group-onsemi 0:098463de4c5d 323 struct{
group-onsemi 0:098463de4c5d 324 __IO uint32_t MR0; /*!< (@ 0x40014018) Match Register. MR0 */
group-onsemi 0:098463de4c5d 325 __IO uint32_t MR1; /*!< (@ 0x4001401C) Match Register. MR1 */
group-onsemi 0:098463de4c5d 326 __IO uint32_t MR2; /*!< (@ 0x40014020) Match Register. MR2 */
group-onsemi 0:098463de4c5d 327 __IO uint32_t MR3; /*!< (@ 0x40014024) Match Register. MR3 */
group-onsemi 0:098463de4c5d 328 };
group-onsemi 0:098463de4c5d 329 };
group-onsemi 0:098463de4c5d 330 __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
group-onsemi 0:098463de4c5d 331 union{
group-onsemi 0:098463de4c5d 332 __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
group-onsemi 0:098463de4c5d 333 struct{
group-onsemi 0:098463de4c5d 334 __I uint32_t CR0; /*!< (@ 0x4001402C) Capture Register. CR 0 */
group-onsemi 0:098463de4c5d 335 __I uint32_t CR1; /*!< (@ 0x40014030) Capture Register. CR 1 */
group-onsemi 0:098463de4c5d 336 __I uint32_t CR2; /*!< (@ 0x40014034) Capture Register. CR 2 */
group-onsemi 0:098463de4c5d 337 __I uint32_t CR3; /*!< (@ 0x40014038) Capture Register. CR 3 */
group-onsemi 0:098463de4c5d 338 };
group-onsemi 0:098463de4c5d 339 };
group-onsemi 0:098463de4c5d 340 __IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
group-onsemi 0:098463de4c5d 341 __I uint32_t RESERVED0[12];
group-onsemi 0:098463de4c5d 342 __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
group-onsemi 0:098463de4c5d 343 __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
group-onsemi 0:098463de4c5d 344 } LPC_CT32B0_Type;
group-onsemi 0:098463de4c5d 345
group-onsemi 0:098463de4c5d 346
group-onsemi 0:098463de4c5d 347 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 348 // ----- CT32B1 -----
group-onsemi 0:098463de4c5d 349 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 350 typedef struct { /*!< (@ 0x40018000) CT32B1 Structure */
group-onsemi 0:098463de4c5d 351 __IO uint32_t IR; /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
group-onsemi 0:098463de4c5d 352 __IO uint32_t TCR; /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
group-onsemi 0:098463de4c5d 353 __IO uint32_t TC; /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
group-onsemi 0:098463de4c5d 354 __IO uint32_t PR; /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
group-onsemi 0:098463de4c5d 355 __IO uint32_t PC; /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
group-onsemi 0:098463de4c5d 356 __IO uint32_t MCR; /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
group-onsemi 0:098463de4c5d 357 union {
group-onsemi 0:098463de4c5d 358 __IO uint32_t MR[4]; /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
group-onsemi 0:098463de4c5d 359 struct{
group-onsemi 0:098463de4c5d 360 __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
group-onsemi 0:098463de4c5d 361 __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
group-onsemi 0:098463de4c5d 362 __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
group-onsemi 0:098463de4c5d 363 __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
group-onsemi 0:098463de4c5d 364 };
group-onsemi 0:098463de4c5d 365 };
group-onsemi 0:098463de4c5d 366 __IO uint32_t CCR; /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
group-onsemi 0:098463de4c5d 367 union{
group-onsemi 0:098463de4c5d 368 __I uint32_t CR[4]; /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
group-onsemi 0:098463de4c5d 369 struct{
group-onsemi 0:098463de4c5d 370 __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
group-onsemi 0:098463de4c5d 371 __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
group-onsemi 0:098463de4c5d 372 __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
group-onsemi 0:098463de4c5d 373 __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
group-onsemi 0:098463de4c5d 374 };
group-onsemi 0:098463de4c5d 375 };
group-onsemi 0:098463de4c5d 376 __IO uint32_t EMR; /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
group-onsemi 0:098463de4c5d 377 __I uint32_t RESERVED0[12];
group-onsemi 0:098463de4c5d 378 __IO uint32_t CTCR; /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
group-onsemi 0:098463de4c5d 379 __IO uint32_t PWMC; /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
group-onsemi 0:098463de4c5d 380 } LPC_CT32B1_Type;
group-onsemi 0:098463de4c5d 381
group-onsemi 0:098463de4c5d 382
group-onsemi 0:098463de4c5d 383 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 384 // ----- ADC -----
group-onsemi 0:098463de4c5d 385 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 386 typedef struct { /*!< (@ 0x4001C000) ADC Structure */
group-onsemi 0:098463de4c5d 387 __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
group-onsemi 0:098463de4c5d 388 __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
group-onsemi 0:098463de4c5d 389 __I uint32_t RESERVED0[1];
group-onsemi 0:098463de4c5d 390 __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
group-onsemi 0:098463de4c5d 391 union{
group-onsemi 0:098463de4c5d 392 __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
group-onsemi 0:098463de4c5d 393 struct{
group-onsemi 0:098463de4c5d 394 __I uint32_t DR0; /*!< (@ 0x4001C010) A/D Channel Data Register 0*/
group-onsemi 0:098463de4c5d 395 __I uint32_t DR1; /*!< (@ 0x4001C014) A/D Channel Data Register 1*/
group-onsemi 0:098463de4c5d 396 __I uint32_t DR2; /*!< (@ 0x4001C018) A/D Channel Data Register 2*/
group-onsemi 0:098463de4c5d 397 __I uint32_t DR3; /*!< (@ 0x4001C01C) A/D Channel Data Register 3*/
group-onsemi 0:098463de4c5d 398 __I uint32_t DR4; /*!< (@ 0x4001C020) A/D Channel Data Register 4*/
group-onsemi 0:098463de4c5d 399 __I uint32_t DR5; /*!< (@ 0x4001C024) A/D Channel Data Register 5*/
group-onsemi 0:098463de4c5d 400 __I uint32_t DR6; /*!< (@ 0x4001C028) A/D Channel Data Register 6*/
group-onsemi 0:098463de4c5d 401 __I uint32_t DR7; /*!< (@ 0x4001C02C) A/D Channel Data Register 7*/
group-onsemi 0:098463de4c5d 402 };
group-onsemi 0:098463de4c5d 403 };
group-onsemi 0:098463de4c5d 404 __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
group-onsemi 0:098463de4c5d 405 } LPC_ADC_Type;
group-onsemi 0:098463de4c5d 406
group-onsemi 0:098463de4c5d 407
group-onsemi 0:098463de4c5d 408 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 409 // ----- PMU -----
group-onsemi 0:098463de4c5d 410 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 411
group-onsemi 0:098463de4c5d 412 typedef struct { /*!< (@ 0x40038000) PMU Structure */
group-onsemi 0:098463de4c5d 413 __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
group-onsemi 0:098463de4c5d 414 union{
group-onsemi 0:098463de4c5d 415 __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
group-onsemi 0:098463de4c5d 416 struct{
group-onsemi 0:098463de4c5d 417 __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
group-onsemi 0:098463de4c5d 418 __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
group-onsemi 0:098463de4c5d 419 __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
group-onsemi 0:098463de4c5d 420 __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
group-onsemi 0:098463de4c5d 421 };
group-onsemi 0:098463de4c5d 422 };
group-onsemi 0:098463de4c5d 423 __IO uint32_t GPREG4; /*!< (@ 0x40038014) General purpose register 4 */
group-onsemi 0:098463de4c5d 424 } LPC_PMU_Type;
group-onsemi 0:098463de4c5d 425
group-onsemi 0:098463de4c5d 426
group-onsemi 0:098463de4c5d 427 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 428 // ----- FLASHCTRL -----
group-onsemi 0:098463de4c5d 429 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 430
group-onsemi 0:098463de4c5d 431 typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
group-onsemi 0:098463de4c5d 432 __I uint32_t RESERVED0[4];
group-onsemi 0:098463de4c5d 433 __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
group-onsemi 0:098463de4c5d 434 __I uint32_t RESERVED1[3];
group-onsemi 0:098463de4c5d 435 __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
group-onsemi 0:098463de4c5d 436 __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
group-onsemi 0:098463de4c5d 437 __I uint32_t RESERVED2[1];
group-onsemi 0:098463de4c5d 438 __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
group-onsemi 0:098463de4c5d 439 __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
group-onsemi 0:098463de4c5d 440 __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
group-onsemi 0:098463de4c5d 441 __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
group-onsemi 0:098463de4c5d 442 __I uint32_t RESERVED3[1001];
group-onsemi 0:098463de4c5d 443 __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
group-onsemi 0:098463de4c5d 444 __I uint32_t RESERVED4[1];
group-onsemi 0:098463de4c5d 445 __O uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
group-onsemi 0:098463de4c5d 446 } LPC_FLASHCTRL_Type;
group-onsemi 0:098463de4c5d 447
group-onsemi 0:098463de4c5d 448
group-onsemi 0:098463de4c5d 449 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 450 // ----- SSP -----
group-onsemi 0:098463de4c5d 451 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 452 typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
group-onsemi 0:098463de4c5d 453 __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
group-onsemi 0:098463de4c5d 454 __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
group-onsemi 0:098463de4c5d 455 __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
group-onsemi 0:098463de4c5d 456 __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
group-onsemi 0:098463de4c5d 457 __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
group-onsemi 0:098463de4c5d 458 __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
group-onsemi 0:098463de4c5d 459 __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
group-onsemi 0:098463de4c5d 460 __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
group-onsemi 0:098463de4c5d 461 __O uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
group-onsemi 0:098463de4c5d 462 } LPC_SSPx_Type;
group-onsemi 0:098463de4c5d 463
group-onsemi 0:098463de4c5d 464
group-onsemi 0:098463de4c5d 465 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 466 // ----- IOCON -----
group-onsemi 0:098463de4c5d 467 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 468 typedef struct { /*!< (@ 0x40044000) IOCON Structure */
group-onsemi 0:098463de4c5d 469 __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
group-onsemi 0:098463de4c5d 470 __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
group-onsemi 0:098463de4c5d 471 __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
group-onsemi 0:098463de4c5d 472 __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
group-onsemi 0:098463de4c5d 473 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
group-onsemi 0:098463de4c5d 474 __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
group-onsemi 0:098463de4c5d 475 __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
group-onsemi 0:098463de4c5d 476 __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
group-onsemi 0:098463de4c5d 477 __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/SWO */
group-onsemi 0:098463de4c5d 478 __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/TRACECLK */
group-onsemi 0:098463de4c5d 479 __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
group-onsemi 0:098463de4c5d 480 __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
group-onsemi 0:098463de4c5d 481 __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
group-onsemi 0:098463de4c5d 482 __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
group-onsemi 0:098463de4c5d 483 __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
group-onsemi 0:098463de4c5d 484 __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
group-onsemi 0:098463de4c5d 485 __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
group-onsemi 0:098463de4c5d 486 __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
group-onsemi 0:098463de4c5d 487 __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
group-onsemi 0:098463de4c5d 488 __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
group-onsemi 0:098463de4c5d 489 __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
group-onsemi 0:098463de4c5d 490 __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
group-onsemi 0:098463de4c5d 491 __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
group-onsemi 0:098463de4c5d 492 __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
group-onsemi 0:098463de4c5d 493 __IO uint32_t PIO1_0; /*!< (@ 0x40044060) I/O configuration for pin PIO1_0/CT32B1_MAT0 */
group-onsemi 0:098463de4c5d 494 __IO uint32_t PIO1_1; /*!< (@ 0x40044064) I/O configuration for pin PIO1_1/CT32B1_MAT1 */
group-onsemi 0:098463de4c5d 495 __IO uint32_t PIO1_2; /*!< (@ 0x40044068) I/O configuration for pin PIO1_2/CT32B1_MAT2 */
group-onsemi 0:098463de4c5d 496 __IO uint32_t PIO1_3; /*!< (@ 0x4004406C) I/O configuration for pin PIO1_3/CT32B1_MAT3 */
group-onsemi 0:098463de4c5d 497 __IO uint32_t PIO1_4; /*!< (@ 0x40044070) I/O configuration for pin PIO1_4/CT32B1_CAP0 */
group-onsemi 0:098463de4c5d 498 __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
group-onsemi 0:098463de4c5d 499 __IO uint32_t PIO1_6; /*!< (@ 0x40044078) I/O configuration for pin PIO1_6 */
group-onsemi 0:098463de4c5d 500 __IO uint32_t PIO1_7; /*!< (@ 0x4004407C) I/O configuration for pin PIO1_7 */
group-onsemi 0:098463de4c5d 501 __IO uint32_t PIO1_8; /*!< (@ 0x40044080) I/O configuration for pin PIO1_8 */
group-onsemi 0:098463de4c5d 502 __IO uint32_t PIO1_9; /*!< (@ 0x40044084) I/O configuration for pin PIO1_9 */
group-onsemi 0:098463de4c5d 503 __IO uint32_t PIO1_10; /*!< (@ 0x40044088) I/O configuration for pin PIO1_10 */
group-onsemi 0:098463de4c5d 504 __IO uint32_t PIO1_11; /*!< (@ 0x4004408C) I/O configuration for pin PIO1_11 */
group-onsemi 0:098463de4c5d 505 __IO uint32_t PIO1_12; /*!< (@ 0x40044090) I/O configuration for pin PIO1_12 */
group-onsemi 0:098463de4c5d 506 __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD */
group-onsemi 0:098463de4c5d 507 __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD */
group-onsemi 0:098463de4c5d 508 __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
group-onsemi 0:098463de4c5d 509 __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
group-onsemi 0:098463de4c5d 510 __IO uint32_t PIO1_17; /*!< (@ 0x400440A4) I/O configuration for PIO1_17/CT16B0_CAP1/RXD */
group-onsemi 0:098463de4c5d 511 __IO uint32_t PIO1_18; /*!< (@ 0x400440A8) I/O configuration for PIO1_18/CT16B1_CAP1/TXD */
group-onsemi 0:098463de4c5d 512 __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
group-onsemi 0:098463de4c5d 513 __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
group-onsemi 0:098463de4c5d 514 __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
group-onsemi 0:098463de4c5d 515 __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
group-onsemi 0:098463de4c5d 516 __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
group-onsemi 0:098463de4c5d 517 __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
group-onsemi 0:098463de4c5d 518 __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
group-onsemi 0:098463de4c5d 519 __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
group-onsemi 0:098463de4c5d 520 __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
group-onsemi 0:098463de4c5d 521 __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
group-onsemi 0:098463de4c5d 522 __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
group-onsemi 0:098463de4c5d 523 __IO uint32_t PIO1_30; /*!< (@ 0x400440D8) I/O configuration for pin PIO1_30 */
group-onsemi 0:098463de4c5d 524 __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
group-onsemi 0:098463de4c5d 525 } LPC_IOCON_Type;
group-onsemi 0:098463de4c5d 526
group-onsemi 0:098463de4c5d 527
group-onsemi 0:098463de4c5d 528 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 529 // ----- SYSCON -----
group-onsemi 0:098463de4c5d 530 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 531
group-onsemi 0:098463de4c5d 532 typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
group-onsemi 0:098463de4c5d 533 __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
group-onsemi 0:098463de4c5d 534 __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
group-onsemi 0:098463de4c5d 535 __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
group-onsemi 0:098463de4c5d 536 __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
group-onsemi 0:098463de4c5d 537 __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
group-onsemi 0:098463de4c5d 538 __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
group-onsemi 0:098463de4c5d 539 __I uint32_t RESERVED0[2];
group-onsemi 0:098463de4c5d 540 __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
group-onsemi 0:098463de4c5d 541 __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
group-onsemi 0:098463de4c5d 542 __I uint32_t RESERVED1[2];
group-onsemi 0:098463de4c5d 543 __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
group-onsemi 0:098463de4c5d 544 __I uint32_t RESERVED2[3];
group-onsemi 0:098463de4c5d 545 __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
group-onsemi 0:098463de4c5d 546 __I uint32_t RESERVED3;
group-onsemi 0:098463de4c5d 547 __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
group-onsemi 0:098463de4c5d 548 __I uint32_t RESERVED4[9];
group-onsemi 0:098463de4c5d 549 __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
group-onsemi 0:098463de4c5d 550 __I uint32_t RESERVED5;
group-onsemi 0:098463de4c5d 551 __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
group-onsemi 0:098463de4c5d 552 __I uint32_t RESERVED6;
group-onsemi 0:098463de4c5d 553 __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
group-onsemi 0:098463de4c5d 554 __I uint32_t RESERVED7[4];
group-onsemi 0:098463de4c5d 555 __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
group-onsemi 0:098463de4c5d 556 __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
group-onsemi 0:098463de4c5d 557 __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
group-onsemi 0:098463de4c5d 558 __I uint32_t RESERVED8[3];
group-onsemi 0:098463de4c5d 559 __IO uint32_t TRACECLKDIV; /*!< (@ 0x400480AC) ARM trace clock divider */
group-onsemi 0:098463de4c5d 560 __IO uint32_t SYSTICKCLKDIV; /*!< (@ 0x400480B0) SYSTICK clock divder */
group-onsemi 0:098463de4c5d 561 __I uint32_t RESERVED9[3];
group-onsemi 0:098463de4c5d 562 __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
group-onsemi 0:098463de4c5d 563 __I uint32_t RESERVED10;
group-onsemi 0:098463de4c5d 564 __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
group-onsemi 0:098463de4c5d 565 __I uint32_t RESERVED11[5];
group-onsemi 0:098463de4c5d 566 __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
group-onsemi 0:098463de4c5d 567 __I uint32_t RESERVED12;
group-onsemi 0:098463de4c5d 568 __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
group-onsemi 0:098463de4c5d 569 __I uint32_t RESERVED13[5];
group-onsemi 0:098463de4c5d 570 __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
group-onsemi 0:098463de4c5d 571 __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
group-onsemi 0:098463de4c5d 572 __I uint32_t RESERVED14[18];
group-onsemi 0:098463de4c5d 573 __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
group-onsemi 0:098463de4c5d 574 __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
group-onsemi 0:098463de4c5d 575 __I uint32_t RESERVED15[6];
group-onsemi 0:098463de4c5d 576 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */
group-onsemi 0:098463de4c5d 577 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
group-onsemi 0:098463de4c5d 578 __IO uint32_t PINSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register */
group-onsemi 0:098463de4c5d 579 __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
group-onsemi 0:098463de4c5d 580 __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
group-onsemi 0:098463de4c5d 581 __I uint32_t RESERVED16[25];
group-onsemi 0:098463de4c5d 582 __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
group-onsemi 0:098463de4c5d 583 __I uint32_t RESERVED17[3];
group-onsemi 0:098463de4c5d 584 __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
group-onsemi 0:098463de4c5d 585 __I uint32_t RESERVED18[6];
group-onsemi 0:098463de4c5d 586 __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
group-onsemi 0:098463de4c5d 587 __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
group-onsemi 0:098463de4c5d 588 __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
group-onsemi 0:098463de4c5d 589 __I uint32_t RESERVED19[111];
group-onsemi 0:098463de4c5d 590 __I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
group-onsemi 0:098463de4c5d 591 } LPC_SYSCON_Type;
group-onsemi 0:098463de4c5d 592
group-onsemi 0:098463de4c5d 593
group-onsemi 0:098463de4c5d 594 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 595 // ----- GPIO_PIN_INT -----
group-onsemi 0:098463de4c5d 596 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 597 typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
group-onsemi 0:098463de4c5d 598 __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
group-onsemi 0:098463de4c5d 599 __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
group-onsemi 0:098463de4c5d 600 __O uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
group-onsemi 0:098463de4c5d 601 __O uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
group-onsemi 0:098463de4c5d 602 __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
group-onsemi 0:098463de4c5d 603 __O uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
group-onsemi 0:098463de4c5d 604 __O uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
group-onsemi 0:098463de4c5d 605 __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
group-onsemi 0:098463de4c5d 606 __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
group-onsemi 0:098463de4c5d 607 __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
group-onsemi 0:098463de4c5d 608 } LPC_GPIO_PIN_INT_Type;
group-onsemi 0:098463de4c5d 609
group-onsemi 0:098463de4c5d 610
group-onsemi 0:098463de4c5d 611 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 612 // ----- GPIO_GROUP_INT0 -----
group-onsemi 0:098463de4c5d 613 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 614 typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
group-onsemi 0:098463de4c5d 615 __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
group-onsemi 0:098463de4c5d 616 __I uint32_t RESERVED0[7];
group-onsemi 0:098463de4c5d 617 __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
group-onsemi 0:098463de4c5d 618 __I uint32_t RESERVED1[6];
group-onsemi 0:098463de4c5d 619 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
group-onsemi 0:098463de4c5d 620 } LPC_GPIO_GROUP_INT0_Type;
group-onsemi 0:098463de4c5d 621
group-onsemi 0:098463de4c5d 622
group-onsemi 0:098463de4c5d 623 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 624 // ----- GPIO_GROUP_INT1 -----
group-onsemi 0:098463de4c5d 625 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 626
group-onsemi 0:098463de4c5d 627 typedef struct { /*!< (@ 0x40060000) GPIO_GROUP_INT1 Structure */
group-onsemi 0:098463de4c5d 628 __IO uint32_t CTRL; /*!< (@ 0x40060000) GPIO grouped interrupt control register */
group-onsemi 0:098463de4c5d 629 __I uint32_t RESERVED0[7];
group-onsemi 0:098463de4c5d 630 __IO uint32_t PORT_POL[2]; /*!< (@ 0x40060020) GPIO grouped interrupt port 0 polarity register */
group-onsemi 0:098463de4c5d 631 __I uint32_t RESERVED1[6];
group-onsemi 0:098463de4c5d 632 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x40060040) GPIO grouped interrupt port 0/1 enable register */
group-onsemi 0:098463de4c5d 633 } LPC_GPIO_GROUP_INT1_Type;
group-onsemi 0:098463de4c5d 634
group-onsemi 0:098463de4c5d 635
group-onsemi 0:098463de4c5d 636 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 637 // ----- Repetitive Interrupt Timer (RIT) -----
group-onsemi 0:098463de4c5d 638 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 639
group-onsemi 0:098463de4c5d 640 typedef struct { /*!< (@ 0x40064000) RITIMER Structure */
group-onsemi 0:098463de4c5d 641 __IO uint32_t COMPVAL; /*!< (@ 0x40064000) RITIMER compare register */
group-onsemi 0:098463de4c5d 642 __IO uint32_t MASK; /*!< (@ 0x40064004) RITIMER mask register */
group-onsemi 0:098463de4c5d 643 __IO uint32_t CTRL; /*!< (@ 0x40064008) RITIMER control register */
group-onsemi 0:098463de4c5d 644 __IO uint32_t COUNTER; /*!< (@ 0x4006400C) RITIMER counter register */
group-onsemi 0:098463de4c5d 645 __IO uint32_t COMPVAL_H; /*!< (@ 0x40064010) RITIMER compare upper register */
group-onsemi 0:098463de4c5d 646 __IO uint32_t MASK_H; /*!< (@ 0x40064014) RITIMER mask upper register */
group-onsemi 0:098463de4c5d 647 __I uint32_t RESERVED0[1];
group-onsemi 0:098463de4c5d 648 __IO uint32_t COUNTER_H; /*!< (@ 0x4006401C) RITIMER counter upper register */
group-onsemi 0:098463de4c5d 649 } LPC_RITIMER_Type;
group-onsemi 0:098463de4c5d 650
group-onsemi 0:098463de4c5d 651
group-onsemi 0:098463de4c5d 652 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 653 // ----- USB -----
group-onsemi 0:098463de4c5d 654 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 655 typedef struct { /*!< (@ 0x40020000) USB Structure */
group-onsemi 0:098463de4c5d 656 __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40020000) USB Device Command/Status register */
group-onsemi 0:098463de4c5d 657 __IO uint32_t INFO; /*!< (@ 0x40020004) USB Info register */
group-onsemi 0:098463de4c5d 658 __IO uint32_t EPLISTSTART; /*!< (@ 0x40020008) USB EP Command/Status List start address */
group-onsemi 0:098463de4c5d 659 __IO uint32_t DATABUFSTART; /*!< (@ 0x4002000C) USB Data buffer start address */
group-onsemi 0:098463de4c5d 660 __IO uint32_t LPM; /*!< (@ 0x40020010) Link Power Management register */
group-onsemi 0:098463de4c5d 661 __IO uint32_t EPSKIP; /*!< (@ 0x40020014) USB Endpoint skip */
group-onsemi 0:098463de4c5d 662 __IO uint32_t EPINUSE; /*!< (@ 0x40020018) USB Endpoint Buffer in use */
group-onsemi 0:098463de4c5d 663 __IO uint32_t EPBUFCFG; /*!< (@ 0x4002001C) USB Endpoint Buffer Configuration register */
group-onsemi 0:098463de4c5d 664 __IO uint32_t INTSTAT; /*!< (@ 0x40020020) USB interrupt status register */
group-onsemi 0:098463de4c5d 665 __IO uint32_t INTEN; /*!< (@ 0x40020024) USB interrupt enable register */
group-onsemi 0:098463de4c5d 666 __IO uint32_t INTSETSTAT; /*!< (@ 0x40020028) USB set interrupt status register */
group-onsemi 0:098463de4c5d 667 __IO uint32_t INTROUTING; /*!< (@ 0x4002002C) USB interrupt routing register */
group-onsemi 0:098463de4c5d 668 __I uint32_t RESERVED0[1];
group-onsemi 0:098463de4c5d 669 __I uint32_t EPTOGGLE; /*!< (@ 0x40020034) USB Endpoint toggle register */
group-onsemi 0:098463de4c5d 670 } LPC_USB_Type;
group-onsemi 0:098463de4c5d 671
group-onsemi 0:098463de4c5d 672
group-onsemi 0:098463de4c5d 673 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 674 // ----- GPIO_PORT -----
group-onsemi 0:098463de4c5d 675 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 676
group-onsemi 0:098463de4c5d 677 typedef struct { /*!< (@ 0x50000000) GPIO_PORT Structure */
group-onsemi 0:098463de4c5d 678 union {
group-onsemi 0:098463de4c5d 679 struct {
group-onsemi 0:098463de4c5d 680 __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
group-onsemi 0:098463de4c5d 681 __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
group-onsemi 0:098463de4c5d 682 };
group-onsemi 0:098463de4c5d 683 __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
group-onsemi 0:098463de4c5d 684 };
group-onsemi 0:098463de4c5d 685 __I uint32_t RESERVED0[1008];
group-onsemi 0:098463de4c5d 686 union {
group-onsemi 0:098463de4c5d 687 struct {
group-onsemi 0:098463de4c5d 688 __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
group-onsemi 0:098463de4c5d 689 __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
group-onsemi 0:098463de4c5d 690 };
group-onsemi 0:098463de4c5d 691 __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
group-onsemi 0:098463de4c5d 692 };
group-onsemi 0:098463de4c5d 693 __I uint32_t RESERVED1[960];
group-onsemi 0:098463de4c5d 694 __IO uint32_t DIR[2]; /*!< (@ 0x50002000) Direction registers port 0/1 */
group-onsemi 0:098463de4c5d 695 __I uint32_t RESERVED2[30];
group-onsemi 0:098463de4c5d 696 __IO uint32_t MASK[2]; /*!< (@ 0x50002080) Mask register port 0/1 */
group-onsemi 0:098463de4c5d 697 __I uint32_t RESERVED3[30];
group-onsemi 0:098463de4c5d 698 __IO uint32_t PIN[2]; /*!< (@ 0x50002100) Portpin register port 0 */
group-onsemi 0:098463de4c5d 699 __I uint32_t RESERVED4[30];
group-onsemi 0:098463de4c5d 700 __IO uint32_t MPIN[2]; /*!< (@ 0x50002180) Masked port register port 0/1 */
group-onsemi 0:098463de4c5d 701 __I uint32_t RESERVED5[30];
group-onsemi 0:098463de4c5d 702 __IO uint32_t SET[2]; /*!< (@ 0x50002200) Write: Set register for port 0/1 Read: output bits for port 0/1 */
group-onsemi 0:098463de4c5d 703 __I uint32_t RESERVED6[30];
group-onsemi 0:098463de4c5d 704 __O uint32_t CLR[2]; /*!< (@ 0x50002280) Clear port 0/1 */
group-onsemi 0:098463de4c5d 705 __I uint32_t RESERVED7[30];
group-onsemi 0:098463de4c5d 706 __O uint32_t NOT[2]; /*!< (@ 0x50002300) Toggle port 0/1 */
group-onsemi 0:098463de4c5d 707 } LPC_GPIO_Type;
group-onsemi 0:098463de4c5d 708
group-onsemi 0:098463de4c5d 709
group-onsemi 0:098463de4c5d 710 #if defined ( __CC_ARM )
group-onsemi 0:098463de4c5d 711 #pragma no_anon_unions
group-onsemi 0:098463de4c5d 712 #endif
group-onsemi 0:098463de4c5d 713
group-onsemi 0:098463de4c5d 714
group-onsemi 0:098463de4c5d 715 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 716 // ----- Peripheral memory map -----
group-onsemi 0:098463de4c5d 717 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 718
group-onsemi 0:098463de4c5d 719 #define LPC_I2C_BASE (0x40000000)
group-onsemi 0:098463de4c5d 720 #define LPC_WWDT_BASE (0x40004000)
group-onsemi 0:098463de4c5d 721 #define LPC_USART_BASE (0x40008000)
group-onsemi 0:098463de4c5d 722 #define LPC_CT16B0_BASE (0x4000C000)
group-onsemi 0:098463de4c5d 723 #define LPC_CT16B1_BASE (0x40010000)
group-onsemi 0:098463de4c5d 724 #define LPC_CT32B0_BASE (0x40014000)
group-onsemi 0:098463de4c5d 725 #define LPC_CT32B1_BASE (0x40018000)
group-onsemi 0:098463de4c5d 726 #define LPC_ADC_BASE (0x4001C000)
group-onsemi 0:098463de4c5d 727 #define LPC_PMU_BASE (0x40038000)
group-onsemi 0:098463de4c5d 728 #define LPC_FLASHCTRL_BASE (0x4003C000)
group-onsemi 0:098463de4c5d 729 #define LPC_SSP0_BASE (0x40040000)
group-onsemi 0:098463de4c5d 730 #define LPC_IOCON_BASE (0x40044000)
group-onsemi 0:098463de4c5d 731 #define LPC_SYSCON_BASE (0x40048000)
group-onsemi 0:098463de4c5d 732 #define LPC_GPIO_PIN_INT_BASE (0x4004C000)
group-onsemi 0:098463de4c5d 733 #define LPC_SSP1_BASE (0x40058000)
group-onsemi 0:098463de4c5d 734 #define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
group-onsemi 0:098463de4c5d 735 #define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
group-onsemi 0:098463de4c5d 736 #define LPC_RITIMER_BASE (0x40064000)
group-onsemi 0:098463de4c5d 737 #define LPC_USB_BASE (0x40080000)
group-onsemi 0:098463de4c5d 738 #define LPC_GPIO_BASE (0x50000000)
group-onsemi 0:098463de4c5d 739
group-onsemi 0:098463de4c5d 740
group-onsemi 0:098463de4c5d 741 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 742 // ----- Peripheral declaration -----
group-onsemi 0:098463de4c5d 743 // ------------------------------------------------------------------------------------------------
group-onsemi 0:098463de4c5d 744
group-onsemi 0:098463de4c5d 745 #define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
group-onsemi 0:098463de4c5d 746 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
group-onsemi 0:098463de4c5d 747 #define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
group-onsemi 0:098463de4c5d 748 #define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
group-onsemi 0:098463de4c5d 749 #define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
group-onsemi 0:098463de4c5d 750 #define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
group-onsemi 0:098463de4c5d 751 #define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
group-onsemi 0:098463de4c5d 752 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
group-onsemi 0:098463de4c5d 753 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
group-onsemi 0:098463de4c5d 754 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
group-onsemi 0:098463de4c5d 755 #define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
group-onsemi 0:098463de4c5d 756 #define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
group-onsemi 0:098463de4c5d 757 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
group-onsemi 0:098463de4c5d 758 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
group-onsemi 0:098463de4c5d 759 #define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
group-onsemi 0:098463de4c5d 760 #define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INT0_Type*) LPC_GPIO_GROUP_INT0_BASE)
group-onsemi 0:098463de4c5d 761 #define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INT1_Type*) LPC_GPIO_GROUP_INT1_BASE)
group-onsemi 0:098463de4c5d 762 #define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE)
group-onsemi 0:098463de4c5d 763 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
group-onsemi 0:098463de4c5d 764 #define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
group-onsemi 0:098463de4c5d 765
group-onsemi 0:098463de4c5d 766
group-onsemi 0:098463de4c5d 767 /** @} */ /* End of group Device_Peripheral_Registers */
group-onsemi 0:098463de4c5d 768 /** @} */ /* End of group (null) */
group-onsemi 0:098463de4c5d 769 /** @} */ /* End of group h1usf */
group-onsemi 0:098463de4c5d 770
group-onsemi 0:098463de4c5d 771 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 772 }
group-onsemi 0:098463de4c5d 773 #endif
group-onsemi 0:098463de4c5d 774
group-onsemi 0:098463de4c5d 775
group-onsemi 0:098463de4c5d 776 #endif // __LPC13UXX_H__