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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NXP/TARGET_LPC11UXX/gpio_irq_api.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2006-2013 ARM Limited
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 #include <stddef.h>
group-onsemi 0:098463de4c5d 17 #include "cmsis.h"
group-onsemi 0:098463de4c5d 18 #include "gpio_irq_api.h"
group-onsemi 0:098463de4c5d 19 #include "mbed_error.h"
group-onsemi 0:098463de4c5d 20
group-onsemi 0:098463de4c5d 21 #define CHANNEL_NUM 8
group-onsemi 0:098463de4c5d 22 #define LPC_GPIO_X LPC_GPIO_PIN_INT
group-onsemi 0:098463de4c5d 23 #define PININT_IRQ 0
group-onsemi 0:098463de4c5d 24
group-onsemi 0:098463de4c5d 25 static uint32_t channel_ids[CHANNEL_NUM] = {0};
group-onsemi 0:098463de4c5d 26 static gpio_irq_handler irq_handler;
group-onsemi 0:098463de4c5d 27
group-onsemi 0:098463de4c5d 28 static inline void handle_interrupt_in(uint32_t channel) {
group-onsemi 0:098463de4c5d 29 uint32_t ch_bit = (1 << channel);
group-onsemi 0:098463de4c5d 30 // Return immediately if:
group-onsemi 0:098463de4c5d 31 // * The interrupt was already served
group-onsemi 0:098463de4c5d 32 // * There is no user handler
group-onsemi 0:098463de4c5d 33 // * It is a level interrupt, not an edge interrupt
group-onsemi 0:098463de4c5d 34 if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
group-onsemi 0:098463de4c5d 35 (channel_ids[channel] == 0 ) ||
group-onsemi 0:098463de4c5d 36 (LPC_GPIO_X->ISEL & ch_bit ) ) return;
group-onsemi 0:098463de4c5d 37
group-onsemi 0:098463de4c5d 38 if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
group-onsemi 0:098463de4c5d 39 irq_handler(channel_ids[channel], IRQ_RISE);
group-onsemi 0:098463de4c5d 40 LPC_GPIO_X->RISE = ch_bit;
group-onsemi 0:098463de4c5d 41 }
group-onsemi 0:098463de4c5d 42 if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
group-onsemi 0:098463de4c5d 43 irq_handler(channel_ids[channel], IRQ_FALL);
group-onsemi 0:098463de4c5d 44 }
group-onsemi 0:098463de4c5d 45 LPC_GPIO_X->IST = ch_bit;
group-onsemi 0:098463de4c5d 46 }
group-onsemi 0:098463de4c5d 47
group-onsemi 0:098463de4c5d 48 void gpio_irq0(void) {handle_interrupt_in(0);}
group-onsemi 0:098463de4c5d 49 void gpio_irq1(void) {handle_interrupt_in(1);}
group-onsemi 0:098463de4c5d 50 void gpio_irq2(void) {handle_interrupt_in(2);}
group-onsemi 0:098463de4c5d 51 void gpio_irq3(void) {handle_interrupt_in(3);}
group-onsemi 0:098463de4c5d 52 void gpio_irq4(void) {handle_interrupt_in(4);}
group-onsemi 0:098463de4c5d 53 void gpio_irq5(void) {handle_interrupt_in(5);}
group-onsemi 0:098463de4c5d 54 void gpio_irq6(void) {handle_interrupt_in(6);}
group-onsemi 0:098463de4c5d 55 void gpio_irq7(void) {handle_interrupt_in(7);}
group-onsemi 0:098463de4c5d 56
group-onsemi 0:098463de4c5d 57 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
group-onsemi 0:098463de4c5d 58 if (pin == NC) return -1;
group-onsemi 0:098463de4c5d 59
group-onsemi 0:098463de4c5d 60 irq_handler = handler;
group-onsemi 0:098463de4c5d 61
group-onsemi 0:098463de4c5d 62 int found_free_channel = 0;
group-onsemi 0:098463de4c5d 63 int i = 0;
group-onsemi 0:098463de4c5d 64 for (i=0; i<CHANNEL_NUM; i++) {
group-onsemi 0:098463de4c5d 65 if (channel_ids[i] == 0) {
group-onsemi 0:098463de4c5d 66 channel_ids[i] = id;
group-onsemi 0:098463de4c5d 67 obj->ch = i;
group-onsemi 0:098463de4c5d 68 found_free_channel = 1;
group-onsemi 0:098463de4c5d 69 break;
group-onsemi 0:098463de4c5d 70 }
group-onsemi 0:098463de4c5d 71 }
group-onsemi 0:098463de4c5d 72 if (!found_free_channel) return -1;
group-onsemi 0:098463de4c5d 73
group-onsemi 0:098463de4c5d 74 /* Enable AHB clock to the GPIO domain. */
group-onsemi 0:098463de4c5d 75 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
group-onsemi 0:098463de4c5d 76
group-onsemi 0:098463de4c5d 77 /* Enable AHB clock to the FlexInt, GroupedInt domain. */
group-onsemi 0:098463de4c5d 78 LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24));
group-onsemi 0:098463de4c5d 79
group-onsemi 0:098463de4c5d 80 /* To select a pin for any of the eight pin interrupts, write the pin number
group-onsemi 0:098463de4c5d 81 * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
group-onsemi 0:098463de4c5d 82 * @see: mbed_capi/PinNames.h
group-onsemi 0:098463de4c5d 83 */
group-onsemi 0:098463de4c5d 84 LPC_SYSCON->PINTSEL[obj->ch] = (pin >> 5) ? (pin - 8) : (pin);
group-onsemi 0:098463de4c5d 85
group-onsemi 0:098463de4c5d 86 // Interrupt Wake-Up Enable
group-onsemi 0:098463de4c5d 87 LPC_SYSCON->STARTERP0 |= 1 << obj->ch;
group-onsemi 0:098463de4c5d 88
group-onsemi 0:098463de4c5d 89 void (*channels_irq)(void) = NULL;
group-onsemi 0:098463de4c5d 90 switch (obj->ch) {
group-onsemi 0:098463de4c5d 91 case 0: channels_irq = &gpio_irq0; break;
group-onsemi 0:098463de4c5d 92 case 1: channels_irq = &gpio_irq1; break;
group-onsemi 0:098463de4c5d 93 case 2: channels_irq = &gpio_irq2; break;
group-onsemi 0:098463de4c5d 94 case 3: channels_irq = &gpio_irq3; break;
group-onsemi 0:098463de4c5d 95 case 4: channels_irq = &gpio_irq4; break;
group-onsemi 0:098463de4c5d 96 case 5: channels_irq = &gpio_irq5; break;
group-onsemi 0:098463de4c5d 97 case 6: channels_irq = &gpio_irq6; break;
group-onsemi 0:098463de4c5d 98 case 7: channels_irq = &gpio_irq7; break;
group-onsemi 0:098463de4c5d 99 }
group-onsemi 0:098463de4c5d 100 NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
group-onsemi 0:098463de4c5d 101 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
group-onsemi 0:098463de4c5d 102
group-onsemi 0:098463de4c5d 103 return 0;
group-onsemi 0:098463de4c5d 104 }
group-onsemi 0:098463de4c5d 105
group-onsemi 0:098463de4c5d 106 void gpio_irq_free(gpio_irq_t *obj) {
group-onsemi 0:098463de4c5d 107 channel_ids[obj->ch] = 0;
group-onsemi 0:098463de4c5d 108 LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
group-onsemi 0:098463de4c5d 109 }
group-onsemi 0:098463de4c5d 110
group-onsemi 0:098463de4c5d 111 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
group-onsemi 0:098463de4c5d 112 unsigned int ch_bit = (1 << obj->ch);
group-onsemi 0:098463de4c5d 113
group-onsemi 0:098463de4c5d 114 // Clear interrupt
group-onsemi 0:098463de4c5d 115 if (!(LPC_GPIO_X->ISEL & ch_bit))
group-onsemi 0:098463de4c5d 116 LPC_GPIO_X->IST = ch_bit;
group-onsemi 0:098463de4c5d 117
group-onsemi 0:098463de4c5d 118 // Edge trigger
group-onsemi 0:098463de4c5d 119 LPC_GPIO_X->ISEL &= ~ch_bit;
group-onsemi 0:098463de4c5d 120 if (event == IRQ_RISE) {
group-onsemi 0:098463de4c5d 121 if (enable) {
group-onsemi 0:098463de4c5d 122 LPC_GPIO_X->IENR |= ch_bit;
group-onsemi 0:098463de4c5d 123 } else {
group-onsemi 0:098463de4c5d 124 LPC_GPIO_X->IENR &= ~ch_bit;
group-onsemi 0:098463de4c5d 125 }
group-onsemi 0:098463de4c5d 126 } else {
group-onsemi 0:098463de4c5d 127 if (enable) {
group-onsemi 0:098463de4c5d 128 LPC_GPIO_X->IENF |= ch_bit;
group-onsemi 0:098463de4c5d 129 } else {
group-onsemi 0:098463de4c5d 130 LPC_GPIO_X->IENF &= ~ch_bit;
group-onsemi 0:098463de4c5d 131 }
group-onsemi 0:098463de4c5d 132 }
group-onsemi 0:098463de4c5d 133 }
group-onsemi 0:098463de4c5d 134
group-onsemi 0:098463de4c5d 135 void gpio_irq_enable(gpio_irq_t *obj) {
group-onsemi 0:098463de4c5d 136 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
group-onsemi 0:098463de4c5d 137 }
group-onsemi 0:098463de4c5d 138
group-onsemi 0:098463de4c5d 139 void gpio_irq_disable(gpio_irq_t *obj) {
group-onsemi 0:098463de4c5d 140 NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
group-onsemi 0:098463de4c5d 141 }