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targets/TARGET_Maxim/TARGET_MAX32620/device/pwrseq_regs.h@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #ifndef _MXC_PWRSEQ_REGS_H_
group-onsemi 0:098463de4c5d 35 #define _MXC_PWRSEQ_REGS_H_
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 38 extern "C" {
group-onsemi 0:098463de4c5d 39 #endif
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 #include <stdint.h>
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 /*
group-onsemi 0:098463de4c5d 44 If types are not defined elsewhere (CMSIS) define them here
group-onsemi 0:098463de4c5d 45 */
group-onsemi 0:098463de4c5d 46 #ifndef __IO
group-onsemi 0:098463de4c5d 47 #define __IO volatile
group-onsemi 0:098463de4c5d 48 #endif
group-onsemi 0:098463de4c5d 49 #ifndef __I
group-onsemi 0:098463de4c5d 50 #define __I volatile const
group-onsemi 0:098463de4c5d 51 #endif
group-onsemi 0:098463de4c5d 52 #ifndef __O
group-onsemi 0:098463de4c5d 53 #define __O volatile
group-onsemi 0:098463de4c5d 54 #endif
group-onsemi 0:098463de4c5d 55
group-onsemi 0:098463de4c5d 56
group-onsemi 0:098463de4c5d 57 /*
group-onsemi 0:098463de4c5d 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
group-onsemi 0:098463de4c5d 59 access to each register in module.
group-onsemi 0:098463de4c5d 60 */
group-onsemi 0:098463de4c5d 61
group-onsemi 0:098463de4c5d 62 /* Offset Register Description
group-onsemi 0:098463de4c5d 63 ============= ============================================================================ */
group-onsemi 0:098463de4c5d 64 typedef struct {
group-onsemi 0:098463de4c5d 65 __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */
group-onsemi 0:098463de4c5d 66 __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */
group-onsemi 0:098463de4c5d 67 __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */
group-onsemi 0:098463de4c5d 68 __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */
group-onsemi 0:098463de4c5d 69 __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 (Internal Test Only) */
group-onsemi 0:098463de4c5d 70 __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */
group-onsemi 0:098463de4c5d 71 __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */
group-onsemi 0:098463de4c5d 72 __IO uint32_t reg7; /* 0x001C Power Sequencer Control Register 7 (Trim 2) */
group-onsemi 0:098463de4c5d 73 __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */
group-onsemi 0:098463de4c5d 74 __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */
group-onsemi 0:098463de4c5d 75 __I uint32_t rsv028[2]; /* 0x0028-0x002C */
group-onsemi 0:098463de4c5d 76 __IO uint32_t retn_ctrl0; /* 0x0030 Retention Control Register 0 */
group-onsemi 0:098463de4c5d 77 __IO uint32_t retn_ctrl1; /* 0x0034 Retention Control Register 1 */
group-onsemi 0:098463de4c5d 78 } mxc_pwrseq_regs_t;
group-onsemi 0:098463de4c5d 79
group-onsemi 0:098463de4c5d 80
group-onsemi 0:098463de4c5d 81 /*
group-onsemi 0:098463de4c5d 82 Register offsets for module PWRSEQ.
group-onsemi 0:098463de4c5d 83 */
group-onsemi 0:098463de4c5d 84
group-onsemi 0:098463de4c5d 85 #define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL)
group-onsemi 0:098463de4c5d 86 #define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL)
group-onsemi 0:098463de4c5d 87 #define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL)
group-onsemi 0:098463de4c5d 88 #define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL)
group-onsemi 0:098463de4c5d 89 #define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL)
group-onsemi 0:098463de4c5d 90 #define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL)
group-onsemi 0:098463de4c5d 91 #define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL)
group-onsemi 0:098463de4c5d 92 #define MXC_R_PWRSEQ_OFFS_REG7 ((uint32_t)0x0000001CUL)
group-onsemi 0:098463de4c5d 93 #define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL)
group-onsemi 0:098463de4c5d 94 #define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL)
group-onsemi 0:098463de4c5d 95 #define MXC_R_PWRSEQ_OFFS_RETN_CTRL0 ((uint32_t)0x00000030UL)
group-onsemi 0:098463de4c5d 96 #define MXC_R_PWRSEQ_OFFS_RETN_CTRL1 ((uint32_t)0x00000034UL)
group-onsemi 0:098463de4c5d 97
group-onsemi 0:098463de4c5d 98
group-onsemi 0:098463de4c5d 99 /*
group-onsemi 0:098463de4c5d 100 Field positions and masks for module PWRSEQ.
group-onsemi 0:098463de4c5d 101 */
group-onsemi 0:098463de4c5d 102
group-onsemi 0:098463de4c5d 103 #define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0
group-onsemi 0:098463de4c5d 104 #define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS))
group-onsemi 0:098463de4c5d 105 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1
group-onsemi 0:098463de4c5d 106 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS))
group-onsemi 0:098463de4c5d 107 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2
group-onsemi 0:098463de4c5d 108 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS))
group-onsemi 0:098463de4c5d 109 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS 3
group-onsemi 0:098463de4c5d 110 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS))
group-onsemi 0:098463de4c5d 111 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS 4
group-onsemi 0:098463de4c5d 112 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS))
group-onsemi 0:098463de4c5d 113 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS 5
group-onsemi 0:098463de4c5d 114 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS))
group-onsemi 0:098463de4c5d 115 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS 6
group-onsemi 0:098463de4c5d 116 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS))
group-onsemi 0:098463de4c5d 117 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7
group-onsemi 0:098463de4c5d 118 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS))
group-onsemi 0:098463de4c5d 119 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8
group-onsemi 0:098463de4c5d 120 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS))
group-onsemi 0:098463de4c5d 121 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9
group-onsemi 0:098463de4c5d 122 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS))
group-onsemi 0:098463de4c5d 123 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10
group-onsemi 0:098463de4c5d 124 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS))
group-onsemi 0:098463de4c5d 125 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11
group-onsemi 0:098463de4c5d 126 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS))
group-onsemi 0:098463de4c5d 127 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12
group-onsemi 0:098463de4c5d 128 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS))
group-onsemi 0:098463de4c5d 129 #define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS 13
group-onsemi 0:098463de4c5d 130 #define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS))
group-onsemi 0:098463de4c5d 131 #define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS 15
group-onsemi 0:098463de4c5d 132 #define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS))
group-onsemi 0:098463de4c5d 133 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17
group-onsemi 0:098463de4c5d 134 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS))
group-onsemi 0:098463de4c5d 135 #define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS 19
group-onsemi 0:098463de4c5d 136 #define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS))
group-onsemi 0:098463de4c5d 137 #define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS 21
group-onsemi 0:098463de4c5d 138 #define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS))
group-onsemi 0:098463de4c5d 139 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS 23
group-onsemi 0:098463de4c5d 140 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS))
group-onsemi 0:098463de4c5d 141 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS 24
group-onsemi 0:098463de4c5d 142 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS))
group-onsemi 0:098463de4c5d 143 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS 25
group-onsemi 0:098463de4c5d 144 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS))
group-onsemi 0:098463de4c5d 145 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS 26
group-onsemi 0:098463de4c5d 146 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS))
group-onsemi 0:098463de4c5d 147 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS 27
group-onsemi 0:098463de4c5d 148 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS))
group-onsemi 0:098463de4c5d 149 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS 28
group-onsemi 0:098463de4c5d 150 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS))
group-onsemi 0:098463de4c5d 151
group-onsemi 0:098463de4c5d 152 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS 0
group-onsemi 0:098463de4c5d 153 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS))
group-onsemi 0:098463de4c5d 154 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS 1
group-onsemi 0:098463de4c5d 155 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS))
group-onsemi 0:098463de4c5d 156 #define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS 2
group-onsemi 0:098463de4c5d 157 #define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS))
group-onsemi 0:098463de4c5d 158 #define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS 3
group-onsemi 0:098463de4c5d 159 #define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS))
group-onsemi 0:098463de4c5d 160 #define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS 4
group-onsemi 0:098463de4c5d 161 #define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS))
group-onsemi 0:098463de4c5d 162
group-onsemi 0:098463de4c5d 163 #define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS 0
group-onsemi 0:098463de4c5d 164 #define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS))
group-onsemi 0:098463de4c5d 165 #define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS 2
group-onsemi 0:098463de4c5d 166 #define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS))
group-onsemi 0:098463de4c5d 167 #define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS 4
group-onsemi 0:098463de4c5d 168 #define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS))
group-onsemi 0:098463de4c5d 169 #define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS 6
group-onsemi 0:098463de4c5d 170 #define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS))
group-onsemi 0:098463de4c5d 171 #define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS 8
group-onsemi 0:098463de4c5d 172 #define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS))
group-onsemi 0:098463de4c5d 173
group-onsemi 0:098463de4c5d 174 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0
group-onsemi 0:098463de4c5d 175 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS))
group-onsemi 0:098463de4c5d 176 #define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS 3
group-onsemi 0:098463de4c5d 177 #define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS))
group-onsemi 0:098463de4c5d 178 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 6
group-onsemi 0:098463de4c5d 179 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS))
group-onsemi 0:098463de4c5d 180 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 8
group-onsemi 0:098463de4c5d 181 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS))
group-onsemi 0:098463de4c5d 182 #define MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS 10
group-onsemi 0:098463de4c5d 183 #define MXC_F_PWRSEQ_REG3_PWR_FAILSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS))
group-onsemi 0:098463de4c5d 184
group-onsemi 0:098463de4c5d 185 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0
group-onsemi 0:098463de4c5d 186 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS))
group-onsemi 0:098463de4c5d 187 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1
group-onsemi 0:098463de4c5d 188 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS))
group-onsemi 0:098463de4c5d 189 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3
group-onsemi 0:098463de4c5d 190 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS))
group-onsemi 0:098463de4c5d 191 #define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS 4
group-onsemi 0:098463de4c5d 192 #define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS))
group-onsemi 0:098463de4c5d 193 #define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS 5
group-onsemi 0:098463de4c5d 194 #define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS))
group-onsemi 0:098463de4c5d 195 #define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS 6
group-onsemi 0:098463de4c5d 196 #define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS))
group-onsemi 0:098463de4c5d 197 #define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS 7
group-onsemi 0:098463de4c5d 198 #define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS))
group-onsemi 0:098463de4c5d 199
group-onsemi 0:098463de4c5d 200 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0
group-onsemi 0:098463de4c5d 201 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS))
group-onsemi 0:098463de4c5d 202 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS 9
group-onsemi 0:098463de4c5d 203 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS))
group-onsemi 0:098463de4c5d 204 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_POS 15
group-onsemi 0:098463de4c5d 205 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_POS))
group-onsemi 0:098463de4c5d 206 #define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS 21
group-onsemi 0:098463de4c5d 207 #define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS))
group-onsemi 0:098463de4c5d 208
group-onsemi 0:098463de4c5d 209 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0
group-onsemi 0:098463de4c5d 210 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS))
group-onsemi 0:098463de4c5d 211 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3
group-onsemi 0:098463de4c5d 212 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS))
group-onsemi 0:098463de4c5d 213 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7
group-onsemi 0:098463de4c5d 214 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS))
group-onsemi 0:098463de4c5d 215 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS 11
group-onsemi 0:098463de4c5d 216 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS))
group-onsemi 0:098463de4c5d 217 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS 20
group-onsemi 0:098463de4c5d 218 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS))
group-onsemi 0:098463de4c5d 219
group-onsemi 0:098463de4c5d 220 #define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS 0
group-onsemi 0:098463de4c5d 221 #define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS))
group-onsemi 0:098463de4c5d 222
group-onsemi 0:098463de4c5d 223 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0
group-onsemi 0:098463de4c5d 224 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS))
group-onsemi 0:098463de4c5d 225 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1
group-onsemi 0:098463de4c5d 226 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS))
group-onsemi 0:098463de4c5d 227 #define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS 2
group-onsemi 0:098463de4c5d 228 #define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS))
group-onsemi 0:098463de4c5d 229 #define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS 3
group-onsemi 0:098463de4c5d 230 #define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS))
group-onsemi 0:098463de4c5d 231 #define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS 4
group-onsemi 0:098463de4c5d 232 #define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS))
group-onsemi 0:098463de4c5d 233 #define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS 5
group-onsemi 0:098463de4c5d 234 #define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS))
group-onsemi 0:098463de4c5d 235 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS 6
group-onsemi 0:098463de4c5d 236 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS))
group-onsemi 0:098463de4c5d 237 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS 7
group-onsemi 0:098463de4c5d 238 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS))
group-onsemi 0:098463de4c5d 239 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS 8
group-onsemi 0:098463de4c5d 240 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS))
group-onsemi 0:098463de4c5d 241 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS 9
group-onsemi 0:098463de4c5d 242 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS))
group-onsemi 0:098463de4c5d 243 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS 10
group-onsemi 0:098463de4c5d 244 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS))
group-onsemi 0:098463de4c5d 245 #define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11
group-onsemi 0:098463de4c5d 246 #define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS))
group-onsemi 0:098463de4c5d 247 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 12
group-onsemi 0:098463de4c5d 248 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS))
group-onsemi 0:098463de4c5d 249 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 13
group-onsemi 0:098463de4c5d 250 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS))
group-onsemi 0:098463de4c5d 251 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 14
group-onsemi 0:098463de4c5d 252 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS))
group-onsemi 0:098463de4c5d 253 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 15
group-onsemi 0:098463de4c5d 254 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS))
group-onsemi 0:098463de4c5d 255 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16
group-onsemi 0:098463de4c5d 256 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
group-onsemi 0:098463de4c5d 257 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17
group-onsemi 0:098463de4c5d 258 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
group-onsemi 0:098463de4c5d 259 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS 18
group-onsemi 0:098463de4c5d 260 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS))
group-onsemi 0:098463de4c5d 261
group-onsemi 0:098463de4c5d 262 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1
group-onsemi 0:098463de4c5d 263 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS))
group-onsemi 0:098463de4c5d 264 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS 2
group-onsemi 0:098463de4c5d 265 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS))
group-onsemi 0:098463de4c5d 266 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS 3
group-onsemi 0:098463de4c5d 267 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS))
group-onsemi 0:098463de4c5d 268 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS 4
group-onsemi 0:098463de4c5d 269 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS))
group-onsemi 0:098463de4c5d 270 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS 5
group-onsemi 0:098463de4c5d 271 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS))
group-onsemi 0:098463de4c5d 272 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS 6
group-onsemi 0:098463de4c5d 273 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS))
group-onsemi 0:098463de4c5d 274 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS 7
group-onsemi 0:098463de4c5d 275 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS))
group-onsemi 0:098463de4c5d 276 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS 8
group-onsemi 0:098463de4c5d 277 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS))
group-onsemi 0:098463de4c5d 278 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS 9
group-onsemi 0:098463de4c5d 279 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS))
group-onsemi 0:098463de4c5d 280 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS 10
group-onsemi 0:098463de4c5d 281 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS))
group-onsemi 0:098463de4c5d 282 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11
group-onsemi 0:098463de4c5d 283 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS))
group-onsemi 0:098463de4c5d 284 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 12
group-onsemi 0:098463de4c5d 285 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS))
group-onsemi 0:098463de4c5d 286 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 13
group-onsemi 0:098463de4c5d 287 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS))
group-onsemi 0:098463de4c5d 288 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 14
group-onsemi 0:098463de4c5d 289 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS))
group-onsemi 0:098463de4c5d 290 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 15
group-onsemi 0:098463de4c5d 291 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS))
group-onsemi 0:098463de4c5d 292 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16
group-onsemi 0:098463de4c5d 293 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
group-onsemi 0:098463de4c5d 294 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17
group-onsemi 0:098463de4c5d 295 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
group-onsemi 0:098463de4c5d 296 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS 18
group-onsemi 0:098463de4c5d 297 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS))
group-onsemi 0:098463de4c5d 298
group-onsemi 0:098463de4c5d 299 #define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS 0
group-onsemi 0:098463de4c5d 300 #define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS))
group-onsemi 0:098463de4c5d 301 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS 1
group-onsemi 0:098463de4c5d 302 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS))
group-onsemi 0:098463de4c5d 303 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS 2
group-onsemi 0:098463de4c5d 304 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS))
group-onsemi 0:098463de4c5d 305 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS 3
group-onsemi 0:098463de4c5d 306 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS))
group-onsemi 0:098463de4c5d 307 #define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS 4
group-onsemi 0:098463de4c5d 308 #define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS))
group-onsemi 0:098463de4c5d 309
group-onsemi 0:098463de4c5d 310 #define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS 0
group-onsemi 0:098463de4c5d 311 #define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS))
group-onsemi 0:098463de4c5d 312 #define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS 4
group-onsemi 0:098463de4c5d 313 #define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS))
group-onsemi 0:098463de4c5d 314
group-onsemi 0:098463de4c5d 315
group-onsemi 0:098463de4c5d 316
group-onsemi 0:098463de4c5d 317 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 318 }
group-onsemi 0:098463de4c5d 319 #endif
group-onsemi 0:098463de4c5d 320
group-onsemi 0:098463de4c5d 321 #endif /* _MXC_PWRSEQ_REGS_H_ */
group-onsemi 0:098463de4c5d 322