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targets/TARGET_Maxim/TARGET_MAX32620/device/pwrman_regs.h@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #ifndef _MXC_PWRMAN_REGS_H_
group-onsemi 0:098463de4c5d 35 #define _MXC_PWRMAN_REGS_H_
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 38 extern "C" {
group-onsemi 0:098463de4c5d 39 #endif
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 #include <stdint.h>
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 /*
group-onsemi 0:098463de4c5d 44 If types are not defined elsewhere (CMSIS) define them here
group-onsemi 0:098463de4c5d 45 */
group-onsemi 0:098463de4c5d 46 #ifndef __IO
group-onsemi 0:098463de4c5d 47 #define __IO volatile
group-onsemi 0:098463de4c5d 48 #endif
group-onsemi 0:098463de4c5d 49 #ifndef __I
group-onsemi 0:098463de4c5d 50 #define __I volatile const
group-onsemi 0:098463de4c5d 51 #endif
group-onsemi 0:098463de4c5d 52 #ifndef __O
group-onsemi 0:098463de4c5d 53 #define __O volatile
group-onsemi 0:098463de4c5d 54 #endif
group-onsemi 0:098463de4c5d 55
group-onsemi 0:098463de4c5d 56
group-onsemi 0:098463de4c5d 57 /**
group-onsemi 0:098463de4c5d 58 * @brief Defines PAD Modes for Wake Up Detection.
group-onsemi 0:098463de4c5d 59 */
group-onsemi 0:098463de4c5d 60 typedef enum {
group-onsemi 0:098463de4c5d 61 /** WUD Mode for Selected PAD = Clear/Activate */
group-onsemi 0:098463de4c5d 62 MXC_E_PWRMAN_PAD_MODE_CLEAR_SET,
group-onsemi 0:098463de4c5d 63 /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */
group-onsemi 0:098463de4c5d 64 MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO,
group-onsemi 0:098463de4c5d 65 /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */
group-onsemi 0:098463de4c5d 66 MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO,
group-onsemi 0:098463de4c5d 67 /** WUD Mode for Selected PAD = No pad state change */
group-onsemi 0:098463de4c5d 68 MXC_E_PWRMAN_PAD_MODE_NONE
group-onsemi 0:098463de4c5d 69 } mxc_pwrman_pad_mode_t;
group-onsemi 0:098463de4c5d 70
group-onsemi 0:098463de4c5d 71 /*
group-onsemi 0:098463de4c5d 72 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
group-onsemi 0:098463de4c5d 73 access to each register in module.
group-onsemi 0:098463de4c5d 74 */
group-onsemi 0:098463de4c5d 75
group-onsemi 0:098463de4c5d 76 /* Offset Register Description
group-onsemi 0:098463de4c5d 77 ============= ============================================================================ */
group-onsemi 0:098463de4c5d 78 typedef struct {
group-onsemi 0:098463de4c5d 79 __IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */
group-onsemi 0:098463de4c5d 80 __IO uint32_t intfl; /* 0x0004 Interrupt Flags */
group-onsemi 0:098463de4c5d 81 __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */
group-onsemi 0:098463de4c5d 82 __IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */
group-onsemi 0:098463de4c5d 83 __IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */
group-onsemi 0:098463de4c5d 84 __IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */
group-onsemi 0:098463de4c5d 85 __IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */
group-onsemi 0:098463de4c5d 86 __IO uint32_t wud_seen0; /* 0x001C Wake-up Detect Status for P0/P1/P2/P3 */
group-onsemi 0:098463de4c5d 87 __IO uint32_t wud_seen1; /* 0x0020 Wake-up Detect Status for P4/P5/P6/P7 */
group-onsemi 0:098463de4c5d 88 __I uint32_t rsv024[5]; /* 0x0024-0x0034 */
group-onsemi 0:098463de4c5d 89 __IO uint32_t die_type; /* 0x0038 Die Type ID Register */
group-onsemi 0:098463de4c5d 90 __IO uint32_t base_part_num; /* 0x003C Base Part Number */
group-onsemi 0:098463de4c5d 91 __IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */
group-onsemi 0:098463de4c5d 92 __IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */
group-onsemi 0:098463de4c5d 93 __IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */
group-onsemi 0:098463de4c5d 94 } mxc_pwrman_regs_t;
group-onsemi 0:098463de4c5d 95
group-onsemi 0:098463de4c5d 96
group-onsemi 0:098463de4c5d 97 /*
group-onsemi 0:098463de4c5d 98 Register offsets for module PWRMAN.
group-onsemi 0:098463de4c5d 99 */
group-onsemi 0:098463de4c5d 100
group-onsemi 0:098463de4c5d 101 #define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL)
group-onsemi 0:098463de4c5d 102 #define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL)
group-onsemi 0:098463de4c5d 103 #define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL)
group-onsemi 0:098463de4c5d 104 #define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL)
group-onsemi 0:098463de4c5d 105 #define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL)
group-onsemi 0:098463de4c5d 106 #define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL)
group-onsemi 0:098463de4c5d 107 #define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL)
group-onsemi 0:098463de4c5d 108 #define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x0000001CUL)
group-onsemi 0:098463de4c5d 109 #define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000020UL)
group-onsemi 0:098463de4c5d 110 #define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL)
group-onsemi 0:098463de4c5d 111 #define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL)
group-onsemi 0:098463de4c5d 112 #define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL)
group-onsemi 0:098463de4c5d 113 #define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL)
group-onsemi 0:098463de4c5d 114 #define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL)
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116
group-onsemi 0:098463de4c5d 117 /*
group-onsemi 0:098463de4c5d 118 Field positions and masks for module PWRMAN.
group-onsemi 0:098463de4c5d 119 */
group-onsemi 0:098463de4c5d 120
group-onsemi 0:098463de4c5d 121 #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2
group-onsemi 0:098463de4c5d 122 #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS))
group-onsemi 0:098463de4c5d 123 #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3
group-onsemi 0:098463de4c5d 124 #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS))
group-onsemi 0:098463de4c5d 125 #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4
group-onsemi 0:098463de4c5d 126 #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS))
group-onsemi 0:098463de4c5d 127 #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5
group-onsemi 0:098463de4c5d 128 #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS))
group-onsemi 0:098463de4c5d 129 #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8
group-onsemi 0:098463de4c5d 130 #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS))
group-onsemi 0:098463de4c5d 131 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9
group-onsemi 0:098463de4c5d 132 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS))
group-onsemi 0:098463de4c5d 133 #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16
group-onsemi 0:098463de4c5d 134 #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS))
group-onsemi 0:098463de4c5d 135 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 17
group-onsemi 0:098463de4c5d 136 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS))
group-onsemi 0:098463de4c5d 137 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 18
group-onsemi 0:098463de4c5d 138 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS))
group-onsemi 0:098463de4c5d 139 #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 19
group-onsemi 0:098463de4c5d 140 #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS))
group-onsemi 0:098463de4c5d 141 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 20
group-onsemi 0:098463de4c5d 142 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS))
group-onsemi 0:098463de4c5d 143 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21
group-onsemi 0:098463de4c5d 144 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS))
group-onsemi 0:098463de4c5d 145 #define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22
group-onsemi 0:098463de4c5d 146 #define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS))
group-onsemi 0:098463de4c5d 147 #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31
group-onsemi 0:098463de4c5d 148 #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS))
group-onsemi 0:098463de4c5d 149
group-onsemi 0:098463de4c5d 150 #define MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS 0
group-onsemi 0:098463de4c5d 151 #define MXC_F_PWRMAN_INTFL_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS))
group-onsemi 0:098463de4c5d 152 #define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 1
group-onsemi 0:098463de4c5d 153 #define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS))
group-onsemi 0:098463de4c5d 154 #define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2
group-onsemi 0:098463de4c5d 155 #define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS))
group-onsemi 0:098463de4c5d 156 #define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 3
group-onsemi 0:098463de4c5d 157 #define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS))
group-onsemi 0:098463de4c5d 158 #define MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS 4
group-onsemi 0:098463de4c5d 159 #define MXC_F_PWRMAN_INTFL_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS))
group-onsemi 0:098463de4c5d 160
group-onsemi 0:098463de4c5d 161 #define MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS 0
group-onsemi 0:098463de4c5d 162 #define MXC_F_PWRMAN_INTEN_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS))
group-onsemi 0:098463de4c5d 163 #define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 1
group-onsemi 0:098463de4c5d 164 #define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS))
group-onsemi 0:098463de4c5d 165 #define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2
group-onsemi 0:098463de4c5d 166 #define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS))
group-onsemi 0:098463de4c5d 167 #define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 3
group-onsemi 0:098463de4c5d 168 #define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS))
group-onsemi 0:098463de4c5d 169 #define MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS 4
group-onsemi 0:098463de4c5d 170 #define MXC_F_PWRMAN_INTEN_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS))
group-onsemi 0:098463de4c5d 171
group-onsemi 0:098463de4c5d 172 #define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS 0
group-onsemi 0:098463de4c5d 173 #define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS))
group-onsemi 0:098463de4c5d 174 #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 1
group-onsemi 0:098463de4c5d 175 #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS))
group-onsemi 0:098463de4c5d 176 #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2
group-onsemi 0:098463de4c5d 177 #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS))
group-onsemi 0:098463de4c5d 178 #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 3
group-onsemi 0:098463de4c5d 179 #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS))
group-onsemi 0:098463de4c5d 180 #define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS 4
group-onsemi 0:098463de4c5d 181 #define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS))
group-onsemi 0:098463de4c5d 182
group-onsemi 0:098463de4c5d 183 #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0
group-onsemi 0:098463de4c5d 184 #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS))
group-onsemi 0:098463de4c5d 185 #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8
group-onsemi 0:098463de4c5d 186 #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS))
group-onsemi 0:098463de4c5d 187 #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12
group-onsemi 0:098463de4c5d 188 #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS))
group-onsemi 0:098463de4c5d 189 #define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS 16
group-onsemi 0:098463de4c5d 190 #define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS))
group-onsemi 0:098463de4c5d 191
group-onsemi 0:098463de4c5d 192 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0
group-onsemi 0:098463de4c5d 193 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS))
group-onsemi 0:098463de4c5d 194 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1
group-onsemi 0:098463de4c5d 195 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS))
group-onsemi 0:098463de4c5d 196 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2
group-onsemi 0:098463de4c5d 197 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS))
group-onsemi 0:098463de4c5d 198 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3
group-onsemi 0:098463de4c5d 199 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS))
group-onsemi 0:098463de4c5d 200 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4
group-onsemi 0:098463de4c5d 201 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS))
group-onsemi 0:098463de4c5d 202 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5
group-onsemi 0:098463de4c5d 203 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS))
group-onsemi 0:098463de4c5d 204 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6
group-onsemi 0:098463de4c5d 205 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS))
group-onsemi 0:098463de4c5d 206 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7
group-onsemi 0:098463de4c5d 207 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS))
group-onsemi 0:098463de4c5d 208 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8
group-onsemi 0:098463de4c5d 209 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS))
group-onsemi 0:098463de4c5d 210 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9
group-onsemi 0:098463de4c5d 211 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS))
group-onsemi 0:098463de4c5d 212 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10
group-onsemi 0:098463de4c5d 213 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS))
group-onsemi 0:098463de4c5d 214 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11
group-onsemi 0:098463de4c5d 215 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS))
group-onsemi 0:098463de4c5d 216 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12
group-onsemi 0:098463de4c5d 217 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS))
group-onsemi 0:098463de4c5d 218 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13
group-onsemi 0:098463de4c5d 219 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS))
group-onsemi 0:098463de4c5d 220 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14
group-onsemi 0:098463de4c5d 221 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS))
group-onsemi 0:098463de4c5d 222 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15
group-onsemi 0:098463de4c5d 223 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS))
group-onsemi 0:098463de4c5d 224 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16
group-onsemi 0:098463de4c5d 225 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS))
group-onsemi 0:098463de4c5d 226 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17
group-onsemi 0:098463de4c5d 227 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS))
group-onsemi 0:098463de4c5d 228 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18
group-onsemi 0:098463de4c5d 229 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS))
group-onsemi 0:098463de4c5d 230 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19
group-onsemi 0:098463de4c5d 231 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS))
group-onsemi 0:098463de4c5d 232 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20
group-onsemi 0:098463de4c5d 233 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS))
group-onsemi 0:098463de4c5d 234 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21
group-onsemi 0:098463de4c5d 235 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS))
group-onsemi 0:098463de4c5d 236 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22
group-onsemi 0:098463de4c5d 237 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS))
group-onsemi 0:098463de4c5d 238 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23
group-onsemi 0:098463de4c5d 239 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS))
group-onsemi 0:098463de4c5d 240 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24
group-onsemi 0:098463de4c5d 241 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS))
group-onsemi 0:098463de4c5d 242 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25
group-onsemi 0:098463de4c5d 243 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS))
group-onsemi 0:098463de4c5d 244 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26
group-onsemi 0:098463de4c5d 245 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS))
group-onsemi 0:098463de4c5d 246 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27
group-onsemi 0:098463de4c5d 247 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS))
group-onsemi 0:098463de4c5d 248 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28
group-onsemi 0:098463de4c5d 249 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS))
group-onsemi 0:098463de4c5d 250 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29
group-onsemi 0:098463de4c5d 251 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS))
group-onsemi 0:098463de4c5d 252 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30
group-onsemi 0:098463de4c5d 253 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS))
group-onsemi 0:098463de4c5d 254 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31
group-onsemi 0:098463de4c5d 255 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS))
group-onsemi 0:098463de4c5d 256
group-onsemi 0:098463de4c5d 257 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0
group-onsemi 0:098463de4c5d 258 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS))
group-onsemi 0:098463de4c5d 259 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1
group-onsemi 0:098463de4c5d 260 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS))
group-onsemi 0:098463de4c5d 261 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2
group-onsemi 0:098463de4c5d 262 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS))
group-onsemi 0:098463de4c5d 263 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3
group-onsemi 0:098463de4c5d 264 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS))
group-onsemi 0:098463de4c5d 265 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4
group-onsemi 0:098463de4c5d 266 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS))
group-onsemi 0:098463de4c5d 267 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5
group-onsemi 0:098463de4c5d 268 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS))
group-onsemi 0:098463de4c5d 269 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6
group-onsemi 0:098463de4c5d 270 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS))
group-onsemi 0:098463de4c5d 271 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7
group-onsemi 0:098463de4c5d 272 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS))
group-onsemi 0:098463de4c5d 273 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS 8
group-onsemi 0:098463de4c5d 274 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO40 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS))
group-onsemi 0:098463de4c5d 275 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS 9
group-onsemi 0:098463de4c5d 276 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO41 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS))
group-onsemi 0:098463de4c5d 277 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS 10
group-onsemi 0:098463de4c5d 278 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO42 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS))
group-onsemi 0:098463de4c5d 279 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS 11
group-onsemi 0:098463de4c5d 280 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO43 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS))
group-onsemi 0:098463de4c5d 281 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS 12
group-onsemi 0:098463de4c5d 282 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO44 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS))
group-onsemi 0:098463de4c5d 283 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS 13
group-onsemi 0:098463de4c5d 284 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO45 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS))
group-onsemi 0:098463de4c5d 285 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS 14
group-onsemi 0:098463de4c5d 286 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO46 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS))
group-onsemi 0:098463de4c5d 287 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS 15
group-onsemi 0:098463de4c5d 288 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO47 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS))
group-onsemi 0:098463de4c5d 289 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS 16
group-onsemi 0:098463de4c5d 290 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO48 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS))
group-onsemi 0:098463de4c5d 291
group-onsemi 0:098463de4c5d 292 #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0
group-onsemi 0:098463de4c5d 293 #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS))
group-onsemi 0:098463de4c5d 294
group-onsemi 0:098463de4c5d 295 #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0
group-onsemi 0:098463de4c5d 296 #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS))
group-onsemi 0:098463de4c5d 297 #define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4
group-onsemi 0:098463de4c5d 298 #define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS))
group-onsemi 0:098463de4c5d 299
group-onsemi 0:098463de4c5d 300 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0
group-onsemi 0:098463de4c5d 301 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS))
group-onsemi 0:098463de4c5d 302 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31
group-onsemi 0:098463de4c5d 303 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS))
group-onsemi 0:098463de4c5d 304
group-onsemi 0:098463de4c5d 305 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 0
group-onsemi 0:098463de4c5d 306 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS))
group-onsemi 0:098463de4c5d 307 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS 1
group-onsemi 0:098463de4c5d 308 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS))
group-onsemi 0:098463de4c5d 309 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS 2
group-onsemi 0:098463de4c5d 310 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS))
group-onsemi 0:098463de4c5d 311 #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 3
group-onsemi 0:098463de4c5d 312 #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS))
group-onsemi 0:098463de4c5d 313 #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 4
group-onsemi 0:098463de4c5d 314 #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS))
group-onsemi 0:098463de4c5d 315 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 5
group-onsemi 0:098463de4c5d 316 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS))
group-onsemi 0:098463de4c5d 317 #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6
group-onsemi 0:098463de4c5d 318 #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS))
group-onsemi 0:098463de4c5d 319 #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 7
group-onsemi 0:098463de4c5d 320 #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS))
group-onsemi 0:098463de4c5d 321 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 8
group-onsemi 0:098463de4c5d 322 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS))
group-onsemi 0:098463de4c5d 323 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 9
group-onsemi 0:098463de4c5d 324 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS))
group-onsemi 0:098463de4c5d 325 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 10
group-onsemi 0:098463de4c5d 326 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS))
group-onsemi 0:098463de4c5d 327 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 11
group-onsemi 0:098463de4c5d 328 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS))
group-onsemi 0:098463de4c5d 329 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS 12
group-onsemi 0:098463de4c5d 330 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS))
group-onsemi 0:098463de4c5d 331 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS 13
group-onsemi 0:098463de4c5d 332 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS))
group-onsemi 0:098463de4c5d 333 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 14
group-onsemi 0:098463de4c5d 334 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS))
group-onsemi 0:098463de4c5d 335 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 15
group-onsemi 0:098463de4c5d 336 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS))
group-onsemi 0:098463de4c5d 337 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 16
group-onsemi 0:098463de4c5d 338 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS))
group-onsemi 0:098463de4c5d 339 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS 17
group-onsemi 0:098463de4c5d 340 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS))
group-onsemi 0:098463de4c5d 341 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART3_POS 18
group-onsemi 0:098463de4c5d 342 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART3_POS))
group-onsemi 0:098463de4c5d 343 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 19
group-onsemi 0:098463de4c5d 344 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS))
group-onsemi 0:098463de4c5d 345 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 20
group-onsemi 0:098463de4c5d 346 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS))
group-onsemi 0:098463de4c5d 347 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2_POS 21
group-onsemi 0:098463de4c5d 348 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2_POS))
group-onsemi 0:098463de4c5d 349 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22
group-onsemi 0:098463de4c5d 350 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS))
group-onsemi 0:098463de4c5d 351 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS 23
group-onsemi 0:098463de4c5d 352 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS))
group-onsemi 0:098463de4c5d 353 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS 24
group-onsemi 0:098463de4c5d 354 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS))
group-onsemi 0:098463de4c5d 355 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS 25
group-onsemi 0:098463de4c5d 356 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS))
group-onsemi 0:098463de4c5d 357 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB_POS 26
group-onsemi 0:098463de4c5d 358 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB_POS))
group-onsemi 0:098463de4c5d 359 #define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS 27
group-onsemi 0:098463de4c5d 360 #define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS))
group-onsemi 0:098463de4c5d 361 #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 28
group-onsemi 0:098463de4c5d 362 #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS))
group-onsemi 0:098463de4c5d 363
group-onsemi 0:098463de4c5d 364
group-onsemi 0:098463de4c5d 365
group-onsemi 0:098463de4c5d 366 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 367 }
group-onsemi 0:098463de4c5d 368 #endif
group-onsemi 0:098463de4c5d 369
group-onsemi 0:098463de4c5d 370 #endif /* _MXC_PWRMAN_REGS_H_ */
group-onsemi 0:098463de4c5d 371