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targets/TARGET_Maxim/TARGET_MAX32620/device/owm_regs.h@0:098463de4c5d, 2017-01-25 (annotated)
- Committer:
- group-onsemi
- Date:
- Wed Jan 25 20:34:15 2017 +0000
- Revision:
- 0:098463de4c5d
Initial commit
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| group-onsemi | 0:098463de4c5d | 1 | /******************************************************************************* |
| group-onsemi | 0:098463de4c5d | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| group-onsemi | 0:098463de4c5d | 3 | * |
| group-onsemi | 0:098463de4c5d | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| group-onsemi | 0:098463de4c5d | 5 | * copy of this software and associated documentation files (the "Software"), |
| group-onsemi | 0:098463de4c5d | 6 | * to deal in the Software without restriction, including without limitation |
| group-onsemi | 0:098463de4c5d | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| group-onsemi | 0:098463de4c5d | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| group-onsemi | 0:098463de4c5d | 9 | * Software is furnished to do so, subject to the following conditions: |
| group-onsemi | 0:098463de4c5d | 10 | * |
| group-onsemi | 0:098463de4c5d | 11 | * The above copyright notice and this permission notice shall be included |
| group-onsemi | 0:098463de4c5d | 12 | * in all copies or substantial portions of the Software. |
| group-onsemi | 0:098463de4c5d | 13 | * |
| group-onsemi | 0:098463de4c5d | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| group-onsemi | 0:098463de4c5d | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| group-onsemi | 0:098463de4c5d | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| group-onsemi | 0:098463de4c5d | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| group-onsemi | 0:098463de4c5d | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| group-onsemi | 0:098463de4c5d | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| group-onsemi | 0:098463de4c5d | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| group-onsemi | 0:098463de4c5d | 21 | * |
| group-onsemi | 0:098463de4c5d | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| group-onsemi | 0:098463de4c5d | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| group-onsemi | 0:098463de4c5d | 24 | * Products, Inc. Branding Policy. |
| group-onsemi | 0:098463de4c5d | 25 | * |
| group-onsemi | 0:098463de4c5d | 26 | * The mere transfer of this software does not imply any licenses |
| group-onsemi | 0:098463de4c5d | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| group-onsemi | 0:098463de4c5d | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| group-onsemi | 0:098463de4c5d | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| group-onsemi | 0:098463de4c5d | 30 | * ownership rights. |
| group-onsemi | 0:098463de4c5d | 31 | ******************************************************************************* |
| group-onsemi | 0:098463de4c5d | 32 | */ |
| group-onsemi | 0:098463de4c5d | 33 | |
| group-onsemi | 0:098463de4c5d | 34 | #ifndef _MXC_OWM_REGS_H_ |
| group-onsemi | 0:098463de4c5d | 35 | #define _MXC_OWM_REGS_H_ |
| group-onsemi | 0:098463de4c5d | 36 | |
| group-onsemi | 0:098463de4c5d | 37 | #ifdef __cplusplus |
| group-onsemi | 0:098463de4c5d | 38 | extern "C" { |
| group-onsemi | 0:098463de4c5d | 39 | #endif |
| group-onsemi | 0:098463de4c5d | 40 | |
| group-onsemi | 0:098463de4c5d | 41 | #include <stdint.h> |
| group-onsemi | 0:098463de4c5d | 42 | |
| group-onsemi | 0:098463de4c5d | 43 | /* |
| group-onsemi | 0:098463de4c5d | 44 | If types are not defined elsewhere (CMSIS) define them here |
| group-onsemi | 0:098463de4c5d | 45 | */ |
| group-onsemi | 0:098463de4c5d | 46 | #ifndef __IO |
| group-onsemi | 0:098463de4c5d | 47 | #define __IO volatile |
| group-onsemi | 0:098463de4c5d | 48 | #endif |
| group-onsemi | 0:098463de4c5d | 49 | #ifndef __I |
| group-onsemi | 0:098463de4c5d | 50 | #define __I volatile const |
| group-onsemi | 0:098463de4c5d | 51 | #endif |
| group-onsemi | 0:098463de4c5d | 52 | #ifndef __O |
| group-onsemi | 0:098463de4c5d | 53 | #define __O volatile |
| group-onsemi | 0:098463de4c5d | 54 | #endif |
| group-onsemi | 0:098463de4c5d | 55 | |
| group-onsemi | 0:098463de4c5d | 56 | |
| group-onsemi | 0:098463de4c5d | 57 | /* |
| group-onsemi | 0:098463de4c5d | 58 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
| group-onsemi | 0:098463de4c5d | 59 | access to each register in module. |
| group-onsemi | 0:098463de4c5d | 60 | */ |
| group-onsemi | 0:098463de4c5d | 61 | |
| group-onsemi | 0:098463de4c5d | 62 | /* Offset Register Description |
| group-onsemi | 0:098463de4c5d | 63 | ============= ============================================================================ */ |
| group-onsemi | 0:098463de4c5d | 64 | typedef struct { |
| group-onsemi | 0:098463de4c5d | 65 | __IO uint32_t cfg; /* 0x0000 1-Wire Master Configuration */ |
| group-onsemi | 0:098463de4c5d | 66 | __IO uint32_t clk_div_1us; /* 0x0004 1-Wire Master Clock Divisor */ |
| group-onsemi | 0:098463de4c5d | 67 | __IO uint32_t ctrl_stat; /* 0x0008 1-Wire Master Control/Status */ |
| group-onsemi | 0:098463de4c5d | 68 | __IO uint32_t data; /* 0x000C 1-Wire Master Data Buffer */ |
| group-onsemi | 0:098463de4c5d | 69 | __IO uint32_t intfl; /* 0x0010 1-Wire Master Interrupt Flags */ |
| group-onsemi | 0:098463de4c5d | 70 | __IO uint32_t inten; /* 0x0014 1-Wire Master Interrupt Enables */ |
| group-onsemi | 0:098463de4c5d | 71 | } mxc_owm_regs_t; |
| group-onsemi | 0:098463de4c5d | 72 | |
| group-onsemi | 0:098463de4c5d | 73 | |
| group-onsemi | 0:098463de4c5d | 74 | /* |
| group-onsemi | 0:098463de4c5d | 75 | Register offsets for module OWM. |
| group-onsemi | 0:098463de4c5d | 76 | */ |
| group-onsemi | 0:098463de4c5d | 77 | |
| group-onsemi | 0:098463de4c5d | 78 | #define MXC_R_OWM_OFFS_CFG ((uint32_t)0x00000000UL) |
| group-onsemi | 0:098463de4c5d | 79 | #define MXC_R_OWM_OFFS_CLK_DIV_1US ((uint32_t)0x00000004UL) |
| group-onsemi | 0:098463de4c5d | 80 | #define MXC_R_OWM_OFFS_CTRL_STAT ((uint32_t)0x00000008UL) |
| group-onsemi | 0:098463de4c5d | 81 | #define MXC_R_OWM_OFFS_DATA ((uint32_t)0x0000000CUL) |
| group-onsemi | 0:098463de4c5d | 82 | #define MXC_R_OWM_OFFS_INTFL ((uint32_t)0x00000010UL) |
| group-onsemi | 0:098463de4c5d | 83 | #define MXC_R_OWM_OFFS_INTEN ((uint32_t)0x00000014UL) |
| group-onsemi | 0:098463de4c5d | 84 | |
| group-onsemi | 0:098463de4c5d | 85 | |
| group-onsemi | 0:098463de4c5d | 86 | /* |
| group-onsemi | 0:098463de4c5d | 87 | Field positions and masks for module OWM. |
| group-onsemi | 0:098463de4c5d | 88 | */ |
| group-onsemi | 0:098463de4c5d | 89 | |
| group-onsemi | 0:098463de4c5d | 90 | #define MXC_F_OWM_CFG_LONG_LINE_MODE_POS 0 |
| group-onsemi | 0:098463de4c5d | 91 | #define MXC_F_OWM_CFG_LONG_LINE_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_LONG_LINE_MODE_POS)) |
| group-onsemi | 0:098463de4c5d | 92 | #define MXC_F_OWM_CFG_FORCE_PRES_DET_POS 1 |
| group-onsemi | 0:098463de4c5d | 93 | #define MXC_F_OWM_CFG_FORCE_PRES_DET ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_FORCE_PRES_DET_POS)) |
| group-onsemi | 0:098463de4c5d | 94 | #define MXC_F_OWM_CFG_BIT_BANG_EN_POS 2 |
| group-onsemi | 0:098463de4c5d | 95 | #define MXC_F_OWM_CFG_BIT_BANG_EN ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_BIT_BANG_EN_POS)) |
| group-onsemi | 0:098463de4c5d | 96 | #define MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS 3 |
| group-onsemi | 0:098463de4c5d | 97 | #define MXC_F_OWM_CFG_EXT_PULLUP_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS)) |
| group-onsemi | 0:098463de4c5d | 98 | #define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS 4 |
| group-onsemi | 0:098463de4c5d | 99 | #define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS)) |
| group-onsemi | 0:098463de4c5d | 100 | #define MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS 5 |
| group-onsemi | 0:098463de4c5d | 101 | #define MXC_F_OWM_CFG_SINGLE_BIT_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS)) |
| group-onsemi | 0:098463de4c5d | 102 | #define MXC_F_OWM_CFG_OVERDRIVE_POS 6 |
| group-onsemi | 0:098463de4c5d | 103 | #define MXC_F_OWM_CFG_OVERDRIVE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_OVERDRIVE_POS)) |
| group-onsemi | 0:098463de4c5d | 104 | #define MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS 7 |
| group-onsemi | 0:098463de4c5d | 105 | #define MXC_F_OWM_CFG_INT_PULLUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS)) |
| group-onsemi | 0:098463de4c5d | 106 | |
| group-onsemi | 0:098463de4c5d | 107 | #define MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS 0 |
| group-onsemi | 0:098463de4c5d | 108 | #define MXC_F_OWM_CLK_DIV_1US_DIVISOR ((uint32_t)(0x000000FFUL << MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS)) |
| group-onsemi | 0:098463de4c5d | 109 | |
| group-onsemi | 0:098463de4c5d | 110 | #define MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS 0 |
| group-onsemi | 0:098463de4c5d | 111 | #define MXC_F_OWM_CTRL_STAT_START_OW_RESET ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS)) |
| group-onsemi | 0:098463de4c5d | 112 | #define MXC_F_OWM_CTRL_STAT_SRA_MODE_POS 1 |
| group-onsemi | 0:098463de4c5d | 113 | #define MXC_F_OWM_CTRL_STAT_SRA_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_SRA_MODE_POS)) |
| group-onsemi | 0:098463de4c5d | 114 | #define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS 2 |
| group-onsemi | 0:098463de4c5d | 115 | #define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS)) |
| group-onsemi | 0:098463de4c5d | 116 | #define MXC_F_OWM_CTRL_STAT_OW_INPUT_POS 3 |
| group-onsemi | 0:098463de4c5d | 117 | #define MXC_F_OWM_CTRL_STAT_OW_INPUT ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_OW_INPUT_POS)) |
| group-onsemi | 0:098463de4c5d | 118 | #define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS 7 |
| group-onsemi | 0:098463de4c5d | 119 | #define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS)) |
| group-onsemi | 0:098463de4c5d | 120 | |
| group-onsemi | 0:098463de4c5d | 121 | #define MXC_F_OWM_DATA_TX_RX_POS 0 |
| group-onsemi | 0:098463de4c5d | 122 | #define MXC_F_OWM_DATA_TX_RX ((uint32_t)(0x000000FFUL << MXC_F_OWM_DATA_TX_RX_POS)) |
| group-onsemi | 0:098463de4c5d | 123 | |
| group-onsemi | 0:098463de4c5d | 124 | #define MXC_F_OWM_INTFL_OW_RESET_DONE_POS 0 |
| group-onsemi | 0:098463de4c5d | 125 | #define MXC_F_OWM_INTFL_OW_RESET_DONE ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_OW_RESET_DONE_POS)) |
| group-onsemi | 0:098463de4c5d | 126 | #define MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS 1 |
| group-onsemi | 0:098463de4c5d | 127 | #define MXC_F_OWM_INTFL_TX_DATA_EMPTY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS)) |
| group-onsemi | 0:098463de4c5d | 128 | #define MXC_F_OWM_INTFL_RX_DATA_READY_POS 2 |
| group-onsemi | 0:098463de4c5d | 129 | #define MXC_F_OWM_INTFL_RX_DATA_READY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_RX_DATA_READY_POS)) |
| group-onsemi | 0:098463de4c5d | 130 | #define MXC_F_OWM_INTFL_LINE_SHORT_POS 3 |
| group-onsemi | 0:098463de4c5d | 131 | #define MXC_F_OWM_INTFL_LINE_SHORT ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_LINE_SHORT_POS)) |
| group-onsemi | 0:098463de4c5d | 132 | #define MXC_F_OWM_INTFL_LINE_LOW_POS 4 |
| group-onsemi | 0:098463de4c5d | 133 | #define MXC_F_OWM_INTFL_LINE_LOW ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_LINE_LOW_POS)) |
| group-onsemi | 0:098463de4c5d | 134 | |
| group-onsemi | 0:098463de4c5d | 135 | #define MXC_F_OWM_INTEN_OW_RESET_DONE_POS 0 |
| group-onsemi | 0:098463de4c5d | 136 | #define MXC_F_OWM_INTEN_OW_RESET_DONE ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_OW_RESET_DONE_POS)) |
| group-onsemi | 0:098463de4c5d | 137 | #define MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS 1 |
| group-onsemi | 0:098463de4c5d | 138 | #define MXC_F_OWM_INTEN_TX_DATA_EMPTY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS)) |
| group-onsemi | 0:098463de4c5d | 139 | #define MXC_F_OWM_INTEN_RX_DATA_READY_POS 2 |
| group-onsemi | 0:098463de4c5d | 140 | #define MXC_F_OWM_INTEN_RX_DATA_READY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_RX_DATA_READY_POS)) |
| group-onsemi | 0:098463de4c5d | 141 | #define MXC_F_OWM_INTEN_LINE_SHORT_POS 3 |
| group-onsemi | 0:098463de4c5d | 142 | #define MXC_F_OWM_INTEN_LINE_SHORT ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_LINE_SHORT_POS)) |
| group-onsemi | 0:098463de4c5d | 143 | #define MXC_F_OWM_INTEN_LINE_LOW_POS 4 |
| group-onsemi | 0:098463de4c5d | 144 | #define MXC_F_OWM_INTEN_LINE_LOW ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_LINE_LOW_POS)) |
| group-onsemi | 0:098463de4c5d | 145 | |
| group-onsemi | 0:098463de4c5d | 146 | |
| group-onsemi | 0:098463de4c5d | 147 | |
| group-onsemi | 0:098463de4c5d | 148 | #ifdef __cplusplus |
| group-onsemi | 0:098463de4c5d | 149 | } |
| group-onsemi | 0:098463de4c5d | 150 | #endif |
| group-onsemi | 0:098463de4c5d | 151 | |
| group-onsemi | 0:098463de4c5d | 152 | #endif /* _MXC_OWM_REGS_H_ */ |
| group-onsemi | 0:098463de4c5d | 153 |