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targets/TARGET_Maxim/TARGET_MAX32610/device/afe_regs.h@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #ifndef _MXC_AFE_REGS_H
group-onsemi 0:098463de4c5d 35 #define _MXC_AFE_REGS_H
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 38 extern "C" {
group-onsemi 0:098463de4c5d 39 #endif
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 #include <stdint.h>
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 /**
group-onsemi 0:098463de4c5d 44 * @file afe_regs.h
group-onsemi 0:098463de4c5d 45 * @addtogroup afe AFE
group-onsemi 0:098463de4c5d 46 * @{
group-onsemi 0:098463de4c5d 47 */
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49 /**
group-onsemi 0:098463de4c5d 50 * @brief Defines Configure Options for the LED Ports.
group-onsemi 0:098463de4c5d 51 */
group-onsemi 0:098463de4c5d 52 typedef enum {
group-onsemi 0:098463de4c5d 53 /** LED Sink Port 0 with OpAmp A, LED Sink Port 1 with OpAmp C */
group-onsemi 0:098463de4c5d 54 MXC_E_AFE_LED_CFG_PORT_OPAMP_A_C = 0,
group-onsemi 0:098463de4c5d 55 /** LED Sink Port 0 with OpAmp B, LED Sink Port 1 with OpAmp D */
group-onsemi 0:098463de4c5d 56 MXC_E_AFE_LED_CFG_PORT_OPAMP_B_D,
group-onsemi 0:098463de4c5d 57 /** Disable LED Sink Port 0,Disable LED Sink Port 1 */
group-onsemi 0:098463de4c5d 58 MXC_E_AFE_LED_CFG_PORT_DISABLED,
group-onsemi 0:098463de4c5d 59 } mxc_afe_led_cfg_port_t;
group-onsemi 0:098463de4c5d 60
group-onsemi 0:098463de4c5d 61 /**
group-onsemi 0:098463de4c5d 62 * @brief Setup of Wake Up Detector for LPCs.
group-onsemi 0:098463de4c5d 63 */
group-onsemi 0:098463de4c5d 64 typedef enum {
group-onsemi 0:098463de4c5d 65 /** IDLE */
group-onsemi 0:098463de4c5d 66 MXC_E_AFE_EN_WUD_COMP_IDLE = 0,
group-onsemi 0:098463de4c5d 67 /** Activate WUD for falling edges */
group-onsemi 0:098463de4c5d 68 MXC_E_AFE_EN_WUD_COMP_FALLING_EDGE = 2,
group-onsemi 0:098463de4c5d 69 /** Activate WUD for rising edges */
group-onsemi 0:098463de4c5d 70 MXC_E_AFE_EN_WUD_COMP_RISING_EDGE = 3
group-onsemi 0:098463de4c5d 71 } mxc_afe_en_wud_comp_t;
group-onsemi 0:098463de4c5d 72
group-onsemi 0:098463de4c5d 73 /**
group-onsemi 0:098463de4c5d 74 * @brief LPC InMode.
group-onsemi 0:098463de4c5d 75 */
group-onsemi 0:098463de4c5d 76 typedef enum {
group-onsemi 0:098463de4c5d 77 /** InMode: both Nch and Pch */
group-onsemi 0:098463de4c5d 78 MXC_E_AFE_IN_MODE_COMP_NCH_PCH = 0,
group-onsemi 0:098463de4c5d 79 /** InMode: only Nch */
group-onsemi 0:098463de4c5d 80 MXC_E_AFE_IN_MODE_COMP_NCH,
group-onsemi 0:098463de4c5d 81 /** InMode: only Pch */
group-onsemi 0:098463de4c5d 82 MXC_E_AFE_IN_MODE_COMP_PCH,
group-onsemi 0:098463de4c5d 83 } mxc_afe_in_mode_comp_t;
group-onsemi 0:098463de4c5d 84
group-onsemi 0:098463de4c5d 85 /**
group-onsemi 0:098463de4c5d 86 * @brief LPC Bias.
group-onsemi 0:098463de4c5d 87 */
group-onsemi 0:098463de4c5d 88 typedef enum {
group-onsemi 0:098463de4c5d 89 /** BIAS 0.52uA Delay 4.0us */
group-onsemi 0:098463de4c5d 90 MXC_E_AFE_BIAS_MODE_COMP_0 = 0,
group-onsemi 0:098463de4c5d 91 /** BIAS 1.4uA Delay 1.7us */
group-onsemi 0:098463de4c5d 92 MXC_E_AFE_BIAS_MODE_COMP_1,
group-onsemi 0:098463de4c5d 93 /** BIAS 2.8uA Delay 1.1us */
group-onsemi 0:098463de4c5d 94 MXC_E_AFE_BIAS_MODE_COMP_2,
group-onsemi 0:098463de4c5d 95 /** BIAS 5.1uA Delay 0.7us */
group-onsemi 0:098463de4c5d 96 MXC_E_AFE_BIAS_MODE_COMP_3
group-onsemi 0:098463de4c5d 97 } mxc_afe_bias_mode_comp_t;
group-onsemi 0:098463de4c5d 98
group-onsemi 0:098463de4c5d 99 /**
group-onsemi 0:098463de4c5d 100 * @brief TMON Current Value.
group-onsemi 0:098463de4c5d 101 */
group-onsemi 0:098463de4c5d 102 typedef enum {
group-onsemi 0:098463de4c5d 103 /** TMON Current 4uA */
group-onsemi 0:098463de4c5d 104 MXC_E_AFE_TMON_CURRENT_VAL_0 = 0,
group-onsemi 0:098463de4c5d 105 /** TMON Current 60uA */
group-onsemi 0:098463de4c5d 106 MXC_E_AFE_TMON_CURRENT_VAL_1,
group-onsemi 0:098463de4c5d 107 /** TMON Current 64uA */
group-onsemi 0:098463de4c5d 108 MXC_E_AFE_TMON_CURRENT_VAL_2,
group-onsemi 0:098463de4c5d 109 /** TMON Current 120uA */
group-onsemi 0:098463de4c5d 110 MXC_E_AFE_TMON_CURRENT_VAL_3
group-onsemi 0:098463de4c5d 111 } mxc_afe_tmon_current_t;
group-onsemi 0:098463de4c5d 112
group-onsemi 0:098463de4c5d 113 /**
group-onsemi 0:098463de4c5d 114 * @brief REFADC and REFDAC Voltage Select.
group-onsemi 0:098463de4c5d 115 */
group-onsemi 0:098463de4c5d 116 typedef enum {
group-onsemi 0:098463de4c5d 117 /** Voltage Reference = 1.024 V */
group-onsemi 0:098463de4c5d 118 MXC_E_AFE_REF_VOLT_SEL_1024 = 0,
group-onsemi 0:098463de4c5d 119 /** Voltage Reference = 1.5 V */
group-onsemi 0:098463de4c5d 120 MXC_E_AFE_REF_VOLT_SEL_1500,
group-onsemi 0:098463de4c5d 121 /** Voltage Reference = 2.048 V */
group-onsemi 0:098463de4c5d 122 MXC_E_AFE_REF_VOLT_SEL_2048,
group-onsemi 0:098463de4c5d 123 /** Voltage Reference = 2.5 V */
group-onsemi 0:098463de4c5d 124 MXC_E_AFE_REF_VOLT_SEL_2500
group-onsemi 0:098463de4c5d 125 } mxc_afe_ref_volt_sel_t;
group-onsemi 0:098463de4c5d 126
group-onsemi 0:098463de4c5d 127 /**
group-onsemi 0:098463de4c5d 128 * @brief Selection for DAC VOltage Reference, REFADC or REFDAC.
group-onsemi 0:098463de4c5d 129 */
group-onsemi 0:098463de4c5d 130 typedef enum {
group-onsemi 0:098463de4c5d 131 /** DAC Voltage Reference = REFADC */
group-onsemi 0:098463de4c5d 132 MXC_E_AFE_DAC_REF_REFADC = 0,
group-onsemi 0:098463de4c5d 133 /** DAC Voltage Reference = REFDAC */
group-onsemi 0:098463de4c5d 134 MXC_E_AFE_DAC_REF_REFDAC
group-onsemi 0:098463de4c5d 135 } mxc_afe_dac_ref_t;
group-onsemi 0:098463de4c5d 136
group-onsemi 0:098463de4c5d 137 /**
group-onsemi 0:098463de4c5d 138 * @brief Selection for LPC Hysteresis.
group-onsemi 0:098463de4c5d 139 */
group-onsemi 0:098463de4c5d 140 typedef enum {
group-onsemi 0:098463de4c5d 141 /** LPC Hysteresis = 0 mV */
group-onsemi 0:098463de4c5d 142 MXC_E_AFE_HYST_COMP_0 = 0,
group-onsemi 0:098463de4c5d 143 /** LPC Hysteresis = 7.5 mV */
group-onsemi 0:098463de4c5d 144 MXC_E_AFE_HYST_COMP_1,
group-onsemi 0:098463de4c5d 145 /** LPC Hysteresis = 15 mV */
group-onsemi 0:098463de4c5d 146 MXC_E_AFE_HYST_COMP_2,
group-onsemi 0:098463de4c5d 147 /** LPC Hysteresis = 30 mV */
group-onsemi 0:098463de4c5d 148 MXC_E_AFE_HYST_COMP_3
group-onsemi 0:098463de4c5d 149 } mxc_afe_hyst_comp_t;
group-onsemi 0:098463de4c5d 150
group-onsemi 0:098463de4c5d 151 /**
group-onsemi 0:098463de4c5d 152 * @brief Selection for MUX for SCM_or_sel.
group-onsemi 0:098463de4c5d 153 */
group-onsemi 0:098463de4c5d 154 typedef enum {
group-onsemi 0:098463de4c5d 155 /** SCM_or = HIZ */
group-onsemi 0:098463de4c5d 156 MXC_E_AFE_SCM_OR_SEL_HIZ = 0,
group-onsemi 0:098463de4c5d 157 /** SCM_or = SCM0 */
group-onsemi 0:098463de4c5d 158 MXC_E_AFE_SCM_OR_SEL_SCM0,
group-onsemi 0:098463de4c5d 159 /** SCM_or = SCM1 */
group-onsemi 0:098463de4c5d 160 MXC_E_AFE_SCM_OR_SEL_SCM1,
group-onsemi 0:098463de4c5d 161 /** SCM_or = SCM2 */
group-onsemi 0:098463de4c5d 162 MXC_E_AFE_SCM_OR_SEL_SCM2,
group-onsemi 0:098463de4c5d 163 /** SCM_or = SCM3 */
group-onsemi 0:098463de4c5d 164 MXC_E_AFE_SCM_OR_SEL_SCM3
group-onsemi 0:098463de4c5d 165 } mxc_afe_scm_or_sel_t;
group-onsemi 0:098463de4c5d 166
group-onsemi 0:098463de4c5d 167 /**
group-onsemi 0:098463de4c5d 168 * @brief Selection for MUX for SNO_or_sel.
group-onsemi 0:098463de4c5d 169 */
group-onsemi 0:098463de4c5d 170 typedef enum {
group-onsemi 0:098463de4c5d 171 /** SNO_or = HIZ */
group-onsemi 0:098463de4c5d 172 MXC_E_AFE_SNO_OR_SEL_HIZ = 0,
group-onsemi 0:098463de4c5d 173 /** SNO_or = SNO0 */
group-onsemi 0:098463de4c5d 174 MXC_E_AFE_SNO_OR_SEL_SNO0,
group-onsemi 0:098463de4c5d 175 /** SNO_or = SNO1 */
group-onsemi 0:098463de4c5d 176 MXC_E_AFE_SNO_OR_SEL_SNO1,
group-onsemi 0:098463de4c5d 177 /** SNO_or = SNO2 */
group-onsemi 0:098463de4c5d 178 MXC_E_AFE_SNO_OR_SEL_SNO2,
group-onsemi 0:098463de4c5d 179 /** SNO_or = SNO3 */
group-onsemi 0:098463de4c5d 180 MXC_E_AFE_SNO_OR_SEL_SNO3
group-onsemi 0:098463de4c5d 181 } mxc_afe_sno_or_sel_t;
group-onsemi 0:098463de4c5d 182
group-onsemi 0:098463de4c5d 183 /**
group-onsemi 0:098463de4c5d 184 * @brief Selection for MUX DACx_sel.
group-onsemi 0:098463de4c5d 185 */
group-onsemi 0:098463de4c5d 186 typedef enum {
group-onsemi 0:098463de4c5d 187 /** dacx = DACOP */
group-onsemi 0:098463de4c5d 188 MXC_E_AFE_DACX_SEL_P = 0,
group-onsemi 0:098463de4c5d 189 /** dacx = DACON */
group-onsemi 0:098463de4c5d 190 MXC_E_AFE_DACX_SEL_N
group-onsemi 0:098463de4c5d 191 } mxc_afe_dacx_sel_t;
group-onsemi 0:098463de4c5d 192
group-onsemi 0:098463de4c5d 193 /**
group-onsemi 0:098463de4c5d 194 * @brief Selection for state of Switch.
group-onsemi 0:098463de4c5d 195 */
group-onsemi 0:098463de4c5d 196 typedef enum {
group-onsemi 0:098463de4c5d 197 /** Switch is OPEN */
group-onsemi 0:098463de4c5d 198 MXC_E_AFE_CLOSE_SPST_SWITCH_OPEN = 0,
group-onsemi 0:098463de4c5d 199 /** Switch is CLOSED */
group-onsemi 0:098463de4c5d 200 MXC_E_AFE_CLOSE_SPST_SWITCH_CLOSE
group-onsemi 0:098463de4c5d 201 } mxc_afe_close_spst_t;
group-onsemi 0:098463de4c5d 202
group-onsemi 0:098463de4c5d 203 /**
group-onsemi 0:098463de4c5d 204 * @brief Switch to Connect Positive Pad to GND.
group-onsemi 0:098463de4c5d 205 */
group-onsemi 0:098463de4c5d 206 typedef enum {
group-onsemi 0:098463de4c5d 207 /** Positive Pad GND Switch OPEN */
group-onsemi 0:098463de4c5d 208 MXC_E_AFE_GND_SEL_OPAMP_SWITCH_OPEN = 0,
group-onsemi 0:098463de4c5d 209 /** Positive Pad GND Switch CLOSED */
group-onsemi 0:098463de4c5d 210 MXC_E_AFE_GND_SEL_OPAMP_SWITCH_CLOSED
group-onsemi 0:098463de4c5d 211 } mxc_afe_gnd_sel_opamp_t;
group-onsemi 0:098463de4c5d 212
group-onsemi 0:098463de4c5d 213 /**
group-onsemi 0:098463de4c5d 214 * @brief MUX Selection for OpPsel.
group-onsemi 0:098463de4c5d 215 */
group-onsemi 0:098463de4c5d 216 typedef enum {
group-onsemi 0:098463de4c5d 217 /** OpPsel = INx+ */
group-onsemi 0:098463de4c5d 218 MXC_E_AFE_P_IN_SEL_OPAMP_INPLUS = 0,
group-onsemi 0:098463de4c5d 219 /** OpPsel = DAC_or */
group-onsemi 0:098463de4c5d 220 MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR,
group-onsemi 0:098463de4c5d 221 /** OpPsel = SNO_or */
group-onsemi 0:098463de4c5d 222 MXC_E_AFE_P_IN_SEL_OPAMP_SNO_OR,
group-onsemi 0:098463de4c5d 223 /** OpPsel = DAC_or also output on INx+ */
group-onsemi 0:098463de4c5d 224 MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR_AND_INPLUS
group-onsemi 0:098463de4c5d 225 } mxc_afe_p_in_sel_opamp_t;
group-onsemi 0:098463de4c5d 226
group-onsemi 0:098463de4c5d 227 /**
group-onsemi 0:098463de4c5d 228 * @brief MUX Selection for OpNsel.
group-onsemi 0:098463de4c5d 229 */
group-onsemi 0:098463de4c5d 230 typedef enum {
group-onsemi 0:098463de4c5d 231 /** OpNsel = INx- */
group-onsemi 0:098463de4c5d 232 MXC_E_AFE_N_IN_SEL_OPAMP_INMINUS = 0,
group-onsemi 0:098463de4c5d 233 /** OpNsel = OUTx */
group-onsemi 0:098463de4c5d 234 MXC_E_AFE_N_IN_SEL_OPAMP_OUT,
group-onsemi 0:098463de4c5d 235 /** OpNsel = SCM_or */
group-onsemi 0:098463de4c5d 236 MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR,
group-onsemi 0:098463de4c5d 237 /**OpNsel = SCM_or also output on INx- */
group-onsemi 0:098463de4c5d 238 MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR_AND_INMINUS,
group-onsemi 0:098463de4c5d 239 } mxc_afe_n_in_sel_opamp_t;
group-onsemi 0:098463de4c5d 240
group-onsemi 0:098463de4c5d 241 /**
group-onsemi 0:098463de4c5d 242 * @brief MUX Selection for DAC_sel.
group-onsemi 0:098463de4c5d 243 */
group-onsemi 0:098463de4c5d 244 typedef enum {
group-onsemi 0:098463de4c5d 245 /** DAC_or = DAC0 */
group-onsemi 0:098463de4c5d 246 MXC_E_AFE_DAC_SEL_DAC0 = 0,
group-onsemi 0:098463de4c5d 247 /** DAC_or = DAC1 */
group-onsemi 0:098463de4c5d 248 MXC_E_AFE_DAC_SEL_DAC1,
group-onsemi 0:098463de4c5d 249 /** DAC_or = DAC2P */
group-onsemi 0:098463de4c5d 250 MXC_E_AFE_DAC_SEL_DAC2P,
group-onsemi 0:098463de4c5d 251 /** DAC_or = DAC3P */
group-onsemi 0:098463de4c5d 252 MXC_E_AFE_DAC_SEL_DAC3P
group-onsemi 0:098463de4c5d 253 } mxc_afe_dac_sel_t;
group-onsemi 0:098463de4c5d 254
group-onsemi 0:098463de4c5d 255 /**
group-onsemi 0:098463de4c5d 256 * @brief MUX Selection for NPAD_sel.
group-onsemi 0:098463de4c5d 257 */
group-onsemi 0:098463de4c5d 258 typedef enum {
group-onsemi 0:098463de4c5d 259 /** NPAD_Sel = HIZ */
group-onsemi 0:098463de4c5d 260 MXC_E_AFE_NPAD_SEL_HIZ = 0,
group-onsemi 0:098463de4c5d 261 /** NPAD_Sel = LED Observe Port */
group-onsemi 0:098463de4c5d 262 MXC_E_AFE_NPAD_SEL_LED_OBS_PORT,
group-onsemi 0:098463de4c5d 263 /** NPAD_Sel = DAC_or */
group-onsemi 0:098463de4c5d 264 MXC_E_AFE_NPAD_SEL_DAC_OR,
group-onsemi 0:098463de4c5d 265 /** NPAD_Sel = DAC_or and LED Observe Port */
group-onsemi 0:098463de4c5d 266 MXC_E_AFE_NPAD_SEL_DAC_OR_AND_LED_OBS_PORT
group-onsemi 0:098463de4c5d 267 } mxc_afe_npad_sel_t;
group-onsemi 0:098463de4c5d 268
group-onsemi 0:098463de4c5d 269 /**
group-onsemi 0:098463de4c5d 270 * @brief MUX Selection for CmpPSel.
group-onsemi 0:098463de4c5d 271 */
group-onsemi 0:098463de4c5d 272 typedef enum {
group-onsemi 0:098463de4c5d 273 /** CmpPSel = INx+ */
group-onsemi 0:098463de4c5d 274 MXC_E_AFE_POS_IN_SEL_COMP_INPLUS = 0,
group-onsemi 0:098463de4c5d 275 /** CmpPSel = SCM */
group-onsemi 0:098463de4c5d 276 MXC_E_AFE_POS_IN_SEL_COMP_SCM,
group-onsemi 0:098463de4c5d 277 /** CmpPSel = dac1 */
group-onsemi 0:098463de4c5d 278 MXC_E_AFE_POS_IN_SEL_COMP_DAC1,
group-onsemi 0:098463de4c5d 279 /** CmpPSel = DAC3P */
group-onsemi 0:098463de4c5d 280 MXC_E_AFE_POS_IN_SEL_COMP_DAC3P,
group-onsemi 0:098463de4c5d 281 /** CmpPSel = LED Observe Port */
group-onsemi 0:098463de4c5d 282 MXC_E_AFE_POS_IN_SEL_COMP_LED_OBS_PORT,
group-onsemi 0:098463de4c5d 283 /** CmpPSel = dac1 also output on INx+ */
group-onsemi 0:098463de4c5d 284 MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_INPLUS,
group-onsemi 0:098463de4c5d 285 /** CmpPSel = DAC3P also output on INx+ */
group-onsemi 0:098463de4c5d 286 MXC_E_AFE_POS_IN_SEL_COMP_DAC3P_AND_INPLUS,
group-onsemi 0:098463de4c5d 287 /** CmpPSel = dac1 also output on SCM */
group-onsemi 0:098463de4c5d 288 MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_SCM
group-onsemi 0:098463de4c5d 289 } mxc_afe_pos_in_sel_comp_t;
group-onsemi 0:098463de4c5d 290
group-onsemi 0:098463de4c5d 291 /**
group-onsemi 0:098463de4c5d 292 * @brief MUX Selection for CmpNSel.
group-onsemi 0:098463de4c5d 293 */
group-onsemi 0:098463de4c5d 294 typedef enum {
group-onsemi 0:098463de4c5d 295 /** CmpNSel = INx- */
group-onsemi 0:098463de4c5d 296 MXC_E_AFE_NEG_IN_SEL_COMP_INMINUS = 0,
group-onsemi 0:098463de4c5d 297 /** CmpNSel = SNO */
group-onsemi 0:098463de4c5d 298 MXC_E_AFE_NEG_IN_SEL_COMP_SNO,
group-onsemi 0:098463de4c5d 299 /** CmpNSel = dac0 */
group-onsemi 0:098463de4c5d 300 MXC_E_AFE_NEG_IN_SEL_COMP_DAC0,
group-onsemi 0:098463de4c5d 301 /** CmpNSel = DAC2P */
group-onsemi 0:098463de4c5d 302 MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P,
group-onsemi 0:098463de4c5d 303 /** CmpNSel = LED Observation Port */
group-onsemi 0:098463de4c5d 304 MXC_E_AFE_NEG_IN_SEL_COMP_LED_OBS_PORT,
group-onsemi 0:098463de4c5d 305 /** CmpNSel = dac0 also output on INx- */
group-onsemi 0:098463de4c5d 306 MXC_E_AFE_NEG_IN_SEL_COMP_DAC0_AND_INMINUS,
group-onsemi 0:098463de4c5d 307 /** CmpNSel = DAC2 also output on INx- */
group-onsemi 0:098463de4c5d 308 MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_INMINUS,
group-onsemi 0:098463de4c5d 309 /** CmpNSel = DAC2 also output on SNO */
group-onsemi 0:098463de4c5d 310 MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_SNO
group-onsemi 0:098463de4c5d 311 } mxc_afe_neg_in_sel_comp_t;
group-onsemi 0:098463de4c5d 312
group-onsemi 0:098463de4c5d 313 /* Offset Register Description
group-onsemi 0:098463de4c5d 314 ====== ==================================================== */
group-onsemi 0:098463de4c5d 315 typedef struct {
group-onsemi 0:098463de4c5d 316 __IO uint32_t intr; /* 0x0000 Analog Front End Interrupt Flags and Enable/Disable */
group-onsemi 0:098463de4c5d 317 __IO uint32_t ctrl0; /* 0x0004 Analog Front End Control 0 */
group-onsemi 0:098463de4c5d 318 __IO uint32_t ctrl1; /* 0x0008 Analog Front End Control 1 */
group-onsemi 0:098463de4c5d 319 __IO uint32_t ctrl2; /* 0x000C Analog Front End Control 2 */
group-onsemi 0:098463de4c5d 320 __IO uint32_t ctrl3; /* 0x0010 Analog Front End Control 3 */
group-onsemi 0:098463de4c5d 321 __IO uint32_t ctrl4; /* 0x0014 Analog Front End Control 4 */
group-onsemi 0:098463de4c5d 322 __IO uint32_t ctrl5; /* 0x0018 Analog Front End Control 5 */
group-onsemi 0:098463de4c5d 323 } mxc_afe_regs_t;
group-onsemi 0:098463de4c5d 324
group-onsemi 0:098463de4c5d 325 /*
group-onsemi 0:098463de4c5d 326 Register offsets for module AFE.
group-onsemi 0:098463de4c5d 327 */
group-onsemi 0:098463de4c5d 328 #define MXC_R_AFE_OFFS_INTR ((uint32_t)0x00000000UL)
group-onsemi 0:098463de4c5d 329 #define MXC_R_AFE_OFFS_CTRL0 ((uint32_t)0x00000004UL)
group-onsemi 0:098463de4c5d 330 #define MXC_R_AFE_OFFS_CTRL1 ((uint32_t)0x00000008UL)
group-onsemi 0:098463de4c5d 331 #define MXC_R_AFE_OFFS_CTRL2 ((uint32_t)0x0000000CUL)
group-onsemi 0:098463de4c5d 332 #define MXC_R_AFE_OFFS_CTRL3 ((uint32_t)0x00000010UL)
group-onsemi 0:098463de4c5d 333 #define MXC_R_AFE_OFFS_CTRL4 ((uint32_t)0x00000014UL)
group-onsemi 0:098463de4c5d 334 #define MXC_R_AFE_OFFS_CTRL5 ((uint32_t)0x00000018UL)
group-onsemi 0:098463de4c5d 335
group-onsemi 0:098463de4c5d 336 /*
group-onsemi 0:098463de4c5d 337 Field positions and masks for module AFE.
group-onsemi 0:098463de4c5d 338 */
group-onsemi 0:098463de4c5d 339 #define MXC_F_AFE_INTR_OP_COMP0_IF_POS 0
group-onsemi 0:098463de4c5d 340 #define MXC_F_AFE_INTR_OP_COMP0_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IF_POS))
group-onsemi 0:098463de4c5d 341 #define MXC_F_AFE_INTR_OP_COMP1_IF_POS 1
group-onsemi 0:098463de4c5d 342 #define MXC_F_AFE_INTR_OP_COMP1_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IF_POS))
group-onsemi 0:098463de4c5d 343 #define MXC_F_AFE_INTR_OP_COMP2_IF_POS 2
group-onsemi 0:098463de4c5d 344 #define MXC_F_AFE_INTR_OP_COMP2_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IF_POS))
group-onsemi 0:098463de4c5d 345 #define MXC_F_AFE_INTR_OP_COMP3_IF_POS 3
group-onsemi 0:098463de4c5d 346 #define MXC_F_AFE_INTR_OP_COMP3_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IF_POS))
group-onsemi 0:098463de4c5d 347 #define MXC_F_AFE_INTR_LP_COMP0_IF_POS 4
group-onsemi 0:098463de4c5d 348 #define MXC_F_AFE_INTR_LP_COMP0_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IF_POS))
group-onsemi 0:098463de4c5d 349 #define MXC_F_AFE_INTR_LP_COMP1_IF_POS 5
group-onsemi 0:098463de4c5d 350 #define MXC_F_AFE_INTR_LP_COMP1_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IF_POS))
group-onsemi 0:098463de4c5d 351 #define MXC_F_AFE_INTR_LP_COMP2_IF_POS 6
group-onsemi 0:098463de4c5d 352 #define MXC_F_AFE_INTR_LP_COMP2_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IF_POS))
group-onsemi 0:098463de4c5d 353 #define MXC_F_AFE_INTR_LP_COMP3_IF_POS 7
group-onsemi 0:098463de4c5d 354 #define MXC_F_AFE_INTR_LP_COMP3_IF ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IF_POS))
group-onsemi 0:098463de4c5d 355 #define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS 8
group-onsemi 0:098463de4c5d 356 #define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS))
group-onsemi 0:098463de4c5d 357 #define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS 9
group-onsemi 0:098463de4c5d 358 #define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS))
group-onsemi 0:098463de4c5d 359 #define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS 10
group-onsemi 0:098463de4c5d 360 #define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS))
group-onsemi 0:098463de4c5d 361 #define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS 11
group-onsemi 0:098463de4c5d 362 #define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS))
group-onsemi 0:098463de4c5d 363 #define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS 12
group-onsemi 0:098463de4c5d 364 #define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS))
group-onsemi 0:098463de4c5d 365 #define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS 13
group-onsemi 0:098463de4c5d 366 #define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS))
group-onsemi 0:098463de4c5d 367 #define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS 14
group-onsemi 0:098463de4c5d 368 #define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS))
group-onsemi 0:098463de4c5d 369 #define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS 15
group-onsemi 0:098463de4c5d 370 #define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS))
group-onsemi 0:098463de4c5d 371 #define MXC_F_AFE_INTR_OP_COMP0_POL_POS 16
group-onsemi 0:098463de4c5d 372 #define MXC_F_AFE_INTR_OP_COMP0_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_POL_POS))
group-onsemi 0:098463de4c5d 373 #define MXC_F_AFE_INTR_OP_COMP1_POL_POS 17
group-onsemi 0:098463de4c5d 374 #define MXC_F_AFE_INTR_OP_COMP1_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_POL_POS))
group-onsemi 0:098463de4c5d 375 #define MXC_F_AFE_INTR_OP_COMP2_POL_POS 18
group-onsemi 0:098463de4c5d 376 #define MXC_F_AFE_INTR_OP_COMP2_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_POL_POS))
group-onsemi 0:098463de4c5d 377 #define MXC_F_AFE_INTR_OP_COMP3_POL_POS 19
group-onsemi 0:098463de4c5d 378 #define MXC_F_AFE_INTR_OP_COMP3_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_POL_POS))
group-onsemi 0:098463de4c5d 379 #define MXC_F_AFE_INTR_LP_COMP0_POL_POS 20
group-onsemi 0:098463de4c5d 380 #define MXC_F_AFE_INTR_LP_COMP0_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_POL_POS))
group-onsemi 0:098463de4c5d 381 #define MXC_F_AFE_INTR_LP_COMP1_POL_POS 21
group-onsemi 0:098463de4c5d 382 #define MXC_F_AFE_INTR_LP_COMP1_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_POL_POS))
group-onsemi 0:098463de4c5d 383 #define MXC_F_AFE_INTR_LP_COMP2_POL_POS 22
group-onsemi 0:098463de4c5d 384 #define MXC_F_AFE_INTR_LP_COMP2_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_POL_POS))
group-onsemi 0:098463de4c5d 385 #define MXC_F_AFE_INTR_LP_COMP3_POL_POS 23
group-onsemi 0:098463de4c5d 386 #define MXC_F_AFE_INTR_LP_COMP3_POL ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_POL_POS))
group-onsemi 0:098463de4c5d 387 #define MXC_F_AFE_INTR_OP_COMP0_IE_POS 24
group-onsemi 0:098463de4c5d 388 #define MXC_F_AFE_INTR_OP_COMP0_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IE_POS))
group-onsemi 0:098463de4c5d 389 #define MXC_F_AFE_INTR_OP_COMP1_IE_POS 25
group-onsemi 0:098463de4c5d 390 #define MXC_F_AFE_INTR_OP_COMP1_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IE_POS))
group-onsemi 0:098463de4c5d 391 #define MXC_F_AFE_INTR_OP_COMP2_IE_POS 26
group-onsemi 0:098463de4c5d 392 #define MXC_F_AFE_INTR_OP_COMP2_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IE_POS))
group-onsemi 0:098463de4c5d 393 #define MXC_F_AFE_INTR_OP_COMP3_IE_POS 27
group-onsemi 0:098463de4c5d 394 #define MXC_F_AFE_INTR_OP_COMP3_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IE_POS))
group-onsemi 0:098463de4c5d 395 #define MXC_F_AFE_INTR_LP_COMP0_IE_POS 28
group-onsemi 0:098463de4c5d 396 #define MXC_F_AFE_INTR_LP_COMP0_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IE_POS))
group-onsemi 0:098463de4c5d 397 #define MXC_F_AFE_INTR_LP_COMP1_IE_POS 29
group-onsemi 0:098463de4c5d 398 #define MXC_F_AFE_INTR_LP_COMP1_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IE_POS))
group-onsemi 0:098463de4c5d 399 #define MXC_F_AFE_INTR_LP_COMP2_IE_POS 30
group-onsemi 0:098463de4c5d 400 #define MXC_F_AFE_INTR_LP_COMP2_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IE_POS))
group-onsemi 0:098463de4c5d 401 #define MXC_F_AFE_INTR_LP_COMP3_IE_POS 31
group-onsemi 0:098463de4c5d 402 #define MXC_F_AFE_INTR_LP_COMP3_IE ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IE_POS))
group-onsemi 0:098463de4c5d 403
group-onsemi 0:098463de4c5d 404 #define MXC_F_AFE_CTRL0_LED_CFG_POS 0
group-onsemi 0:098463de4c5d 405 #define MXC_F_AFE_CTRL0_LED_CFG ((uint32_t)(0x0000000FUL << MXC_F_AFE_CTRL0_LED_CFG_POS))
group-onsemi 0:098463de4c5d 406 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS 4
group-onsemi 0:098463de4c5d 407 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS))
group-onsemi 0:098463de4c5d 408 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS 5
group-onsemi 0:098463de4c5d 409 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS))
group-onsemi 0:098463de4c5d 410 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS 6
group-onsemi 0:098463de4c5d 411 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS))
group-onsemi 0:098463de4c5d 412 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS 7
group-onsemi 0:098463de4c5d 413 #define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS))
group-onsemi 0:098463de4c5d 414 #define MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS 8
group-onsemi 0:098463de4c5d 415 #define MXC_F_AFE_CTRL0_EN_WUD_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS))
group-onsemi 0:098463de4c5d 416 #define MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS 10
group-onsemi 0:098463de4c5d 417 #define MXC_F_AFE_CTRL0_EN_WUD_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS))
group-onsemi 0:098463de4c5d 418 #define MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS 12
group-onsemi 0:098463de4c5d 419 #define MXC_F_AFE_CTRL0_EN_WUD_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS))
group-onsemi 0:098463de4c5d 420 #define MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS 14
group-onsemi 0:098463de4c5d 421 #define MXC_F_AFE_CTRL0_EN_WUD_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS))
group-onsemi 0:098463de4c5d 422 #define MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS 16
group-onsemi 0:098463de4c5d 423 #define MXC_F_AFE_CTRL0_IN_MODE_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS))
group-onsemi 0:098463de4c5d 424 #define MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS 18
group-onsemi 0:098463de4c5d 425 #define MXC_F_AFE_CTRL0_IN_MODE_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS))
group-onsemi 0:098463de4c5d 426 #define MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS 20
group-onsemi 0:098463de4c5d 427 #define MXC_F_AFE_CTRL0_IN_MODE_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS))
group-onsemi 0:098463de4c5d 428 #define MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS 22
group-onsemi 0:098463de4c5d 429 #define MXC_F_AFE_CTRL0_IN_MODE_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS))
group-onsemi 0:098463de4c5d 430 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS 24
group-onsemi 0:098463de4c5d 431 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS))
group-onsemi 0:098463de4c5d 432 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS 26
group-onsemi 0:098463de4c5d 433 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS))
group-onsemi 0:098463de4c5d 434 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS 28
group-onsemi 0:098463de4c5d 435 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS))
group-onsemi 0:098463de4c5d 436 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS 30
group-onsemi 0:098463de4c5d 437 #define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS))
group-onsemi 0:098463de4c5d 438
group-onsemi 0:098463de4c5d 439 #define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS 0
group-onsemi 0:098463de4c5d 440 #define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS))
group-onsemi 0:098463de4c5d 441 #define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS 1
group-onsemi 0:098463de4c5d 442 #define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS))
group-onsemi 0:098463de4c5d 443 #define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS 3
group-onsemi 0:098463de4c5d 444 #define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS))
group-onsemi 0:098463de4c5d 445 #define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS 4
group-onsemi 0:098463de4c5d 446 #define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS))
group-onsemi 0:098463de4c5d 447 #define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS 5
group-onsemi 0:098463de4c5d 448 #define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS))
group-onsemi 0:098463de4c5d 449 #define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS 6
group-onsemi 0:098463de4c5d 450 #define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS))
group-onsemi 0:098463de4c5d 451 #define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS 8
group-onsemi 0:098463de4c5d 452 #define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS))
group-onsemi 0:098463de4c5d 453 #define MXC_F_AFE_CTRL1_REF_SEL_POS 10
group-onsemi 0:098463de4c5d 454 #define MXC_F_AFE_CTRL1_REF_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_SEL_POS))
group-onsemi 0:098463de4c5d 455 #define MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS 11
group-onsemi 0:098463de4c5d 456 #define MXC_F_AFE_CTRL1_REF_ADC_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS))
group-onsemi 0:098463de4c5d 457 #define MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS 12
group-onsemi 0:098463de4c5d 458 #define MXC_F_AFE_CTRL1_REF_DAC_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS))
group-onsemi 0:098463de4c5d 459 #define MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS 13
group-onsemi 0:098463de4c5d 460 #define MXC_F_AFE_CTRL1_REF_BLK_POWERUP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS))
group-onsemi 0:098463de4c5d 461 #define MXC_F_AFE_CTRL1_REF_ADC_COMP_POS 14
group-onsemi 0:098463de4c5d 462 #define MXC_F_AFE_CTRL1_REF_ADC_COMP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_COMP_POS))
group-onsemi 0:098463de4c5d 463 #define MXC_F_AFE_CTRL1_REF_DAC_COMP_POS 15
group-onsemi 0:098463de4c5d 464 #define MXC_F_AFE_CTRL1_REF_DAC_COMP ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_COMP_POS))
group-onsemi 0:098463de4c5d 465 #define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS 16
group-onsemi 0:098463de4c5d 466 #define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS))
group-onsemi 0:098463de4c5d 467 #define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS 18
group-onsemi 0:098463de4c5d 468 #define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS))
group-onsemi 0:098463de4c5d 469 #define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS 20
group-onsemi 0:098463de4c5d 470 #define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS))
group-onsemi 0:098463de4c5d 471 #define MXC_F_AFE_CTRL1_PLL_TST_EN_POS 23
group-onsemi 0:098463de4c5d 472 #define MXC_F_AFE_CTRL1_PLL_TST_EN ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_PLL_TST_EN_POS))
group-onsemi 0:098463de4c5d 473 #define MXC_F_AFE_CTRL1_V1EXTADJ_POS 25
group-onsemi 0:098463de4c5d 474 #define MXC_F_AFE_CTRL1_V1EXTADJ ((uint32_t)(0x0000001FUL << MXC_F_AFE_CTRL1_V1EXTADJ_POS))
group-onsemi 0:098463de4c5d 475 #define MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS 30
group-onsemi 0:098463de4c5d 476 #define MXC_F_AFE_CTRL1_TMON_CUR_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS))
group-onsemi 0:098463de4c5d 477
group-onsemi 0:098463de4c5d 478 #define MXC_F_AFE_CTRL2_HYST_COMP0_POS 0
group-onsemi 0:098463de4c5d 479 #define MXC_F_AFE_CTRL2_HYST_COMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP0_POS))
group-onsemi 0:098463de4c5d 480 #define MXC_F_AFE_CTRL2_HYST_COMP1_POS 2
group-onsemi 0:098463de4c5d 481 #define MXC_F_AFE_CTRL2_HYST_COMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP1_POS))
group-onsemi 0:098463de4c5d 482 #define MXC_F_AFE_CTRL2_HYST_COMP2_POS 4
group-onsemi 0:098463de4c5d 483 #define MXC_F_AFE_CTRL2_HYST_COMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP2_POS))
group-onsemi 0:098463de4c5d 484 #define MXC_F_AFE_CTRL2_HYST_COMP3_POS 6
group-onsemi 0:098463de4c5d 485 #define MXC_F_AFE_CTRL2_HYST_COMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP3_POS))
group-onsemi 0:098463de4c5d 486 #define MXC_F_AFE_CTRL2_HY_POL_COMP0_POS 8
group-onsemi 0:098463de4c5d 487 #define MXC_F_AFE_CTRL2_HY_POL_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP0_POS))
group-onsemi 0:098463de4c5d 488 #define MXC_F_AFE_CTRL2_HY_POL_COMP1_POS 9
group-onsemi 0:098463de4c5d 489 #define MXC_F_AFE_CTRL2_HY_POL_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP1_POS))
group-onsemi 0:098463de4c5d 490 #define MXC_F_AFE_CTRL2_HY_POL_COMP2_POS 10
group-onsemi 0:098463de4c5d 491 #define MXC_F_AFE_CTRL2_HY_POL_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP2_POS))
group-onsemi 0:098463de4c5d 492 #define MXC_F_AFE_CTRL2_HY_POL_COMP3_POS 11
group-onsemi 0:098463de4c5d 493 #define MXC_F_AFE_CTRL2_HY_POL_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP3_POS))
group-onsemi 0:098463de4c5d 494 #define MXC_F_AFE_CTRL2_POWERUP_COMP0_POS 12
group-onsemi 0:098463de4c5d 495 #define MXC_F_AFE_CTRL2_POWERUP_COMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP0_POS))
group-onsemi 0:098463de4c5d 496 #define MXC_F_AFE_CTRL2_POWERUP_COMP1_POS 13
group-onsemi 0:098463de4c5d 497 #define MXC_F_AFE_CTRL2_POWERUP_COMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP1_POS))
group-onsemi 0:098463de4c5d 498 #define MXC_F_AFE_CTRL2_POWERUP_COMP2_POS 14
group-onsemi 0:098463de4c5d 499 #define MXC_F_AFE_CTRL2_POWERUP_COMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP2_POS))
group-onsemi 0:098463de4c5d 500 #define MXC_F_AFE_CTRL2_POWERUP_COMP3_POS 15
group-onsemi 0:098463de4c5d 501 #define MXC_F_AFE_CTRL2_POWERUP_COMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP3_POS))
group-onsemi 0:098463de4c5d 502 #define MXC_F_AFE_CTRL2_DACOUT_EN0_POS 16
group-onsemi 0:098463de4c5d 503 #define MXC_F_AFE_CTRL2_DACOUT_EN0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN0_POS))
group-onsemi 0:098463de4c5d 504 #define MXC_F_AFE_CTRL2_DACOUT_EN1_POS 17
group-onsemi 0:098463de4c5d 505 #define MXC_F_AFE_CTRL2_DACOUT_EN1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN1_POS))
group-onsemi 0:098463de4c5d 506 #define MXC_F_AFE_CTRL2_DACOUT_EN2_POS 18
group-onsemi 0:098463de4c5d 507 #define MXC_F_AFE_CTRL2_DACOUT_EN2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN2_POS))
group-onsemi 0:098463de4c5d 508 #define MXC_F_AFE_CTRL2_DACOUT_EN3_POS 19
group-onsemi 0:098463de4c5d 509 #define MXC_F_AFE_CTRL2_DACOUT_EN3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN3_POS))
group-onsemi 0:098463de4c5d 510 #define MXC_F_AFE_CTRL2_SCM_OR_SEL_POS 20
group-onsemi 0:098463de4c5d 511 #define MXC_F_AFE_CTRL2_SCM_OR_SEL ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SCM_OR_SEL_POS))
group-onsemi 0:098463de4c5d 512 #define MXC_F_AFE_CTRL2_SNO_OR_SEL_POS 23
group-onsemi 0:098463de4c5d 513 #define MXC_F_AFE_CTRL2_SNO_OR_SEL ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SNO_OR_SEL_POS))
group-onsemi 0:098463de4c5d 514 #define MXC_F_AFE_CTRL2_DAC0_SEL_POS 26
group-onsemi 0:098463de4c5d 515 #define MXC_F_AFE_CTRL2_DAC0_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC0_SEL_POS))
group-onsemi 0:098463de4c5d 516 #define MXC_F_AFE_CTRL2_DAC1_SEL_POS 27
group-onsemi 0:098463de4c5d 517 #define MXC_F_AFE_CTRL2_DAC1_SEL ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC1_SEL_POS))
group-onsemi 0:098463de4c5d 518
group-onsemi 0:098463de4c5d 519 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS 12
group-onsemi 0:098463de4c5d 520 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS))
group-onsemi 0:098463de4c5d 521 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS 13
group-onsemi 0:098463de4c5d 522 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS))
group-onsemi 0:098463de4c5d 523 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS 14
group-onsemi 0:098463de4c5d 524 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS))
group-onsemi 0:098463de4c5d 525 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS 15
group-onsemi 0:098463de4c5d 526 #define MXC_F_AFE_CTRL3_POWERUP_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS))
group-onsemi 0:098463de4c5d 527 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS 16
group-onsemi 0:098463de4c5d 528 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS))
group-onsemi 0:098463de4c5d 529 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS 17
group-onsemi 0:098463de4c5d 530 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS))
group-onsemi 0:098463de4c5d 531 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS 18
group-onsemi 0:098463de4c5d 532 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS))
group-onsemi 0:098463de4c5d 533 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS 19
group-onsemi 0:098463de4c5d 534 #define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS))
group-onsemi 0:098463de4c5d 535 #define MXC_F_AFE_CTRL3_CLOSE_SPST0_POS 20
group-onsemi 0:098463de4c5d 536 #define MXC_F_AFE_CTRL3_CLOSE_SPST0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST0_POS))
group-onsemi 0:098463de4c5d 537 #define MXC_F_AFE_CTRL3_CLOSE_SPST1_POS 21
group-onsemi 0:098463de4c5d 538 #define MXC_F_AFE_CTRL3_CLOSE_SPST1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST1_POS))
group-onsemi 0:098463de4c5d 539 #define MXC_F_AFE_CTRL3_CLOSE_SPST2_POS 22
group-onsemi 0:098463de4c5d 540 #define MXC_F_AFE_CTRL3_CLOSE_SPST2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST2_POS))
group-onsemi 0:098463de4c5d 541 #define MXC_F_AFE_CTRL3_CLOSE_SPST3_POS 23
group-onsemi 0:098463de4c5d 542 #define MXC_F_AFE_CTRL3_CLOSE_SPST3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST3_POS))
group-onsemi 0:098463de4c5d 543 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS 24
group-onsemi 0:098463de4c5d 544 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS))
group-onsemi 0:098463de4c5d 545 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS 25
group-onsemi 0:098463de4c5d 546 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS))
group-onsemi 0:098463de4c5d 547 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS 26
group-onsemi 0:098463de4c5d 548 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS))
group-onsemi 0:098463de4c5d 549 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS 27
group-onsemi 0:098463de4c5d 550 #define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS))
group-onsemi 0:098463de4c5d 551 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS 28
group-onsemi 0:098463de4c5d 552 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS))
group-onsemi 0:098463de4c5d 553 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS 29
group-onsemi 0:098463de4c5d 554 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS))
group-onsemi 0:098463de4c5d 555 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS 30
group-onsemi 0:098463de4c5d 556 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS))
group-onsemi 0:098463de4c5d 557 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS 31
group-onsemi 0:098463de4c5d 558 #define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS))
group-onsemi 0:098463de4c5d 559
group-onsemi 0:098463de4c5d 560 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS 0
group-onsemi 0:098463de4c5d 561 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS))
group-onsemi 0:098463de4c5d 562 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS 2
group-onsemi 0:098463de4c5d 563 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS))
group-onsemi 0:098463de4c5d 564 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS 4
group-onsemi 0:098463de4c5d 565 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS))
group-onsemi 0:098463de4c5d 566 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS 6
group-onsemi 0:098463de4c5d 567 #define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS))
group-onsemi 0:098463de4c5d 568 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS 8
group-onsemi 0:098463de4c5d 569 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS))
group-onsemi 0:098463de4c5d 570 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS 10
group-onsemi 0:098463de4c5d 571 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS))
group-onsemi 0:098463de4c5d 572 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS 12
group-onsemi 0:098463de4c5d 573 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS))
group-onsemi 0:098463de4c5d 574 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS 14
group-onsemi 0:098463de4c5d 575 #define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3 ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS))
group-onsemi 0:098463de4c5d 576 #define MXC_F_AFE_CTRL4_DAC_SEL_A_POS 16
group-onsemi 0:098463de4c5d 577 #define MXC_F_AFE_CTRL4_DAC_SEL_A ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_A_POS))
group-onsemi 0:098463de4c5d 578 #define MXC_F_AFE_CTRL4_DAC_SEL_B_POS 18
group-onsemi 0:098463de4c5d 579 #define MXC_F_AFE_CTRL4_DAC_SEL_B ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_B_POS))
group-onsemi 0:098463de4c5d 580 #define MXC_F_AFE_CTRL4_DAC_SEL_C_POS 20
group-onsemi 0:098463de4c5d 581 #define MXC_F_AFE_CTRL4_DAC_SEL_C ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_C_POS))
group-onsemi 0:098463de4c5d 582 #define MXC_F_AFE_CTRL4_DAC_SEL_D_POS 22
group-onsemi 0:098463de4c5d 583 #define MXC_F_AFE_CTRL4_DAC_SEL_D ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_D_POS))
group-onsemi 0:098463de4c5d 584 #define MXC_F_AFE_CTRL4_NPAD_SEL_A_POS 24
group-onsemi 0:098463de4c5d 585 #define MXC_F_AFE_CTRL4_NPAD_SEL_A ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_A_POS))
group-onsemi 0:098463de4c5d 586 #define MXC_F_AFE_CTRL4_NPAD_SEL_B_POS 26
group-onsemi 0:098463de4c5d 587 #define MXC_F_AFE_CTRL4_NPAD_SEL_B ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_B_POS))
group-onsemi 0:098463de4c5d 588 #define MXC_F_AFE_CTRL4_NPAD_SEL_C_POS 28
group-onsemi 0:098463de4c5d 589 #define MXC_F_AFE_CTRL4_NPAD_SEL_C ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_C_POS))
group-onsemi 0:098463de4c5d 590 #define MXC_F_AFE_CTRL4_NPAD_SEL_D_POS 30
group-onsemi 0:098463de4c5d 591 #define MXC_F_AFE_CTRL4_NPAD_SEL_D ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_D_POS))
group-onsemi 0:098463de4c5d 592
group-onsemi 0:098463de4c5d 593 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS 0
group-onsemi 0:098463de4c5d 594 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS))
group-onsemi 0:098463de4c5d 595 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS 3
group-onsemi 0:098463de4c5d 596 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS))
group-onsemi 0:098463de4c5d 597 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS 6
group-onsemi 0:098463de4c5d 598 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS))
group-onsemi 0:098463de4c5d 599 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS 9
group-onsemi 0:098463de4c5d 600 #define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS))
group-onsemi 0:098463de4c5d 601 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS 12
group-onsemi 0:098463de4c5d 602 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS))
group-onsemi 0:098463de4c5d 603 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS 15
group-onsemi 0:098463de4c5d 604 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS))
group-onsemi 0:098463de4c5d 605 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS 18
group-onsemi 0:098463de4c5d 606 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS))
group-onsemi 0:098463de4c5d 607 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS 21
group-onsemi 0:098463de4c5d 608 #define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3 ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS))
group-onsemi 0:098463de4c5d 609 #define MXC_F_AFE_CTRL5_OP_CMP0_POS 24
group-onsemi 0:098463de4c5d 610 #define MXC_F_AFE_CTRL5_OP_CMP0 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP0_POS))
group-onsemi 0:098463de4c5d 611 #define MXC_F_AFE_CTRL5_OP_CMP1_POS 25
group-onsemi 0:098463de4c5d 612 #define MXC_F_AFE_CTRL5_OP_CMP1 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP1_POS))
group-onsemi 0:098463de4c5d 613 #define MXC_F_AFE_CTRL5_OP_CMP2_POS 26
group-onsemi 0:098463de4c5d 614 #define MXC_F_AFE_CTRL5_OP_CMP2 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP2_POS))
group-onsemi 0:098463de4c5d 615 #define MXC_F_AFE_CTRL5_OP_CMP3_POS 27
group-onsemi 0:098463de4c5d 616 #define MXC_F_AFE_CTRL5_OP_CMP3 ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP3_POS))
group-onsemi 0:098463de4c5d 617
group-onsemi 0:098463de4c5d 618 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 619 }
group-onsemi 0:098463de4c5d 620 #endif
group-onsemi 0:098463de4c5d 621
group-onsemi 0:098463de4c5d 622 /**
group-onsemi 0:098463de4c5d 623 * @}
group-onsemi 0:098463de4c5d 624 */
group-onsemi 0:098463de4c5d 625
group-onsemi 0:098463de4c5d 626 #endif /* _MXC_AFE_REGS_H_ */