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targets/TARGET_Maxim/TARGET_MAX32600/device/rtc_regs.h@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #ifndef _MXC_RTC_REGS_H
group-onsemi 0:098463de4c5d 35 #define _MXC_RTC_REGS_H
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 38 extern "C" {
group-onsemi 0:098463de4c5d 39 #endif
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 #include <stdint.h>
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 /**
group-onsemi 0:098463de4c5d 44 * @file rtc_regs.h
group-onsemi 0:098463de4c5d 45 * @addtogroup rtc RTCTMR
group-onsemi 0:098463de4c5d 46 * @{
group-onsemi 0:098463de4c5d 47 */
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49 /**
group-onsemi 0:098463de4c5d 50 * @brief Defines clock divider for 4096Hz input clock.
group-onsemi 0:098463de4c5d 51 */
group-onsemi 0:098463de4c5d 52 typedef enum {
group-onsemi 0:098463de4c5d 53 /** (4kHz) divide input clock by 2^0 = 1 */
group-onsemi 0:098463de4c5d 54 MXC_E_RTC_PRESCALE_DIV_2_0 = 0,
group-onsemi 0:098463de4c5d 55 /** (2kHz) divide input clock by 2^1 = 2 */
group-onsemi 0:098463de4c5d 56 MXC_E_RTC_PRESCALE_DIV_2_1,
group-onsemi 0:098463de4c5d 57 /** (1kHz) divide input clock by 2^2 = 4 */
group-onsemi 0:098463de4c5d 58 MXC_E_RTC_PRESCALE_DIV_2_2,
group-onsemi 0:098463de4c5d 59 /** (512Hz) divide input clock by 2^3 = 8 */
group-onsemi 0:098463de4c5d 60 MXC_E_RTC_PRESCALE_DIV_2_3,
group-onsemi 0:098463de4c5d 61 /** (256Hz) divide input clock by 2^4 = 16 */
group-onsemi 0:098463de4c5d 62 MXC_E_RTC_PRESCALE_DIV_2_4,
group-onsemi 0:098463de4c5d 63 /** (128Hz) divide input clock by 2^5 = 32 */
group-onsemi 0:098463de4c5d 64 MXC_E_RTC_PRESCALE_DIV_2_5,
group-onsemi 0:098463de4c5d 65 /** (64Hz) divide input clock by 2^6 = 64 */
group-onsemi 0:098463de4c5d 66 MXC_E_RTC_PRESCALE_DIV_2_6,
group-onsemi 0:098463de4c5d 67 /** (32Hz) divide input clock by 2^7 = 128 */
group-onsemi 0:098463de4c5d 68 MXC_E_RTC_PRESCALE_DIV_2_7,
group-onsemi 0:098463de4c5d 69 /** (16Hz) divide input clock by 2^8 = 256 */
group-onsemi 0:098463de4c5d 70 MXC_E_RTC_PRESCALE_DIV_2_8,
group-onsemi 0:098463de4c5d 71 /** (8Hz) divide input clock by 2^9 = 512 */
group-onsemi 0:098463de4c5d 72 MXC_E_RTC_PRESCALE_DIV_2_9,
group-onsemi 0:098463de4c5d 73 /** (4Hz) divide input clock by 2^10 = 1024 */
group-onsemi 0:098463de4c5d 74 MXC_E_RTC_PRESCALE_DIV_2_10,
group-onsemi 0:098463de4c5d 75 /** (2Hz) divide input clock by 2^11 = 2048 */
group-onsemi 0:098463de4c5d 76 MXC_E_RTC_PRESCALE_DIV_2_11,
group-onsemi 0:098463de4c5d 77 /** (1Hz) divide input clock by 2^12 = 4096 */
group-onsemi 0:098463de4c5d 78 MXC_E_RTC_PRESCALE_DIV_2_12,
group-onsemi 0:098463de4c5d 79 } mxc_rtc_prescale_t;
group-onsemi 0:098463de4c5d 80
group-onsemi 0:098463de4c5d 81 /* Offset Register Description
group-onsemi 0:098463de4c5d 82 ====== ========================================= */
group-onsemi 0:098463de4c5d 83 typedef struct {
group-onsemi 0:098463de4c5d 84 __IO uint32_t ctrl; /* 0x0000 RTC Timer Control */
group-onsemi 0:098463de4c5d 85 __IO uint32_t timer; /* 0x0004 RTC Timer Count Value */
group-onsemi 0:098463de4c5d 86 __IO uint32_t comp[2]; /* 0x0008 RTC Alarm (0..1) Compare Registers */
group-onsemi 0:098463de4c5d 87 __IO uint32_t flags; /* 0x0010 CPU Interrupt and RTC Domain Flags */
group-onsemi 0:098463de4c5d 88 __I uint32_t rsv0014; /* 0x0014 */
group-onsemi 0:098463de4c5d 89 __IO uint32_t inten; /* 0x0018 Interrupt Enable Controls */
group-onsemi 0:098463de4c5d 90 __IO uint32_t prescale; /* 0x001C RTC Timer Prescale Setting */
group-onsemi 0:098463de4c5d 91 __I uint32_t rsv0020; /* 0x0020 */
group-onsemi 0:098463de4c5d 92 __IO uint32_t prescale_mask; /* 0x0024 RTC Timer Prescale Compare Mask */
group-onsemi 0:098463de4c5d 93 __IO uint32_t trim_ctrl; /* 0x0028 RTC Timer Trim Controls */
group-onsemi 0:098463de4c5d 94 __IO uint32_t trim_value; /* 0x002C RTC Timer Trim Adjustment Interval */
group-onsemi 0:098463de4c5d 95 } mxc_rtctmr_regs_t;
group-onsemi 0:098463de4c5d 96
group-onsemi 0:098463de4c5d 97 /*
group-onsemi 0:098463de4c5d 98 Register offsets for module RTCTMR.
group-onsemi 0:098463de4c5d 99 */
group-onsemi 0:098463de4c5d 100 #define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL)
group-onsemi 0:098463de4c5d 101 #define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL)
group-onsemi 0:098463de4c5d 102 #define MXC_R_RTCTMR_OFFS_COMP_0 ((uint32_t)0x00000008UL)
group-onsemi 0:098463de4c5d 103 #define MXC_R_RTCTMR_OFFS_COMP_1 ((uint32_t)0x0000000CUL)
group-onsemi 0:098463de4c5d 104 #define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL)
group-onsemi 0:098463de4c5d 105 #define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL)
group-onsemi 0:098463de4c5d 106 #define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL)
group-onsemi 0:098463de4c5d 107 #define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL)
group-onsemi 0:098463de4c5d 108 #define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL)
group-onsemi 0:098463de4c5d 109 #define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL)
group-onsemi 0:098463de4c5d 110
group-onsemi 0:098463de4c5d 111 /*
group-onsemi 0:098463de4c5d 112 Field positions and masks for module RTCTMR.
group-onsemi 0:098463de4c5d 113 */
group-onsemi 0:098463de4c5d 114 #define MXC_F_RTC_CTRL_ENABLE_POS 0
group-onsemi 0:098463de4c5d 115 #define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS))
group-onsemi 0:098463de4c5d 116 #define MXC_F_RTC_CTRL_CLEAR_POS 1
group-onsemi 0:098463de4c5d 117 #define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS))
group-onsemi 0:098463de4c5d 118 #define MXC_F_RTC_CTRL_PENDING_POS 2
group-onsemi 0:098463de4c5d 119 #define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS))
group-onsemi 0:098463de4c5d 120 #define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3
group-onsemi 0:098463de4c5d 121 #define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS))
group-onsemi 0:098463de4c5d 122 #define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4
group-onsemi 0:098463de4c5d 123 #define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS))
group-onsemi 0:098463de4c5d 124 #define MXC_F_RTC_CTRL_EN_ACTIVE_POS 16
group-onsemi 0:098463de4c5d 125 #define MXC_F_RTC_CTRL_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_EN_ACTIVE_POS))
group-onsemi 0:098463de4c5d 126 #define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17
group-onsemi 0:098463de4c5d 127 #define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS))
group-onsemi 0:098463de4c5d 128 #define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18
group-onsemi 0:098463de4c5d 129 #define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS))
group-onsemi 0:098463de4c5d 130 #define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19
group-onsemi 0:098463de4c5d 131 #define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS))
group-onsemi 0:098463de4c5d 132 #define MXC_F_RTC_CTRL_SET_ACTIVE_POS 20
group-onsemi 0:098463de4c5d 133 #define MXC_F_RTC_CTRL_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_SET_ACTIVE_POS))
group-onsemi 0:098463de4c5d 134 #define MXC_F_RTC_CTRL_CLR_ACTIVE_POS 21
group-onsemi 0:098463de4c5d 135 #define MXC_F_RTC_CTRL_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLR_ACTIVE_POS))
group-onsemi 0:098463de4c5d 136 #define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22
group-onsemi 0:098463de4c5d 137 #define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS))
group-onsemi 0:098463de4c5d 138 #define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23
group-onsemi 0:098463de4c5d 139 #define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS))
group-onsemi 0:098463de4c5d 140 #define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24
group-onsemi 0:098463de4c5d 141 #define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS))
group-onsemi 0:098463de4c5d 142 #define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25
group-onsemi 0:098463de4c5d 143 #define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS))
group-onsemi 0:098463de4c5d 144 #define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26
group-onsemi 0:098463de4c5d 145 #define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS))
group-onsemi 0:098463de4c5d 146
group-onsemi 0:098463de4c5d 147 #define MXC_F_RTC_FLAGS_COMP0_POS 0
group-onsemi 0:098463de4c5d 148 #define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS))
group-onsemi 0:098463de4c5d 149 #define MXC_F_RTC_FLAGS_COMP1_POS 1
group-onsemi 0:098463de4c5d 150 #define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS))
group-onsemi 0:098463de4c5d 151 #define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2
group-onsemi 0:098463de4c5d 152 #define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS))
group-onsemi 0:098463de4c5d 153 #define MXC_F_RTC_FLAGS_OVERFLOW_POS 3
group-onsemi 0:098463de4c5d 154 #define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS))
group-onsemi 0:098463de4c5d 155 #define MXC_F_RTC_FLAGS_TRIM_POS 4
group-onsemi 0:098463de4c5d 156 #define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS))
group-onsemi 0:098463de4c5d 157 #define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8
group-onsemi 0:098463de4c5d 158 #define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS))
group-onsemi 0:098463de4c5d 159 #define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9
group-onsemi 0:098463de4c5d 160 #define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS))
group-onsemi 0:098463de4c5d 161 #define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10
group-onsemi 0:098463de4c5d 162 #define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS))
group-onsemi 0:098463de4c5d 163 #define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11
group-onsemi 0:098463de4c5d 164 #define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS))
group-onsemi 0:098463de4c5d 165 #define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12
group-onsemi 0:098463de4c5d 166 #define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS))
group-onsemi 0:098463de4c5d 167 #define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31
group-onsemi 0:098463de4c5d 168 #define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS))
group-onsemi 0:098463de4c5d 169
group-onsemi 0:098463de4c5d 170 #define MXC_F_RTC_INTEN_COMP0_POS 0
group-onsemi 0:098463de4c5d 171 #define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS))
group-onsemi 0:098463de4c5d 172 #define MXC_F_RTC_INTEN_COMP1_POS 1
group-onsemi 0:098463de4c5d 173 #define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS))
group-onsemi 0:098463de4c5d 174 #define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2
group-onsemi 0:098463de4c5d 175 #define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS))
group-onsemi 0:098463de4c5d 176 #define MXC_F_RTC_INTEN_OVERFLOW_POS 3
group-onsemi 0:098463de4c5d 177 #define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS))
group-onsemi 0:098463de4c5d 178 #define MXC_F_RTC_INTEN_TRIM_POS 4
group-onsemi 0:098463de4c5d 179 #define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS))
group-onsemi 0:098463de4c5d 180
group-onsemi 0:098463de4c5d 181 #define MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS 0
group-onsemi 0:098463de4c5d 182 #define MXC_F_RTC_PRESCALE_WIDTH_SELECTION ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS))
group-onsemi 0:098463de4c5d 183
group-onsemi 0:098463de4c5d 184 #define MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS 0
group-onsemi 0:098463de4c5d 185 #define MXC_F_RTC_PRESCALE_MASK_COMP_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS))
group-onsemi 0:098463de4c5d 186
group-onsemi 0:098463de4c5d 187 #define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0
group-onsemi 0:098463de4c5d 188 #define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS))
group-onsemi 0:098463de4c5d 189 #define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1
group-onsemi 0:098463de4c5d 190 #define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS))
group-onsemi 0:098463de4c5d 191 #define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2
group-onsemi 0:098463de4c5d 192 #define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS))
group-onsemi 0:098463de4c5d 193
group-onsemi 0:098463de4c5d 194 #define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0
group-onsemi 0:098463de4c5d 195 #define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS))
group-onsemi 0:098463de4c5d 196 #define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS 18
group-onsemi 0:098463de4c5d 197 #define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS))
group-onsemi 0:098463de4c5d 198
group-onsemi 0:098463de4c5d 199 #define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0
group-onsemi 0:098463de4c5d 200 #define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS))
group-onsemi 0:098463de4c5d 201
group-onsemi 0:098463de4c5d 202 #define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0
group-onsemi 0:098463de4c5d 203 #define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS))
group-onsemi 0:098463de4c5d 204 #define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1
group-onsemi 0:098463de4c5d 205 #define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS))
group-onsemi 0:098463de4c5d 206 #define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2
group-onsemi 0:098463de4c5d 207 #define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS))
group-onsemi 0:098463de4c5d 208
group-onsemi 0:098463de4c5d 209 #define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS 0
group-onsemi 0:098463de4c5d 210 #define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS))
group-onsemi 0:098463de4c5d 211
group-onsemi 0:098463de4c5d 212 #define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0
group-onsemi 0:098463de4c5d 213 #define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS))
group-onsemi 0:098463de4c5d 214 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1
group-onsemi 0:098463de4c5d 215 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS))
group-onsemi 0:098463de4c5d 216 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2
group-onsemi 0:098463de4c5d 217 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS))
group-onsemi 0:098463de4c5d 218 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3
group-onsemi 0:098463de4c5d 219 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS))
group-onsemi 0:098463de4c5d 220
group-onsemi 0:098463de4c5d 221 /* Offset Register Description
group-onsemi 0:098463de4c5d 222 ====== ===================================================================== */
group-onsemi 0:098463de4c5d 223 typedef struct {
group-onsemi 0:098463de4c5d 224 __IO uint32_t nano_counter; /* 0x0000 Nanoring Counter Read Register */
group-onsemi 0:098463de4c5d 225 __IO uint32_t clk_ctrl; /* 0x0004 RTC Clock Control Settings */
group-onsemi 0:098463de4c5d 226 __IO uint32_t dsen_ctrl; /* 0x0008 Dynamic Tamper Sensor Control */
group-onsemi 0:098463de4c5d 227 __IO uint32_t osc_ctrl; /* 0x000C RTC Oscillator Control */
group-onsemi 0:098463de4c5d 228 } mxc_rtccfg_regs_t;
group-onsemi 0:098463de4c5d 229
group-onsemi 0:098463de4c5d 230 /*
group-onsemi 0:098463de4c5d 231 Register offsets for module RTCCFG.
group-onsemi 0:098463de4c5d 232 */
group-onsemi 0:098463de4c5d 233 #define MXC_R_RTCCFG_OFFS_NANO_COUNTER ((uint32_t)0x00000000UL)
group-onsemi 0:098463de4c5d 234 #define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
group-onsemi 0:098463de4c5d 235 #define MXC_R_RTCCFG_OFFS_DSEN_CTRL ((uint32_t)0x00000008UL)
group-onsemi 0:098463de4c5d 236 #define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL)
group-onsemi 0:098463de4c5d 237
group-onsemi 0:098463de4c5d 238 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 239 }
group-onsemi 0:098463de4c5d 240 #endif
group-onsemi 0:098463de4c5d 241
group-onsemi 0:098463de4c5d 242 /**
group-onsemi 0:098463de4c5d 243 * @}
group-onsemi 0:098463de4c5d 244 */
group-onsemi 0:098463de4c5d 245
group-onsemi 0:098463de4c5d 246 #endif /* _MXC_RTC_REGS_H */