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targets/TARGET_Maxim/TARGET_MAX32600/device/flc_regs.h@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #ifndef _MXC_FLC_REGS_H
group-onsemi 0:098463de4c5d 35 #define _MXC_FLC_REGS_H
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 38 extern "C" {
group-onsemi 0:098463de4c5d 39 #endif
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 #include <stdint.h>
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 /**
group-onsemi 0:098463de4c5d 44 * @file flc_regs.h
group-onsemi 0:098463de4c5d 45 * @addtogroup flc FLC
group-onsemi 0:098463de4c5d 46 * @{
group-onsemi 0:098463de4c5d 47 */
group-onsemi 0:098463de4c5d 48 /* Offset Register Description
group-onsemi 0:098463de4c5d 49 ====== ======================================================= */
group-onsemi 0:098463de4c5d 50 typedef struct {
group-onsemi 0:098463de4c5d 51 __IO uint32_t faddr; /* 0x0000 Flash Operation Address */
group-onsemi 0:098463de4c5d 52 __IO uint32_t fckdiv; /* 0x0004 Flash Clock Rate Divisor */
group-onsemi 0:098463de4c5d 53 __IO uint32_t ctrl; /* 0x0008 Flash Control Register */
group-onsemi 0:098463de4c5d 54 __I uint32_t rsv000C[6]; /* 0x000C */
group-onsemi 0:098463de4c5d 55 __IO uint32_t intr; /* 0x0024 Flash Controller Interrupt Flags and Enable/Disable 0 */
group-onsemi 0:098463de4c5d 56 __I uint32_t rsv0028[2]; /* 0x0028 */
group-onsemi 0:098463de4c5d 57 __IO uint32_t fdata; /* 0x0030 Flash Operation Data Register */
group-onsemi 0:098463de4c5d 58 __I uint32_t rsv0034[7]; /* 0x0034 */
group-onsemi 0:098463de4c5d 59 __IO uint32_t perform; /* 0x0050 Flash Performance Settings */
group-onsemi 0:098463de4c5d 60 __I uint32_t rsv0054[11]; /* 0x0054 */
group-onsemi 0:098463de4c5d 61 __IO uint32_t status; /* 0x0080 Security Status Flags */
group-onsemi 0:098463de4c5d 62 __I uint32_t rsv0084; /* 0x0084 */
group-onsemi 0:098463de4c5d 63 __IO uint32_t security; /* 0x0088 Flash Controller Security Settings */
group-onsemi 0:098463de4c5d 64 __I uint32_t rsv008C[4]; /* 0x008C */
group-onsemi 0:098463de4c5d 65 __IO uint32_t bypass; /* 0x009C Status Flags for DSB Operations */
group-onsemi 0:098463de4c5d 66 __IO uint32_t user_option; /* 0x0100 Used to set DSB Access code and Auto-Lock in info block */
group-onsemi 0:098463de4c5d 67 __I uint32_t rsv0104[15]; /* 0x0104 */
group-onsemi 0:098463de4c5d 68 __IO uint32_t ctrl2; /* 0x0140 Flash Control Register 2 */
group-onsemi 0:098463de4c5d 69 __IO uint32_t intfl1; /* 0x0144 Interrupt Flags Register 1 */
group-onsemi 0:098463de4c5d 70 __IO uint32_t inten1; /* 0x0148 Interrupt Enable/Disable Register 1 */
group-onsemi 0:098463de4c5d 71 __I uint32_t rsv014C; /* 0x014C */
group-onsemi 0:098463de4c5d 72 __IO uint32_t disable_xr0; /* 0x0150 Disable Flash Page Exec/Read Register 0 */
group-onsemi 0:098463de4c5d 73 __IO uint32_t disable_xr1; /* 0x0154 Disable Flash Page Exec/Read Register 1 */
group-onsemi 0:098463de4c5d 74 __IO uint32_t disable_xr2; /* 0x0158 Disable Flash Page Exec/Read Register 2 */
group-onsemi 0:098463de4c5d 75 __IO uint32_t disable_xr3; /* 0x015C Disable Flash Page Exec/Read Register 3 */
group-onsemi 0:098463de4c5d 76 __IO uint32_t disable_we0; /* 0x0160 Disable Flash Page Write/Erase Register 0 */
group-onsemi 0:098463de4c5d 77 __IO uint32_t disable_we1; /* 0x0164 Disable Flash Page Write/Erase Register 1 */
group-onsemi 0:098463de4c5d 78 __IO uint32_t disable_we2; /* 0x0168 Disable Flash Page Write/Erase Register 2 */
group-onsemi 0:098463de4c5d 79 __IO uint32_t disable_we3; /* 0x016C Disable Flash Page Write/Erase Register 3 */
group-onsemi 0:098463de4c5d 80 } mxc_flc_regs_t;
group-onsemi 0:098463de4c5d 81
group-onsemi 0:098463de4c5d 82 /*
group-onsemi 0:098463de4c5d 83 Register offsets for module FLC.
group-onsemi 0:098463de4c5d 84 */
group-onsemi 0:098463de4c5d 85 #define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL)
group-onsemi 0:098463de4c5d 86 #define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL)
group-onsemi 0:098463de4c5d 87 #define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL)
group-onsemi 0:098463de4c5d 88 #define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL)
group-onsemi 0:098463de4c5d 89 #define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL)
group-onsemi 0:098463de4c5d 90 #define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL)
group-onsemi 0:098463de4c5d 91 #define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL)
group-onsemi 0:098463de4c5d 92 #define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL)
group-onsemi 0:098463de4c5d 93 #define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL)
group-onsemi 0:098463de4c5d 94 #define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL)
group-onsemi 0:098463de4c5d 95 #define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL)
group-onsemi 0:098463de4c5d 96 #define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL)
group-onsemi 0:098463de4c5d 97 #define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL)
group-onsemi 0:098463de4c5d 98 #define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000150UL)
group-onsemi 0:098463de4c5d 99 #define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000154UL)
group-onsemi 0:098463de4c5d 100 #define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000158UL)
group-onsemi 0:098463de4c5d 101 #define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000015CUL)
group-onsemi 0:098463de4c5d 102 #define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000160UL)
group-onsemi 0:098463de4c5d 103 #define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000164UL)
group-onsemi 0:098463de4c5d 104 #define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000168UL)
group-onsemi 0:098463de4c5d 105 #define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000016CUL)
group-onsemi 0:098463de4c5d 106
group-onsemi 0:098463de4c5d 107 #define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55)
group-onsemi 0:098463de4c5d 108 #define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA)
group-onsemi 0:098463de4c5d 109
group-onsemi 0:098463de4c5d 110 #define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2)
group-onsemi 0:098463de4c5d 111
group-onsemi 0:098463de4c5d 112 /*
group-onsemi 0:098463de4c5d 113 Field positions and masks for module FLC.
group-onsemi 0:098463de4c5d 114 */
group-onsemi 0:098463de4c5d 115 #define MXC_F_FLC_FADDR_FADDR_POS 0
group-onsemi 0:098463de4c5d 116 #define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x0003FFFFUL << MXC_F_FLC_FADDR_FADDR_POS))
group-onsemi 0:098463de4c5d 117
group-onsemi 0:098463de4c5d 118 #define MXC_F_FLC_FCKDIV_FCKDIV_POS 0
group-onsemi 0:098463de4c5d 119 #define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000001FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS))
group-onsemi 0:098463de4c5d 120
group-onsemi 0:098463de4c5d 121 #define MXC_F_FLC_CTRL_WRITE_POS 0
group-onsemi 0:098463de4c5d 122 #define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS))
group-onsemi 0:098463de4c5d 123 #define MXC_F_FLC_CTRL_MASS_ERASE_POS 1
group-onsemi 0:098463de4c5d 124 #define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS))
group-onsemi 0:098463de4c5d 125 #define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2
group-onsemi 0:098463de4c5d 126 #define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS))
group-onsemi 0:098463de4c5d 127 #define MXC_F_FLC_CTRL_ERASE_CODE_POS 8
group-onsemi 0:098463de4c5d 128 #define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS))
group-onsemi 0:098463de4c5d 129 #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16
group-onsemi 0:098463de4c5d 130 #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS))
group-onsemi 0:098463de4c5d 131 #define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17
group-onsemi 0:098463de4c5d 132 #define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS))
group-onsemi 0:098463de4c5d 133 #define MXC_F_FLC_CTRL_PENDING_POS 24
group-onsemi 0:098463de4c5d 134 #define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS))
group-onsemi 0:098463de4c5d 135 #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25
group-onsemi 0:098463de4c5d 136 #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS))
group-onsemi 0:098463de4c5d 137 #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27
group-onsemi 0:098463de4c5d 138 #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS))
group-onsemi 0:098463de4c5d 139 #define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28
group-onsemi 0:098463de4c5d 140 #define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS))
group-onsemi 0:098463de4c5d 141
group-onsemi 0:098463de4c5d 142 #define MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS 0
group-onsemi 0:098463de4c5d 143 #define MXC_F_FLC_INTR_FLASH_OP_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS))
group-onsemi 0:098463de4c5d 144 #define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS 1
group-onsemi 0:098463de4c5d 145 #define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS))
group-onsemi 0:098463de4c5d 146 #define MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS 9
group-onsemi 0:098463de4c5d 147 #define MXC_F_FLC_INTR_FLASH_OP_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS))
group-onsemi 0:098463de4c5d 148 #define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS 10
group-onsemi 0:098463de4c5d 149 #define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS))
group-onsemi 0:098463de4c5d 150
group-onsemi 0:098463de4c5d 151 #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8
group-onsemi 0:098463de4c5d 152 #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS))
group-onsemi 0:098463de4c5d 153 #define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0
group-onsemi 0:098463de4c5d 154 #define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS))
group-onsemi 0:098463de4c5d 155
group-onsemi 0:098463de4c5d 156 #define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS 0
group-onsemi 0:098463de4c5d 157 #define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS))
group-onsemi 0:098463de4c5d 158 #define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS 1
group-onsemi 0:098463de4c5d 159 #define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS))
group-onsemi 0:098463de4c5d 160 #define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3
group-onsemi 0:098463de4c5d 161 #define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS))
group-onsemi 0:098463de4c5d 162
group-onsemi 0:098463de4c5d 163 #define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0
group-onsemi 0:098463de4c5d 164 #define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS))
group-onsemi 0:098463de4c5d 165 #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8
group-onsemi 0:098463de4c5d 166 #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS))
group-onsemi 0:098463de4c5d 167 #define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 31
group-onsemi 0:098463de4c5d 168 #define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS))
group-onsemi 0:098463de4c5d 169
group-onsemi 0:098463de4c5d 170 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0
group-onsemi 0:098463de4c5d 171 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS))
group-onsemi 0:098463de4c5d 172 #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1
group-onsemi 0:098463de4c5d 173 #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS))
group-onsemi 0:098463de4c5d 174 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2
group-onsemi 0:098463de4c5d 175 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS))
group-onsemi 0:098463de4c5d 176 #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3
group-onsemi 0:098463de4c5d 177 #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS))
group-onsemi 0:098463de4c5d 178
group-onsemi 0:098463de4c5d 179 #define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0
group-onsemi 0:098463de4c5d 180 #define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_FLASH_LVE_POS))
group-onsemi 0:098463de4c5d 181 #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8
group-onsemi 0:098463de4c5d 182 #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS))
group-onsemi 0:098463de4c5d 183
group-onsemi 0:098463de4c5d 184 #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0
group-onsemi 0:098463de4c5d 185 #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS))
group-onsemi 0:098463de4c5d 186 #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1
group-onsemi 0:098463de4c5d 187 #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS))
group-onsemi 0:098463de4c5d 188 #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2
group-onsemi 0:098463de4c5d 189 #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS))
group-onsemi 0:098463de4c5d 190 #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3
group-onsemi 0:098463de4c5d 191 #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS))
group-onsemi 0:098463de4c5d 192
group-onsemi 0:098463de4c5d 193 #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0
group-onsemi 0:098463de4c5d 194 #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS))
group-onsemi 0:098463de4c5d 195 #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1
group-onsemi 0:098463de4c5d 196 #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS))
group-onsemi 0:098463de4c5d 197 #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2
group-onsemi 0:098463de4c5d 198 #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS))
group-onsemi 0:098463de4c5d 199 #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3
group-onsemi 0:098463de4c5d 200 #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS))
group-onsemi 0:098463de4c5d 201
group-onsemi 0:098463de4c5d 202 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 203 }
group-onsemi 0:098463de4c5d 204 #endif
group-onsemi 0:098463de4c5d 205
group-onsemi 0:098463de4c5d 206 /**
group-onsemi 0:098463de4c5d 207 * @}
group-onsemi 0:098463de4c5d 208 */
group-onsemi 0:098463de4c5d 209
group-onsemi 0:098463de4c5d 210 #endif /* _MXC_FLC_REGS_H_ */