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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_mpu.h@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
group-onsemi 0:098463de4c5d 3 * All rights reserved.
group-onsemi 0:098463de4c5d 4 *
group-onsemi 0:098463de4c5d 5 * Redistribution and use in source and binary forms, with or without modification,
group-onsemi 0:098463de4c5d 6 * are permitted provided that the following conditions are met:
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * o Redistributions of source code must retain the above copyright notice, this list
group-onsemi 0:098463de4c5d 9 * of conditions and the following disclaimer.
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * o Redistributions in binary form must reproduce the above copyright notice, this
group-onsemi 0:098463de4c5d 12 * list of conditions and the following disclaimer in the documentation and/or
group-onsemi 0:098463de4c5d 13 * other materials provided with the distribution.
group-onsemi 0:098463de4c5d 14 *
group-onsemi 0:098463de4c5d 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
group-onsemi 0:098463de4c5d 16 * contributors may be used to endorse or promote products derived from this
group-onsemi 0:098463de4c5d 17 * software without specific prior written permission.
group-onsemi 0:098463de4c5d 18 *
group-onsemi 0:098463de4c5d 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
group-onsemi 0:098463de4c5d 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
group-onsemi 0:098463de4c5d 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
group-onsemi 0:098463de4c5d 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
group-onsemi 0:098463de4c5d 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
group-onsemi 0:098463de4c5d 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
group-onsemi 0:098463de4c5d 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
group-onsemi 0:098463de4c5d 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
group-onsemi 0:098463de4c5d 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
group-onsemi 0:098463de4c5d 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
group-onsemi 0:098463de4c5d 29 */
group-onsemi 0:098463de4c5d 30 #ifndef _FSL_MPU_H_
group-onsemi 0:098463de4c5d 31 #define _FSL_MPU_H_
group-onsemi 0:098463de4c5d 32
group-onsemi 0:098463de4c5d 33 #include "fsl_common.h"
group-onsemi 0:098463de4c5d 34
group-onsemi 0:098463de4c5d 35 /*!
group-onsemi 0:098463de4c5d 36 * @addtogroup mpu
group-onsemi 0:098463de4c5d 37 * @{
group-onsemi 0:098463de4c5d 38 */
group-onsemi 0:098463de4c5d 39
group-onsemi 0:098463de4c5d 40 /*! @file */
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 /*******************************************************************************
group-onsemi 0:098463de4c5d 43 * Definitions
group-onsemi 0:098463de4c5d 44 ******************************************************************************/
group-onsemi 0:098463de4c5d 45
group-onsemi 0:098463de4c5d 46 /*! @name Driver version */
group-onsemi 0:098463de4c5d 47 /*@{*/
group-onsemi 0:098463de4c5d 48 /*! @brief MPU driver version 2.0.0. */
group-onsemi 0:098463de4c5d 49 #define FSL_MPU_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
group-onsemi 0:098463de4c5d 50 /*@}*/
group-onsemi 0:098463de4c5d 51
group-onsemi 0:098463de4c5d 52 /*! @brief MPU low master bit shift. */
group-onsemi 0:098463de4c5d 53 #define MPU_WORD_LOW_MASTER_SHIFT(n) (n * 6)
group-onsemi 0:098463de4c5d 54
group-onsemi 0:098463de4c5d 55 /*! @brief MPU low master bit mask. */
group-onsemi 0:098463de4c5d 56 #define MPU_WORD_LOW_MASTER_MASK(n) (0x1Fu << MPU_WORD_LOW_MASTER_SHIFT(n))
group-onsemi 0:098463de4c5d 57
group-onsemi 0:098463de4c5d 58 /*! @brief MPU low master bit width. */
group-onsemi 0:098463de4c5d 59 #define MPU_WORD_LOW_MASTER_WIDTH 5
group-onsemi 0:098463de4c5d 60
group-onsemi 0:098463de4c5d 61 /*! @brief MPU low master priority setting. */
group-onsemi 0:098463de4c5d 62 #define MPU_WORD_LOW_MASTER(n, x) \
group-onsemi 0:098463de4c5d 63 (((uint32_t)(((uint32_t)(x)) << MPU_WORD_LOW_MASTER_SHIFT(n))) & MPU_WORD_LOW_MASTER_MASK(n))
group-onsemi 0:098463de4c5d 64
group-onsemi 0:098463de4c5d 65 /*! @brief MPU low master process enable bit shift. */
group-onsemi 0:098463de4c5d 66 #define MPU_LOW_MASTER_PE_SHIFT(n) (n * 6 + 5)
group-onsemi 0:098463de4c5d 67
group-onsemi 0:098463de4c5d 68 /*! @brief MPU low master process enable bit mask. */
group-onsemi 0:098463de4c5d 69 #define MPU_LOW_MASTER_PE_MASK(n) (0x1u << MPU_LOW_MASTER_PE_SHIFT(n))
group-onsemi 0:098463de4c5d 70
group-onsemi 0:098463de4c5d 71 /*! @brief MPU low master process enable width. */
group-onsemi 0:098463de4c5d 72 #define MPU_WORD_MASTER_PE_WIDTH 1
group-onsemi 0:098463de4c5d 73
group-onsemi 0:098463de4c5d 74 /*! @brief MPU low master process enable setting. */
group-onsemi 0:098463de4c5d 75 #define MPU_WORD_MASTER_PE(n, x) \
group-onsemi 0:098463de4c5d 76 (((uint32_t)(((uint32_t)(x)) << MPU_LOW_MASTER_PE_SHIFT(n))) & MPU_LOW_MASTER_PE_MASK(n))
group-onsemi 0:098463de4c5d 77
group-onsemi 0:098463de4c5d 78 /*! @brief MPU high master bit shift. */
group-onsemi 0:098463de4c5d 79 #define MPU_WORD_HIGH_MASTER_SHIFT(n) (n * 2 + 24)
group-onsemi 0:098463de4c5d 80
group-onsemi 0:098463de4c5d 81 /*! @brief MPU high master bit mask. */
group-onsemi 0:098463de4c5d 82 #define MPU_WORD_HIGH_MASTER_MASK(n) (0x03u << MPU_WORD_HIGH_MASTER_SHIFT(n))
group-onsemi 0:098463de4c5d 83
group-onsemi 0:098463de4c5d 84 /*! @brief MPU high master bit width. */
group-onsemi 0:098463de4c5d 85 #define MPU_WORD_HIGH_MASTER_WIDTH 2
group-onsemi 0:098463de4c5d 86
group-onsemi 0:098463de4c5d 87 /*! @brief MPU high master priority setting. */
group-onsemi 0:098463de4c5d 88 #define MPU_WORD_HIGH_MASTER(n, x) \
group-onsemi 0:098463de4c5d 89 (((uint32_t)(((uint32_t)(x)) << MPU_WORD_HIGH_MASTER_SHIFT(n))) & MPU_WORD_HIGH_MASTER_MASK(n))
group-onsemi 0:098463de4c5d 90
group-onsemi 0:098463de4c5d 91 /*! @brief MPU region number. */
group-onsemi 0:098463de4c5d 92 typedef enum _mpu_region_num
group-onsemi 0:098463de4c5d 93 {
group-onsemi 0:098463de4c5d 94 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 0U
group-onsemi 0:098463de4c5d 95 kMPU_RegionNum00 = 0U, /*!< MPU region number 0. */
group-onsemi 0:098463de4c5d 96 #endif
group-onsemi 0:098463de4c5d 97 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 1U
group-onsemi 0:098463de4c5d 98 kMPU_RegionNum01 = 1U, /*!< MPU region number 1. */
group-onsemi 0:098463de4c5d 99 #endif
group-onsemi 0:098463de4c5d 100 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 2U
group-onsemi 0:098463de4c5d 101 kMPU_RegionNum02 = 2U, /*!< MPU region number 2. */
group-onsemi 0:098463de4c5d 102 #endif
group-onsemi 0:098463de4c5d 103 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 3U
group-onsemi 0:098463de4c5d 104 kMPU_RegionNum03 = 3U, /*!< MPU region number 3. */
group-onsemi 0:098463de4c5d 105 #endif
group-onsemi 0:098463de4c5d 106 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 4U
group-onsemi 0:098463de4c5d 107 kMPU_RegionNum04 = 4U, /*!< MPU region number 4. */
group-onsemi 0:098463de4c5d 108 #endif
group-onsemi 0:098463de4c5d 109 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 5U
group-onsemi 0:098463de4c5d 110 kMPU_RegionNum05 = 5U, /*!< MPU region number 5. */
group-onsemi 0:098463de4c5d 111 #endif
group-onsemi 0:098463de4c5d 112 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 6U
group-onsemi 0:098463de4c5d 113 kMPU_RegionNum06 = 6U, /*!< MPU region number 6. */
group-onsemi 0:098463de4c5d 114 #endif
group-onsemi 0:098463de4c5d 115 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 7U
group-onsemi 0:098463de4c5d 116 kMPU_RegionNum07 = 7U, /*!< MPU region number 7. */
group-onsemi 0:098463de4c5d 117 #endif
group-onsemi 0:098463de4c5d 118 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 8U
group-onsemi 0:098463de4c5d 119 kMPU_RegionNum08 = 8U, /*!< MPU region number 8. */
group-onsemi 0:098463de4c5d 120 #endif
group-onsemi 0:098463de4c5d 121 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 9U
group-onsemi 0:098463de4c5d 122 kMPU_RegionNum09 = 9U, /*!< MPU region number 9. */
group-onsemi 0:098463de4c5d 123 #endif
group-onsemi 0:098463de4c5d 124 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 10U
group-onsemi 0:098463de4c5d 125 kMPU_RegionNum10 = 10U, /*!< MPU region number 10. */
group-onsemi 0:098463de4c5d 126 #endif
group-onsemi 0:098463de4c5d 127 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 11U
group-onsemi 0:098463de4c5d 128 kMPU_RegionNum11 = 11U, /*!< MPU region number 11. */
group-onsemi 0:098463de4c5d 129 #endif
group-onsemi 0:098463de4c5d 130 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 12U
group-onsemi 0:098463de4c5d 131 kMPU_RegionNum12 = 12U, /*!< MPU region number 12. */
group-onsemi 0:098463de4c5d 132 #endif
group-onsemi 0:098463de4c5d 133 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 13U
group-onsemi 0:098463de4c5d 134 kMPU_RegionNum13 = 13U, /*!< MPU region number 13. */
group-onsemi 0:098463de4c5d 135 #endif
group-onsemi 0:098463de4c5d 136 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 14U
group-onsemi 0:098463de4c5d 137 kMPU_RegionNum14 = 14U, /*!< MPU region number 14. */
group-onsemi 0:098463de4c5d 138 #endif
group-onsemi 0:098463de4c5d 139 #if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 15U
group-onsemi 0:098463de4c5d 140 kMPU_RegionNum15 = 15U, /*!< MPU region number 15. */
group-onsemi 0:098463de4c5d 141 #endif
group-onsemi 0:098463de4c5d 142 } mpu_region_num_t;
group-onsemi 0:098463de4c5d 143
group-onsemi 0:098463de4c5d 144 /*! @brief MPU master number. */
group-onsemi 0:098463de4c5d 145 typedef enum _mpu_master
group-onsemi 0:098463de4c5d 146 {
group-onsemi 0:098463de4c5d 147 #if FSL_FEATURE_MPU_HAS_MASTER0
group-onsemi 0:098463de4c5d 148 kMPU_Master0 = 0U, /*!< MPU master core. */
group-onsemi 0:098463de4c5d 149 #endif
group-onsemi 0:098463de4c5d 150 #if FSL_FEATURE_MPU_HAS_MASTER1
group-onsemi 0:098463de4c5d 151 kMPU_Master1 = 1U, /*!< MPU master defined in SoC. */
group-onsemi 0:098463de4c5d 152 #endif
group-onsemi 0:098463de4c5d 153 #if FSL_FEATURE_MPU_HAS_MASTER2
group-onsemi 0:098463de4c5d 154 kMPU_Master2 = 2U, /*!< MPU master defined in SoC. */
group-onsemi 0:098463de4c5d 155 #endif
group-onsemi 0:098463de4c5d 156 #if FSL_FEATURE_MPU_HAS_MASTER3
group-onsemi 0:098463de4c5d 157 kMPU_Master3 = 3U, /*!< MPU master defined in SoC. */
group-onsemi 0:098463de4c5d 158 #endif
group-onsemi 0:098463de4c5d 159 #if FSL_FEATURE_MPU_HAS_MASTER4
group-onsemi 0:098463de4c5d 160 kMPU_Master4 = 4U, /*!< MPU master defined in SoC. */
group-onsemi 0:098463de4c5d 161 #endif
group-onsemi 0:098463de4c5d 162 #if FSL_FEATURE_MPU_HAS_MASTER5
group-onsemi 0:098463de4c5d 163 kMPU_Master5 = 5U, /*!< MPU master defined in SoC. */
group-onsemi 0:098463de4c5d 164 #endif
group-onsemi 0:098463de4c5d 165 #if FSL_FEATURE_MPU_HAS_MASTER6
group-onsemi 0:098463de4c5d 166 kMPU_Master6 = 6U, /*!< MPU master defined in SoC. */
group-onsemi 0:098463de4c5d 167 #endif
group-onsemi 0:098463de4c5d 168 #if FSL_FEATURE_MPU_HAS_MASTER7
group-onsemi 0:098463de4c5d 169 kMPU_Master7 = 7U /*!< MPU master defined in SoC. */
group-onsemi 0:098463de4c5d 170 #endif
group-onsemi 0:098463de4c5d 171 } mpu_master_t;
group-onsemi 0:098463de4c5d 172
group-onsemi 0:098463de4c5d 173 /*! @brief Describes the number of MPU regions. */
group-onsemi 0:098463de4c5d 174 typedef enum _mpu_region_total_num
group-onsemi 0:098463de4c5d 175 {
group-onsemi 0:098463de4c5d 176 kMPU_8Regions = 0x0U, /*!< MPU supports 8 regions. */
group-onsemi 0:098463de4c5d 177 kMPU_12Regions = 0x1U, /*!< MPU supports 12 regions. */
group-onsemi 0:098463de4c5d 178 kMPU_16Regions = 0x2U /*!< MPU supports 16 regions. */
group-onsemi 0:098463de4c5d 179 } mpu_region_total_num_t;
group-onsemi 0:098463de4c5d 180
group-onsemi 0:098463de4c5d 181 /*! @brief MPU slave port number. */
group-onsemi 0:098463de4c5d 182 typedef enum _mpu_slave
group-onsemi 0:098463de4c5d 183 {
group-onsemi 0:098463de4c5d 184 kMPU_Slave0 = 4U, /*!< MPU slave port 0. */
group-onsemi 0:098463de4c5d 185 kMPU_Slave1 = 3U, /*!< MPU slave port 1. */
group-onsemi 0:098463de4c5d 186 kMPU_Slave2 = 2U, /*!< MPU slave port 2. */
group-onsemi 0:098463de4c5d 187 kMPU_Slave3 = 1U, /*!< MPU slave port 3. */
group-onsemi 0:098463de4c5d 188 kMPU_Slave4 = 0U /*!< MPU slave port 4. */
group-onsemi 0:098463de4c5d 189 } mpu_slave_t;
group-onsemi 0:098463de4c5d 190
group-onsemi 0:098463de4c5d 191 /*! @brief MPU error access control detail. */
group-onsemi 0:098463de4c5d 192 typedef enum _mpu_err_access_control
group-onsemi 0:098463de4c5d 193 {
group-onsemi 0:098463de4c5d 194 kMPU_NoRegionHit = 0U, /*!< No region hit error. */
group-onsemi 0:098463de4c5d 195 kMPU_NoneOverlappRegion = 1U, /*!< Access single region error. */
group-onsemi 0:098463de4c5d 196 kMPU_OverlappRegion = 2U /*!< Access overlapping region error. */
group-onsemi 0:098463de4c5d 197 } mpu_err_access_control_t;
group-onsemi 0:098463de4c5d 198
group-onsemi 0:098463de4c5d 199 /*! @brief MPU error access type. */
group-onsemi 0:098463de4c5d 200 typedef enum _mpu_err_access_type
group-onsemi 0:098463de4c5d 201 {
group-onsemi 0:098463de4c5d 202 kMPU_ErrTypeRead = 0U, /*!< MPU error access type --- read. */
group-onsemi 0:098463de4c5d 203 kMPU_ErrTypeWrite = 1U /*!< MPU error access type --- write. */
group-onsemi 0:098463de4c5d 204 } mpu_err_access_type_t;
group-onsemi 0:098463de4c5d 205
group-onsemi 0:098463de4c5d 206 /*! @brief MPU access error attributes.*/
group-onsemi 0:098463de4c5d 207 typedef enum _mpu_err_attributes
group-onsemi 0:098463de4c5d 208 {
group-onsemi 0:098463de4c5d 209 kMPU_InstructionAccessInUserMode = 0U, /*!< Access instruction error in user mode. */
group-onsemi 0:098463de4c5d 210 kMPU_DataAccessInUserMode = 1U, /*!< Access data error in user mode. */
group-onsemi 0:098463de4c5d 211 kMPU_InstructionAccessInSupervisorMode = 2U, /*!< Access instruction error in supervisor mode. */
group-onsemi 0:098463de4c5d 212 kMPU_DataAccessInSupervisorMode = 3U /*!< Access data error in supervisor mode. */
group-onsemi 0:098463de4c5d 213 } mpu_err_attributes_t;
group-onsemi 0:098463de4c5d 214
group-onsemi 0:098463de4c5d 215 /*! @brief MPU access rights in supervisor mode for master port 0 ~ port 3. */
group-onsemi 0:098463de4c5d 216 typedef enum _mpu_supervisor_access_rights
group-onsemi 0:098463de4c5d 217 {
group-onsemi 0:098463de4c5d 218 kMPU_SupervisorReadWriteExecute = 0U, /*!< Read write and execute operations are allowed in supervisor mode. */
group-onsemi 0:098463de4c5d 219 kMPU_SupervisorReadExecute = 1U, /*!< Read and execute operations are allowed in supervisor mode. */
group-onsemi 0:098463de4c5d 220 kMPU_SupervisorReadWrite = 2U, /*!< Read write operations are allowed in supervisor mode. */
group-onsemi 0:098463de4c5d 221 kMPU_SupervisorEqualToUsermode = 3U /*!< Access permission equal to user mode. */
group-onsemi 0:098463de4c5d 222 } mpu_supervisor_access_rights_t;
group-onsemi 0:098463de4c5d 223
group-onsemi 0:098463de4c5d 224 /*! @brief MPU access rights in user mode for master port 0 ~ port 3. */
group-onsemi 0:098463de4c5d 225 typedef enum _mpu_user_access_rights
group-onsemi 0:098463de4c5d 226 {
group-onsemi 0:098463de4c5d 227 kMPU_UserNoAccessRights = 0U, /*!< No access allowed in user mode. */
group-onsemi 0:098463de4c5d 228 kMPU_UserExecute = 1U, /*!< Execute operation is allowed in user mode. */
group-onsemi 0:098463de4c5d 229 kMPU_UserWrite = 2U, /*!< Write operation is allowed in user mode. */
group-onsemi 0:098463de4c5d 230 kMPU_UserWriteExecute = 3U, /*!< Write and execute operations are allowed in user mode. */
group-onsemi 0:098463de4c5d 231 kMPU_UserRead = 4U, /*!< Read is allowed in user mode. */
group-onsemi 0:098463de4c5d 232 kMPU_UserReadExecute = 5U, /*!< Read and execute operations are allowed in user mode. */
group-onsemi 0:098463de4c5d 233 kMPU_UserReadWrite = 6U, /*!< Read and write operations are allowed in user mode. */
group-onsemi 0:098463de4c5d 234 kMPU_UserReadWriteExecute = 7U /*!< Read write and execute operations are allowed in user mode. */
group-onsemi 0:098463de4c5d 235 } mpu_user_access_rights_t;
group-onsemi 0:098463de4c5d 236
group-onsemi 0:098463de4c5d 237 /*! @brief MPU hardware basic information. */
group-onsemi 0:098463de4c5d 238 typedef struct _mpu_hardware_info
group-onsemi 0:098463de4c5d 239 {
group-onsemi 0:098463de4c5d 240 uint8_t hardwareRevisionLevel; /*!< Specifies the MPU's hardware and definition reversion level. */
group-onsemi 0:098463de4c5d 241 uint8_t slavePortsNumbers; /*!< Specifies the number of slave ports connected to MPU. */
group-onsemi 0:098463de4c5d 242 mpu_region_total_num_t regionsNumbers; /*!< Indicates the number of region descriptors implemented. */
group-onsemi 0:098463de4c5d 243 } mpu_hardware_info_t;
group-onsemi 0:098463de4c5d 244
group-onsemi 0:098463de4c5d 245 /*! @brief MPU detail error access information. */
group-onsemi 0:098463de4c5d 246 typedef struct _mpu_access_err_info
group-onsemi 0:098463de4c5d 247 {
group-onsemi 0:098463de4c5d 248 mpu_master_t master; /*!< Access error master. */
group-onsemi 0:098463de4c5d 249 mpu_err_attributes_t attributes; /*!< Access error attributes. */
group-onsemi 0:098463de4c5d 250 mpu_err_access_type_t accessType; /*!< Access error type. */
group-onsemi 0:098463de4c5d 251 mpu_err_access_control_t accessControl; /*!< Access error control. */
group-onsemi 0:098463de4c5d 252 uint32_t address; /*!< Access error address. */
group-onsemi 0:098463de4c5d 253 #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
group-onsemi 0:098463de4c5d 254 uint8_t processorIdentification; /*!< Access error processor identification. */
group-onsemi 0:098463de4c5d 255 #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
group-onsemi 0:098463de4c5d 256 } mpu_access_err_info_t;
group-onsemi 0:098463de4c5d 257
group-onsemi 0:098463de4c5d 258 /*! @brief MPU access rights for low master master port 0 ~ port 3. */
group-onsemi 0:098463de4c5d 259 typedef struct _mpu_low_masters_access_rights
group-onsemi 0:098463de4c5d 260 {
group-onsemi 0:098463de4c5d 261 mpu_supervisor_access_rights_t superAccessRights; /*!< Master access rights in supervisor mode. */
group-onsemi 0:098463de4c5d 262 mpu_user_access_rights_t userAccessRights; /*!< Master access rights in user mode. */
group-onsemi 0:098463de4c5d 263 #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
group-onsemi 0:098463de4c5d 264 bool processIdentifierEnable; /*!< Enables or disables process identifier. */
group-onsemi 0:098463de4c5d 265 #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
group-onsemi 0:098463de4c5d 266 } mpu_low_masters_access_rights_t;
group-onsemi 0:098463de4c5d 267
group-onsemi 0:098463de4c5d 268 /*! @brief MPU access rights mode for high master port 4 ~ port 7. */
group-onsemi 0:098463de4c5d 269 typedef struct _mpu_high_masters_access_rights
group-onsemi 0:098463de4c5d 270 {
group-onsemi 0:098463de4c5d 271 bool writeEnable; /*!< Enables or disables write permission. */
group-onsemi 0:098463de4c5d 272 bool readEnable; /*!< Enables or disables read permission. */
group-onsemi 0:098463de4c5d 273 } mpu_high_masters_access_rights_t;
group-onsemi 0:098463de4c5d 274
group-onsemi 0:098463de4c5d 275 /*!
group-onsemi 0:098463de4c5d 276 * @brief MPU region configuration structure.
group-onsemi 0:098463de4c5d 277 *
group-onsemi 0:098463de4c5d 278 * This structure is used to configure the regionNum region.
group-onsemi 0:098463de4c5d 279 * The accessRights1[0] ~ accessRights1[3] are used to configure the four low master
group-onsemi 0:098463de4c5d 280 * numbers: master 0 ~ master 3. The accessRights2[0] ~ accessRights2[3] are
group-onsemi 0:098463de4c5d 281 * used to configure the four high master numbers: master 4 ~ master 7.
group-onsemi 0:098463de4c5d 282 * The master port assignment is the chip configuration. Normally, the core is the
group-onsemi 0:098463de4c5d 283 * master 0, debugger is the master 1.
group-onsemi 0:098463de4c5d 284 * Note: MPU assigns a priority scheme where the debugger is treated as the highest
group-onsemi 0:098463de4c5d 285 * priority master followed by the core and then all the remaining masters.
group-onsemi 0:098463de4c5d 286 * MPU protection does not allow writes from the core to affect the "regionNum 0" start
group-onsemi 0:098463de4c5d 287 * and end address nor the permissions associated with the debugger. It can only write
group-onsemi 0:098463de4c5d 288 * the permission fields associated with the other masters. This protection guarantee
group-onsemi 0:098463de4c5d 289 * the debugger always has access to the entire address space and those rights can't
group-onsemi 0:098463de4c5d 290 * be changed by the core or any other bus master. Prepare
group-onsemi 0:098463de4c5d 291 * the region configuration when regionNum is kMPU_RegionNum00.
group-onsemi 0:098463de4c5d 292 */
group-onsemi 0:098463de4c5d 293 typedef struct _mpu_region_config
group-onsemi 0:098463de4c5d 294 {
group-onsemi 0:098463de4c5d 295 mpu_region_num_t regionNum; /*!< MPU region number. */
group-onsemi 0:098463de4c5d 296 uint32_t startAddress; /*!< Memory region start address. Note: bit0 ~ bit4 always be marked as 0 by MPU. The actual
group-onsemi 0:098463de4c5d 297 start address is 0-modulo-32 byte address. */
group-onsemi 0:098463de4c5d 298 uint32_t endAddress; /*!< Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU. The actual end
group-onsemi 0:098463de4c5d 299 address is 31-modulo-32 byte address. */
group-onsemi 0:098463de4c5d 300 mpu_low_masters_access_rights_t accessRights1[4]; /*!< Low masters access permission. */
group-onsemi 0:098463de4c5d 301 mpu_high_masters_access_rights_t accessRights2[4]; /*!< High masters access permission. */
group-onsemi 0:098463de4c5d 302 #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
group-onsemi 0:098463de4c5d 303 uint8_t processIdentifier; /*!< Process identifier used when "processIdentifierEnable" set with true. */
group-onsemi 0:098463de4c5d 304 uint8_t
group-onsemi 0:098463de4c5d 305 processIdMask; /*!< Process identifier mask. The setting bit will ignore the same bit in process identifier. */
group-onsemi 0:098463de4c5d 306 #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
group-onsemi 0:098463de4c5d 307 } mpu_region_config_t;
group-onsemi 0:098463de4c5d 308
group-onsemi 0:098463de4c5d 309 /*!
group-onsemi 0:098463de4c5d 310 * @brief The configuration structure for the MPU initialization.
group-onsemi 0:098463de4c5d 311 *
group-onsemi 0:098463de4c5d 312 * This structure is used when calling the MPU_Init function.
group-onsemi 0:098463de4c5d 313 */
group-onsemi 0:098463de4c5d 314 typedef struct _mpu_config
group-onsemi 0:098463de4c5d 315 {
group-onsemi 0:098463de4c5d 316 mpu_region_config_t regionConfig; /*!< region access permission. */
group-onsemi 0:098463de4c5d 317 struct _mpu_config *next; /*!< pointer to the next structure. */
group-onsemi 0:098463de4c5d 318 } mpu_config_t;
group-onsemi 0:098463de4c5d 319
group-onsemi 0:098463de4c5d 320 /*******************************************************************************
group-onsemi 0:098463de4c5d 321 * API
group-onsemi 0:098463de4c5d 322 ******************************************************************************/
group-onsemi 0:098463de4c5d 323
group-onsemi 0:098463de4c5d 324 #if defined(__cplusplus)
group-onsemi 0:098463de4c5d 325 extern "C" {
group-onsemi 0:098463de4c5d 326 #endif /* _cplusplus */
group-onsemi 0:098463de4c5d 327
group-onsemi 0:098463de4c5d 328 /*!
group-onsemi 0:098463de4c5d 329 * @name Initialization and deinitialization
group-onsemi 0:098463de4c5d 330 * @{
group-onsemi 0:098463de4c5d 331 */
group-onsemi 0:098463de4c5d 332
group-onsemi 0:098463de4c5d 333 /*!
group-onsemi 0:098463de4c5d 334 * @brief Initializes the MPU with the user configuration structure.
group-onsemi 0:098463de4c5d 335 *
group-onsemi 0:098463de4c5d 336 * This function configures the MPU module with the user-defined configuration.
group-onsemi 0:098463de4c5d 337 *
group-onsemi 0:098463de4c5d 338 * @param base MPU peripheral base address.
group-onsemi 0:098463de4c5d 339 * @param config The pointer to the configuration structure.
group-onsemi 0:098463de4c5d 340 */
group-onsemi 0:098463de4c5d 341 void MPU_Init(MPU_Type *base, const mpu_config_t *config);
group-onsemi 0:098463de4c5d 342
group-onsemi 0:098463de4c5d 343 /*!
group-onsemi 0:098463de4c5d 344 * @brief Deinitializes the MPU regions.
group-onsemi 0:098463de4c5d 345 *
group-onsemi 0:098463de4c5d 346 * @param base MPU peripheral base address.
group-onsemi 0:098463de4c5d 347 */
group-onsemi 0:098463de4c5d 348 void MPU_Deinit(MPU_Type *base);
group-onsemi 0:098463de4c5d 349
group-onsemi 0:098463de4c5d 350 /* @}*/
group-onsemi 0:098463de4c5d 351
group-onsemi 0:098463de4c5d 352 /*!
group-onsemi 0:098463de4c5d 353 * @name Basic Control Operations
group-onsemi 0:098463de4c5d 354 * @{
group-onsemi 0:098463de4c5d 355 */
group-onsemi 0:098463de4c5d 356
group-onsemi 0:098463de4c5d 357 /*!
group-onsemi 0:098463de4c5d 358 * @brief Enables/disables the MPU globally.
group-onsemi 0:098463de4c5d 359 *
group-onsemi 0:098463de4c5d 360 * Call this API to enable or disable the MPU module.
group-onsemi 0:098463de4c5d 361 *
group-onsemi 0:098463de4c5d 362 * @param base MPU peripheral base address.
group-onsemi 0:098463de4c5d 363 * @param enable True enable MPU, false disable MPU.
group-onsemi 0:098463de4c5d 364 */
group-onsemi 0:098463de4c5d 365 static inline void MPU_Enable(MPU_Type *base, bool enable)
group-onsemi 0:098463de4c5d 366 {
group-onsemi 0:098463de4c5d 367 if (enable)
group-onsemi 0:098463de4c5d 368 {
group-onsemi 0:098463de4c5d 369 /* Enable the MPU globally. */
group-onsemi 0:098463de4c5d 370 base->CESR |= MPU_CESR_VLD_MASK;
group-onsemi 0:098463de4c5d 371 }
group-onsemi 0:098463de4c5d 372 else
group-onsemi 0:098463de4c5d 373 { /* Disable the MPU globally. */
group-onsemi 0:098463de4c5d 374 base->CESR &= ~MPU_CESR_VLD_MASK;
group-onsemi 0:098463de4c5d 375 }
group-onsemi 0:098463de4c5d 376 }
group-onsemi 0:098463de4c5d 377
group-onsemi 0:098463de4c5d 378 /*!
group-onsemi 0:098463de4c5d 379 * @brief Enables/disables the MPU for a special region.
group-onsemi 0:098463de4c5d 380 *
group-onsemi 0:098463de4c5d 381 * When MPU is enabled, call this API to disable an unused region
group-onsemi 0:098463de4c5d 382 * of an enabled MPU. Call this API to minimize the power dissipation.
group-onsemi 0:098463de4c5d 383 *
group-onsemi 0:098463de4c5d 384 * @param base MPU peripheral base address.
group-onsemi 0:098463de4c5d 385 * @param number MPU region number.
group-onsemi 0:098463de4c5d 386 * @param enable True enable the special region MPU, false disable the special region MPU.
group-onsemi 0:098463de4c5d 387 */
group-onsemi 0:098463de4c5d 388 static inline void MPU_RegionEnable(MPU_Type *base, mpu_region_num_t number, bool enable)
group-onsemi 0:098463de4c5d 389 {
group-onsemi 0:098463de4c5d 390 if (enable)
group-onsemi 0:098463de4c5d 391 {
group-onsemi 0:098463de4c5d 392 /* Enable the #number region MPU. */
group-onsemi 0:098463de4c5d 393 base->WORD[number][3] |= MPU_WORD_VLD_MASK;
group-onsemi 0:098463de4c5d 394 }
group-onsemi 0:098463de4c5d 395 else
group-onsemi 0:098463de4c5d 396 { /* Disable the #number region MPU. */
group-onsemi 0:098463de4c5d 397 base->WORD[number][3] &= ~MPU_WORD_VLD_MASK;
group-onsemi 0:098463de4c5d 398 }
group-onsemi 0:098463de4c5d 399 }
group-onsemi 0:098463de4c5d 400
group-onsemi 0:098463de4c5d 401 /*!
group-onsemi 0:098463de4c5d 402 * @brief Gets the MPU basic hardware information.
group-onsemi 0:098463de4c5d 403 *
group-onsemi 0:098463de4c5d 404 * @param base MPU peripheral base address.
group-onsemi 0:098463de4c5d 405 * @param hardwareInform The pointer to the MPU hardware information structure. See "mpu_hardware_info_t".
group-onsemi 0:098463de4c5d 406 */
group-onsemi 0:098463de4c5d 407 void MPU_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *hardwareInform);
group-onsemi 0:098463de4c5d 408
group-onsemi 0:098463de4c5d 409 /*!
group-onsemi 0:098463de4c5d 410 * @brief Sets the MPU region.
group-onsemi 0:098463de4c5d 411 *
group-onsemi 0:098463de4c5d 412 * Note: Due to the MPU protection, the kMPU_RegionNum00 does not allow writes from the
group-onsemi 0:098463de4c5d 413 * core to affect the start and end address nor the permissions associated with
group-onsemi 0:098463de4c5d 414 * the debugger. It can only write the permission fields associated
group-onsemi 0:098463de4c5d 415 * with the other masters.
group-onsemi 0:098463de4c5d 416 *
group-onsemi 0:098463de4c5d 417 * @param base MPU peripheral base address.
group-onsemi 0:098463de4c5d 418 * @param regionConfig The pointer to the MPU user configuration structure. See "mpu_region_config_t".
group-onsemi 0:098463de4c5d 419 */
group-onsemi 0:098463de4c5d 420 void MPU_SetRegionConfig(MPU_Type *base, const mpu_region_config_t *regionConfig);
group-onsemi 0:098463de4c5d 421
group-onsemi 0:098463de4c5d 422 /*!
group-onsemi 0:098463de4c5d 423 * @brief Sets the region start and end address.
group-onsemi 0:098463de4c5d 424 *
group-onsemi 0:098463de4c5d 425 * Memory region start address. Note: bit0 ~ bit4 is always marked as 0 by MPU.
group-onsemi 0:098463de4c5d 426 * The actual start address by MPU is 0-modulo-32 byte address.
group-onsemi 0:098463de4c5d 427 * Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU.
group-onsemi 0:098463de4c5d 428 * The actual end address used by MPU is 31-modulo-32 byte address.
group-onsemi 0:098463de4c5d 429 * Note: Due to the MPU protection, the startAddr and endAddr can't be
group-onsemi 0:098463de4c5d 430 * changed by the core when regionNum is "kMPU_RegionNum00".
group-onsemi 0:098463de4c5d 431 *
group-onsemi 0:098463de4c5d 432 * @param base MPU peripheral base address.
group-onsemi 0:098463de4c5d 433 * @param regionNum MPU region number.
group-onsemi 0:098463de4c5d 434 * @param startAddr Region start address.
group-onsemi 0:098463de4c5d 435 * @param endAddr Region end address.
group-onsemi 0:098463de4c5d 436 */
group-onsemi 0:098463de4c5d 437 void MPU_SetRegionAddr(MPU_Type *base, mpu_region_num_t regionNum, uint32_t startAddr, uint32_t endAddr);
group-onsemi 0:098463de4c5d 438
group-onsemi 0:098463de4c5d 439 /*!
group-onsemi 0:098463de4c5d 440 * @brief Sets the MPU region access rights for low master port 0 ~ port 3.
group-onsemi 0:098463de4c5d 441 * This can be used to change the region access rights for any master port for any region.
group-onsemi 0:098463de4c5d 442 *
group-onsemi 0:098463de4c5d 443 * @param base MPU peripheral base address.
group-onsemi 0:098463de4c5d 444 * @param regionNum MPU region number.
group-onsemi 0:098463de4c5d 445 * @param masterNum MPU master number. Should range from kMPU_Master0 ~ kMPU_Master3.
group-onsemi 0:098463de4c5d 446 * @param accessRights The pointer to the MPU access rights configuration. See "mpu_low_masters_access_rights_t".
group-onsemi 0:098463de4c5d 447 */
group-onsemi 0:098463de4c5d 448 void MPU_SetRegionLowMasterAccessRights(MPU_Type *base,
group-onsemi 0:098463de4c5d 449 mpu_region_num_t regionNum,
group-onsemi 0:098463de4c5d 450 mpu_master_t masterNum,
group-onsemi 0:098463de4c5d 451 const mpu_low_masters_access_rights_t *accessRights);
group-onsemi 0:098463de4c5d 452
group-onsemi 0:098463de4c5d 453 /*!
group-onsemi 0:098463de4c5d 454 * @brief Sets the MPU region access rights for high master port 4 ~ port 7.
group-onsemi 0:098463de4c5d 455 * This can be used to change the region access rights for any master port for any region.
group-onsemi 0:098463de4c5d 456 *
group-onsemi 0:098463de4c5d 457 * @param base MPU peripheral base address.
group-onsemi 0:098463de4c5d 458 * @param regionNum MPU region number.
group-onsemi 0:098463de4c5d 459 * @param masterNum MPU master number. Should range from kMPU_Master4 ~ kMPU_Master7.
group-onsemi 0:098463de4c5d 460 * @param accessRights The pointer to the MPU access rights configuration. See "mpu_high_masters_access_rights_t".
group-onsemi 0:098463de4c5d 461 */
group-onsemi 0:098463de4c5d 462 void MPU_SetRegionHighMasterAccessRights(MPU_Type *base,
group-onsemi 0:098463de4c5d 463 mpu_region_num_t regionNum,
group-onsemi 0:098463de4c5d 464 mpu_master_t masterNum,
group-onsemi 0:098463de4c5d 465 const mpu_high_masters_access_rights_t *accessRights);
group-onsemi 0:098463de4c5d 466
group-onsemi 0:098463de4c5d 467 /*!
group-onsemi 0:098463de4c5d 468 * @brief Gets the numbers of slave ports where errors occur.
group-onsemi 0:098463de4c5d 469 *
group-onsemi 0:098463de4c5d 470 * @param base MPU peripheral base address.
group-onsemi 0:098463de4c5d 471 * @param slaveNum MPU slave port number.
group-onsemi 0:098463de4c5d 472 * @return The slave ports error status.
group-onsemi 0:098463de4c5d 473 * true - error happens in this slave port.
group-onsemi 0:098463de4c5d 474 * false - error didn't happen in this slave port.
group-onsemi 0:098463de4c5d 475 */
group-onsemi 0:098463de4c5d 476 bool MPU_GetSlavePortErrorStatus(MPU_Type *base, mpu_slave_t slaveNum);
group-onsemi 0:098463de4c5d 477
group-onsemi 0:098463de4c5d 478 /*!
group-onsemi 0:098463de4c5d 479 * @brief Gets the MPU detailed error access information.
group-onsemi 0:098463de4c5d 480 *
group-onsemi 0:098463de4c5d 481 * @param base MPU peripheral base address.
group-onsemi 0:098463de4c5d 482 * @param slaveNum MPU slave port number.
group-onsemi 0:098463de4c5d 483 * @param errInform The pointer to the MPU access error information. See "mpu_access_err_info_t".
group-onsemi 0:098463de4c5d 484 */
group-onsemi 0:098463de4c5d 485 void MPU_GetDetailErrorAccessInfo(MPU_Type *base, mpu_slave_t slaveNum, mpu_access_err_info_t *errInform);
group-onsemi 0:098463de4c5d 486
group-onsemi 0:098463de4c5d 487 /* @} */
group-onsemi 0:098463de4c5d 488
group-onsemi 0:098463de4c5d 489 #if defined(__cplusplus)
group-onsemi 0:098463de4c5d 490 }
group-onsemi 0:098463de4c5d 491 #endif
group-onsemi 0:098463de4c5d 492
group-onsemi 0:098463de4c5d 493 /*! @}*/
group-onsemi 0:098463de4c5d 494
group-onsemi 0:098463de4c5d 495 #endif /* _FSL_MPU_H_ */