mbed_example
/
mbed-os-example-qspi
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Diff: main.cpp
- Revision:
- 5:da509493e3e6
- Parent:
- 2:3165b07182ad
- Child:
- 6:3a643419d247
diff -r 61e89e5a19a2 -r da509493e3e6 main.cpp
--- a/main.cpp Mon Sep 03 15:06:54 2018 +0200
+++ b/main.cpp Tue Sep 04 09:46:36 2018 +0200
@@ -33,8 +33,7 @@
#define QSPI_MAX_WAIT_TIME 1000 // 1000 ms
-
-
+#define TEST_FLASH_ADDRESS 0x1000
//#define DEBUG_ON 1
#ifdef DEBUG_ON
@@ -43,31 +42,20 @@
#define VERBOSE_PRINT(x)
#endif
-
bool InitializeFlashMem(QSPI &qspi);
bool WaitForMemReady(QSPI &qspi);
bool SectorErase(QSPI &qspi, unsigned int flash_addr);
-
bool WriteReadQuad(QSPI &qspi, unsigned int flash_addr);
-
bool QuadEnable(QSPI &qspi);
bool QuadDisable(QSPI &qspi);
-#define TEST_FLASH_ADDRESS 0x1000
-
// main() runs in its own thread in the OS
int main()
{
printf(">>> Start...\r\n");
- QSPI myQspi((PinName)QSPI_FLASH1_IO0, (PinName)QSPI_FLASH1_IO1, (PinName)QSPI_FLASH1_IO2, (PinName)QSPI_FLASH1_IO3, (PinName)QSPI_FLASH1_SCK, (PinName)QSPI_FLASH1_CSN);
-
- if (QSPI_STATUS_OK == myQspi.configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0)) {
- printf("[main] Configured QSPI driver succesfully: 1-1-1\r\n");
- } else {
- printf("[main] ERROR: Failed configuring QSPI driver\r\n");
- return -1;
- }
+ QSPI myQspi((PinName)QSPI_FLASH1_IO0, (PinName)QSPI_FLASH1_IO1, (PinName)QSPI_FLASH1_IO2,
+ (PinName)QSPI_FLASH1_IO3, (PinName)QSPI_FLASH1_SCK, (PinName)QSPI_FLASH1_CSN);
if (false == InitializeFlashMem(myQspi)) {
printf("[main] Unable to initialize flash memory, tests failed\r\n");
@@ -79,7 +67,7 @@
return -1;
}
- printf("<<< Done...\r\n");
+ printf("<<< Done...\r\n\r\n");
}
bool WriteReadQuad(QSPI &qspi, unsigned int flash_addr)
@@ -110,14 +98,15 @@
return false;
}
- if (QSPI_STATUS_OK == qspi.configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_QUAD, QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_QUAD, 0)) {
- printf("[WriteReadQuad] Configured QSPI driver succesfully: 1-4-4\r\n");
+ if (QSPI_STATUS_OK == qspi.configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD, QSPI_CFG_ADDR_SIZE_24,
+ QSPI_CFG_BUS_QUAD, QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_QUAD, 0)) {
+ printf("Configured QSPI driver succesfully: 1-4-4\r\n");
} else {
printf("[WriteReadQuad] ERROR: Failed configuring QSPI driver\r\n");
return -1;
}
- printf("[WriteReadQuad] Writing: %s\r\n", tx_buf);
+ printf("Writing: %s\r\n", tx_buf);
result = qspi.write(QSPI_STD_CMD_WRITE_4IO, 0, flash_addr, tx_buf, &buf_len);
if ((result != QSPI_STATUS_OK) || buf_len != sizeof(tx_buf)) {
printf("[WriteReadQuad] ERROR: Write failed\r\n");
@@ -128,8 +117,10 @@
return false;
}
- if (QSPI_STATUS_OK == qspi.configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_QUAD, QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_QUAD, QSPI_READ_4IO_DUMMY_CYCLE)) {
- printf("[WriteReadQuad] Configured QSPI driver succesfully: 1-4-4\r\n");
+ // Set dummy cycle count for read operation
+ if (QSPI_STATUS_OK == qspi.configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD, QSPI_CFG_ADDR_SIZE_24,
+ QSPI_CFG_BUS_QUAD, QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_QUAD, QSPI_READ_4IO_DUMMY_CYCLE)) {
+ printf("Configured QSPI driver succesfully: dummy cycle set to 6\r\n");
} else {
printf("[WriteReadQuad] ERROR: Failed configuring QSPI driver\r\n");
return -1;
@@ -142,18 +133,6 @@
return false;
}
- if (QSPI_STATUS_OK == qspi.configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0)) {
- printf("[WriteReadQuad] Configured QSPI driver succesfully: 1-1-1\r\n");
- } else {
- printf("[WriteReadQuad] ERROR: Failed configuring QSPI driver\r\n");
- return -1;
- }
-
- if (false == QuadDisable(qspi)) {
- printf("[WriteReadQuad] ERROR: Quad disable failed\r\n");
- return false;
- }
-
if (buf_len != sizeof(rx_buf)) {
printf("[WriteReadQuad] ERROR: Unable to read the entire buffer\r\n");
return false;
@@ -173,7 +152,21 @@
printf("\r\n");
return false;
}
- printf("[WriteReadQuad] Read: %s\r\n", rx_buf);
+ printf("Read: %s\r\n", rx_buf);
+
+ // Reset dummy cycle count
+ if (QSPI_STATUS_OK == qspi.configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD, QSPI_CFG_ADDR_SIZE_24,
+ QSPI_CFG_BUS_QUAD, QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_QUAD, 0)) {
+ printf("Configured QSPI driver succesfully: dummy cycle set to 0\r\n");
+ } else {
+ printf("[WriteReadQuad] ERROR: Failed configuring QSPI driver\r\n");
+ return -1;
+ }
+
+ if (false == QuadDisable(qspi)) {
+ printf("[WriteReadQuad] ERROR: Quad disable failed\r\n");
+ return false;
+ }
return true;
}
@@ -287,7 +280,7 @@
printf("ERROR: Reading Status Register failed\r\n");
return false;
}
-
+ // Set wite enable
if (QSPI_STATUS_OK == qspi.command_transfer(QSPI_STD_CMD_WREN, // command to send
-1, // no address to transmit
NULL, 0, // do not transmit
@@ -297,9 +290,8 @@
printf("[QuadEnable] ERROR: Sending WREN command failed\r\n");
return false;
}
-
+ //Set the Status Register to set QE enable bit
reg_data[0] |= (STATUS_BIT_QE);
- //Set the Status Register to set QE enable bit
if (QSPI_STATUS_OK == qspi.command_transfer(QSPI_STD_CMD_WRSR, // command to send
-1, // no address to transmit
reg_data, QSPI_STATUS_REG_SIZE,
@@ -343,9 +335,8 @@
printf("[QuadDisable] ERROR: Sending WREN command failed\r\n");
return false;
}
-
+ //Set the Status Register to reset QE enable bit
reg_data[0] &= ~(STATUS_BIT_QE);
- //Set the Status Register to reset QE enable bit
if (QSPI_STATUS_OK == qspi.command_transfer(QSPI_STD_CMD_WRSR, // command to send
-1, // no address to transmit
reg_data, QSPI_STATUS_REG_SIZE,
