mbed_example
/
mbed-os-example-qspi
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
main.cpp@2:3165b07182ad, 2018-09-03 (annotated)
- Committer:
- Maciej Bocianski
- Date:
- Mon Sep 03 14:02:44 2018 +0200
- Revision:
- 2:3165b07182ad
- Parent:
- 1:cc0165946232
- Child:
- 5:da509493e3e6
example update
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Senthil Ramakrishnan |
0:f741508e07a3 | 1 | #include "mbed.h" |
| Senthil Ramakrishnan |
0:f741508e07a3 | 2 | #include "QSPI.h" |
| Senthil Ramakrishnan |
0:f741508e07a3 | 3 | |
| Senthil Ramakrishnan |
0:f741508e07a3 | 4 | // The below values are command codes defined in Datasheet for MX25R6435F Macronix Flash Memory |
| Maciej Bocianski |
2:3165b07182ad | 5 | // should work for whole MX25RXX35F chip family |
| Maciej Bocianski |
2:3165b07182ad | 6 | |
| Senthil Ramakrishnan |
0:f741508e07a3 | 7 | // Command for reading status register |
| Senthil Ramakrishnan |
0:f741508e07a3 | 8 | #define QSPI_STD_CMD_RDSR 0x05 |
| Maciej Bocianski |
2:3165b07182ad | 9 | // Command for reading configuration register |
| Maciej Bocianski |
2:3165b07182ad | 10 | #define QSPI_STD_CMD_RDCR 0x15 |
| Maciej Bocianski |
2:3165b07182ad | 11 | // Command for writing status/configuration register |
| Senthil Ramakrishnan |
0:f741508e07a3 | 12 | #define QSPI_STD_CMD_WRSR 0x01 |
| Senthil Ramakrishnan |
0:f741508e07a3 | 13 | // Command for setting WREN (supported only by some memories) |
| Senthil Ramakrishnan |
0:f741508e07a3 | 14 | #define QSPI_STD_CMD_WREN 0x06 |
| Senthil Ramakrishnan |
0:f741508e07a3 | 15 | // Command for Sector erase (supported only by some memories) |
| Senthil Ramakrishnan |
0:f741508e07a3 | 16 | #define QSPI_STD_CMD_SECT_ERASE 0x20 |
| Maciej Bocianski |
2:3165b07182ad | 17 | // |
| Maciej Bocianski |
2:3165b07182ad | 18 | #define QSPI_STD_CMD_WRITE_1IO 0x02 // 1-1-1 mode |
| Maciej Bocianski |
2:3165b07182ad | 19 | #define QSPI_STD_CMD_WRITE_4IO 0x38 // 1-4-4 mode |
| Maciej Bocianski |
2:3165b07182ad | 20 | #define QSPI_STD_CMD_READ_1IO 0x03 // 1-1-1 mode |
| Maciej Bocianski |
2:3165b07182ad | 21 | #define QSPI_STD_CMD_READ_4IO 0xEB // 1-4-4 mode |
| Maciej Bocianski |
2:3165b07182ad | 22 | |
| Maciej Bocianski |
2:3165b07182ad | 23 | #define QSPI_STD_CMD_RSTEN 0x66 |
| Maciej Bocianski |
2:3165b07182ad | 24 | // Command for setting Reset (supported only by some memories) |
| Maciej Bocianski |
2:3165b07182ad | 25 | #define QSPI_STD_CMD_RST 0x99 |
| Maciej Bocianski |
2:3165b07182ad | 26 | |
| Maciej Bocianski |
2:3165b07182ad | 27 | #define STATUS_BIT_WIP (1 << 0) // write in progress bit |
| Maciej Bocianski |
2:3165b07182ad | 28 | #define STATUS_BIT_QE (1 << 6) // Quad Enable |
| Maciej Bocianski |
2:3165b07182ad | 29 | |
| Maciej Bocianski |
2:3165b07182ad | 30 | #define QSPI_STATUS_REG_SIZE 1 |
| Maciej Bocianski |
2:3165b07182ad | 31 | |
| Maciej Bocianski |
2:3165b07182ad | 32 | #define QSPI_READ_4IO_DUMMY_CYCLE 6 |
| Maciej Bocianski |
2:3165b07182ad | 33 | |
| Maciej Bocianski |
2:3165b07182ad | 34 | #define QSPI_MAX_WAIT_TIME 1000 // 1000 ms |
| Maciej Bocianski |
2:3165b07182ad | 35 | |
| Maciej Bocianski |
2:3165b07182ad | 36 | |
| Maciej Bocianski |
2:3165b07182ad | 37 | |
| Senthil Ramakrishnan |
0:f741508e07a3 | 38 | |
| Senthil Ramakrishnan |
0:f741508e07a3 | 39 | //#define DEBUG_ON 1 |
| Senthil Ramakrishnan |
0:f741508e07a3 | 40 | #ifdef DEBUG_ON |
| Maciej Bocianski |
2:3165b07182ad | 41 | #define VERBOSE_PRINT(x) printf x |
| Maciej Bocianski |
2:3165b07182ad | 42 | #else |
| Maciej Bocianski |
2:3165b07182ad | 43 | #define VERBOSE_PRINT(x) |
| Senthil Ramakrishnan |
0:f741508e07a3 | 44 | #endif |
| Senthil Ramakrishnan |
0:f741508e07a3 | 45 | |
| Maciej Bocianski |
2:3165b07182ad | 46 | |
| Maciej Bocianski |
2:3165b07182ad | 47 | bool InitializeFlashMem(QSPI &qspi); |
| Maciej Bocianski |
2:3165b07182ad | 48 | bool WaitForMemReady(QSPI &qspi); |
| Maciej Bocianski |
2:3165b07182ad | 49 | bool SectorErase(QSPI &qspi, unsigned int flash_addr); |
| Maciej Bocianski |
2:3165b07182ad | 50 | |
| Maciej Bocianski |
2:3165b07182ad | 51 | bool WriteReadQuad(QSPI &qspi, unsigned int flash_addr); |
| Maciej Bocianski |
2:3165b07182ad | 52 | |
| Maciej Bocianski |
2:3165b07182ad | 53 | bool QuadEnable(QSPI &qspi); |
| Maciej Bocianski |
2:3165b07182ad | 54 | bool QuadDisable(QSPI &qspi); |
| Maciej Bocianski |
2:3165b07182ad | 55 | |
| Maciej Bocianski |
2:3165b07182ad | 56 | |
| Maciej Bocianski |
2:3165b07182ad | 57 | #define TEST_FLASH_ADDRESS 0x1000 |
| Maciej Bocianski |
2:3165b07182ad | 58 | |
| Senthil Ramakrishnan |
0:f741508e07a3 | 59 | // main() runs in its own thread in the OS |
| Maciej Bocianski |
2:3165b07182ad | 60 | int main() |
| Maciej Bocianski |
2:3165b07182ad | 61 | { |
| Maciej Bocianski |
2:3165b07182ad | 62 | printf(">>> Start...\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 63 | QSPI myQspi((PinName)QSPI_FLASH1_IO0, (PinName)QSPI_FLASH1_IO1, (PinName)QSPI_FLASH1_IO2, (PinName)QSPI_FLASH1_IO3, (PinName)QSPI_FLASH1_SCK, (PinName)QSPI_FLASH1_CSN); |
| Maciej Bocianski |
2:3165b07182ad | 64 | |
| Maciej Bocianski |
2:3165b07182ad | 65 | if (QSPI_STATUS_OK == myQspi.configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0)) { |
| Maciej Bocianski |
2:3165b07182ad | 66 | printf("[main] Configured QSPI driver succesfully: 1-1-1\r\n"); |
| Senthil Ramakrishnan |
0:f741508e07a3 | 67 | } else { |
| Maciej Bocianski |
2:3165b07182ad | 68 | printf("[main] ERROR: Failed configuring QSPI driver\r\n"); |
| Senthil Ramakrishnan |
0:f741508e07a3 | 69 | return -1; |
| Senthil Ramakrishnan |
0:f741508e07a3 | 70 | } |
| Maciej Bocianski |
2:3165b07182ad | 71 | |
| Maciej Bocianski |
2:3165b07182ad | 72 | if (false == InitializeFlashMem(myQspi)) { |
| Maciej Bocianski |
2:3165b07182ad | 73 | printf("[main] Unable to initialize flash memory, tests failed\r\n"); |
| Senthil Ramakrishnan |
0:f741508e07a3 | 74 | return -1; |
| Senthil Ramakrishnan |
0:f741508e07a3 | 75 | } |
| Maciej Bocianski |
2:3165b07182ad | 76 | |
| Maciej Bocianski |
2:3165b07182ad | 77 | if (false == WriteReadQuad(myQspi, TEST_FLASH_ADDRESS)) { |
| Maciej Bocianski |
2:3165b07182ad | 78 | printf("[main] Unable to read/write using QuadSPI\r\n"); |
| Senthil Ramakrishnan |
0:f741508e07a3 | 79 | return -1; |
| Senthil Ramakrishnan |
0:f741508e07a3 | 80 | } |
| Maciej Bocianski |
2:3165b07182ad | 81 | |
| Maciej Bocianski |
2:3165b07182ad | 82 | printf("<<< Done...\r\n"); |
| Senthil Ramakrishnan |
0:f741508e07a3 | 83 | } |
| Senthil Ramakrishnan |
0:f741508e07a3 | 84 | |
| Maciej Bocianski |
2:3165b07182ad | 85 | bool WriteReadQuad(QSPI &qspi, unsigned int flash_addr) |
| Senthil Ramakrishnan |
0:f741508e07a3 | 86 | { |
| Senthil Ramakrishnan |
0:f741508e07a3 | 87 | int result = 0; |
| Maciej Bocianski |
2:3165b07182ad | 88 | char tx_buf[] = { 'H', 'E', 'L', 'L', 'O', ' ', 'Q', 'U', 'A', 'D', '-', 'S', 'P', 'I', '!', 0 }; |
| Maciej Bocianski |
2:3165b07182ad | 89 | char rx_buf[16]; |
| Senthil Ramakrishnan |
0:f741508e07a3 | 90 | size_t buf_len = sizeof(tx_buf); |
| Maciej Bocianski |
2:3165b07182ad | 91 | |
| Maciej Bocianski |
2:3165b07182ad | 92 | if (false == SectorErase(qspi, flash_addr)) { |
| Maciej Bocianski |
2:3165b07182ad | 93 | printf("[WriteReadQuad] ERROR: SectorErase failed(addr = 0x%08lX)\r\n", flash_addr); |
| Maciej Bocianski |
2:3165b07182ad | 94 | return false; |
| Maciej Bocianski |
2:3165b07182ad | 95 | } |
| Maciej Bocianski |
2:3165b07182ad | 96 | |
| Maciej Bocianski |
2:3165b07182ad | 97 | if (false == QuadEnable(qspi)) { |
| Maciej Bocianski |
2:3165b07182ad | 98 | printf("[WriteReadQuad] ERROR: Quad enable failed\r\n"); |
| Senthil Ramakrishnan |
0:f741508e07a3 | 99 | return false; |
| Senthil Ramakrishnan |
0:f741508e07a3 | 100 | } |
| Maciej Bocianski |
2:3165b07182ad | 101 | |
| Maciej Bocianski |
2:3165b07182ad | 102 | // Send write enable |
| Maciej Bocianski |
2:3165b07182ad | 103 | if (QSPI_STATUS_OK == qspi.command_transfer(QSPI_STD_CMD_WREN, // command to send |
| Maciej Bocianski |
2:3165b07182ad | 104 | -1, // no address to transmit |
| Maciej Bocianski |
2:3165b07182ad | 105 | NULL, 0, // do not transmit |
| Maciej Bocianski |
2:3165b07182ad | 106 | NULL, 0)) { // do not receive |
| Maciej Bocianski |
2:3165b07182ad | 107 | VERBOSE_PRINT(("[WriteReadQuad] Sending WREN command success\r\n")); |
| Maciej Bocianski |
2:3165b07182ad | 108 | } else { |
| Maciej Bocianski |
2:3165b07182ad | 109 | printf("[WriteReadQuad] ERROR: Sending WREN command failed\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 110 | return false; |
| Maciej Bocianski |
2:3165b07182ad | 111 | } |
| Maciej Bocianski |
2:3165b07182ad | 112 | |
| Maciej Bocianski |
2:3165b07182ad | 113 | if (QSPI_STATUS_OK == qspi.configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_QUAD, QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_QUAD, 0)) { |
| Maciej Bocianski |
2:3165b07182ad | 114 | printf("[WriteReadQuad] Configured QSPI driver succesfully: 1-4-4\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 115 | } else { |
| Maciej Bocianski |
2:3165b07182ad | 116 | printf("[WriteReadQuad] ERROR: Failed configuring QSPI driver\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 117 | return -1; |
| Maciej Bocianski |
2:3165b07182ad | 118 | } |
| Maciej Bocianski |
2:3165b07182ad | 119 | |
| Maciej Bocianski |
2:3165b07182ad | 120 | printf("[WriteReadQuad] Writing: %s\r\n", tx_buf); |
| Maciej Bocianski |
2:3165b07182ad | 121 | result = qspi.write(QSPI_STD_CMD_WRITE_4IO, 0, flash_addr, tx_buf, &buf_len); |
| Maciej Bocianski |
2:3165b07182ad | 122 | if ((result != QSPI_STATUS_OK) || buf_len != sizeof(tx_buf)) { |
| Maciej Bocianski |
2:3165b07182ad | 123 | printf("[WriteReadQuad] ERROR: Write failed\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 124 | } |
| Maciej Bocianski |
2:3165b07182ad | 125 | |
| Maciej Bocianski |
2:3165b07182ad | 126 | if (false == WaitForMemReady(qspi)) { |
| Maciej Bocianski |
2:3165b07182ad | 127 | printf("[WriteReadQuad] ERROR: Device not ready, tests failed\r\n"); |
| Senthil Ramakrishnan |
0:f741508e07a3 | 128 | return false; |
| Senthil Ramakrishnan |
0:f741508e07a3 | 129 | } |
| Maciej Bocianski |
2:3165b07182ad | 130 | |
| Maciej Bocianski |
2:3165b07182ad | 131 | if (QSPI_STATUS_OK == qspi.configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_QUAD, QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_QUAD, QSPI_READ_4IO_DUMMY_CYCLE)) { |
| Maciej Bocianski |
2:3165b07182ad | 132 | printf("[WriteReadQuad] Configured QSPI driver succesfully: 1-4-4\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 133 | } else { |
| Maciej Bocianski |
2:3165b07182ad | 134 | printf("[WriteReadQuad] ERROR: Failed configuring QSPI driver\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 135 | return -1; |
| Senthil Ramakrishnan |
0:f741508e07a3 | 136 | } |
| Maciej Bocianski |
2:3165b07182ad | 137 | |
| Maciej Bocianski |
2:3165b07182ad | 138 | memset(rx_buf, 0, sizeof(rx_buf)); |
| Maciej Bocianski |
2:3165b07182ad | 139 | result = qspi.read(QSPI_STD_CMD_READ_4IO, 0, flash_addr, rx_buf, &buf_len); |
| Maciej Bocianski |
2:3165b07182ad | 140 | if (result != QSPI_STATUS_OK) { |
| Maciej Bocianski |
2:3165b07182ad | 141 | printf("[WriteReadQuad] ERROR: Read failed\r\n"); |
| Senthil Ramakrishnan |
0:f741508e07a3 | 142 | return false; |
| Senthil Ramakrishnan |
0:f741508e07a3 | 143 | } |
| Maciej Bocianski |
2:3165b07182ad | 144 | |
| Maciej Bocianski |
2:3165b07182ad | 145 | if (QSPI_STATUS_OK == qspi.configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0)) { |
| Maciej Bocianski |
2:3165b07182ad | 146 | printf("[WriteReadQuad] Configured QSPI driver succesfully: 1-1-1\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 147 | } else { |
| Maciej Bocianski |
2:3165b07182ad | 148 | printf("[WriteReadQuad] ERROR: Failed configuring QSPI driver\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 149 | return -1; |
| Maciej Bocianski |
2:3165b07182ad | 150 | } |
| Maciej Bocianski |
2:3165b07182ad | 151 | |
| Maciej Bocianski |
2:3165b07182ad | 152 | if (false == QuadDisable(qspi)) { |
| Maciej Bocianski |
2:3165b07182ad | 153 | printf("[WriteReadQuad] ERROR: Quad disable failed\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 154 | return false; |
| Maciej Bocianski |
2:3165b07182ad | 155 | } |
| Maciej Bocianski |
2:3165b07182ad | 156 | |
| Maciej Bocianski |
2:3165b07182ad | 157 | if (buf_len != sizeof(rx_buf)) { |
| Maciej Bocianski |
2:3165b07182ad | 158 | printf("[WriteReadQuad] ERROR: Unable to read the entire buffer\r\n"); |
| Senthil Ramakrishnan |
0:f741508e07a3 | 159 | return false; |
| Senthil Ramakrishnan |
0:f741508e07a3 | 160 | } |
| Maciej Bocianski |
2:3165b07182ad | 161 | |
| Maciej Bocianski |
2:3165b07182ad | 162 | if (0 != (memcmp(rx_buf, tx_buf, sizeof(rx_buf)))) { |
| Maciej Bocianski |
2:3165b07182ad | 163 | printf("[WriteReadQuad] ERROR: Buffer contents are invalid\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 164 | printf("tx_buf: "); |
| Maciej Bocianski |
2:3165b07182ad | 165 | for (uint32_t i = 0; i < buf_len; i++) { |
| Maciej Bocianski |
2:3165b07182ad | 166 | printf("%d ", tx_buf[i]); |
| Maciej Bocianski |
2:3165b07182ad | 167 | } |
| Maciej Bocianski |
2:3165b07182ad | 168 | printf("\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 169 | printf("rx_buf: "); |
| Maciej Bocianski |
2:3165b07182ad | 170 | for (uint32_t i = 0; i < buf_len; i++) { |
| Maciej Bocianski |
2:3165b07182ad | 171 | printf("%d ", rx_buf[i]); |
| Maciej Bocianski |
2:3165b07182ad | 172 | } |
| Maciej Bocianski |
2:3165b07182ad | 173 | printf("\r\n"); |
| Senthil Ramakrishnan |
0:f741508e07a3 | 174 | return false; |
| Senthil Ramakrishnan |
0:f741508e07a3 | 175 | } |
| Maciej Bocianski |
2:3165b07182ad | 176 | printf("[WriteReadQuad] Read: %s\r\n", rx_buf); |
| Maciej Bocianski |
2:3165b07182ad | 177 | |
| Senthil Ramakrishnan |
0:f741508e07a3 | 178 | return true; |
| Senthil Ramakrishnan |
0:f741508e07a3 | 179 | } |
| Senthil Ramakrishnan |
0:f741508e07a3 | 180 | |
| Maciej Bocianski |
2:3165b07182ad | 181 | bool InitializeFlashMem(QSPI &qspi) |
| Senthil Ramakrishnan |
0:f741508e07a3 | 182 | { |
| Maciej Bocianski |
2:3165b07182ad | 183 | char reg_data[QSPI_STATUS_REG_SIZE]; |
| Maciej Bocianski |
2:3165b07182ad | 184 | |
| Maciej Bocianski |
2:3165b07182ad | 185 | // Read the Status Register from device |
| Maciej Bocianski |
2:3165b07182ad | 186 | if (QSPI_STATUS_OK == qspi.command_transfer(QSPI_STD_CMD_RDSR, // command to send |
| Maciej Bocianski |
2:3165b07182ad | 187 | -1, // no address to transmit |
| Maciej Bocianski |
2:3165b07182ad | 188 | NULL, 0, // do not transmit |
| Maciej Bocianski |
2:3165b07182ad | 189 | reg_data, QSPI_STATUS_REG_SIZE)) { |
| Maciej Bocianski |
2:3165b07182ad | 190 | VERBOSE_PRINT(("[InitializeFlashMem] Reading Status Register Success: value = 0x%02X\r\n", status_value[0])); |
| Senthil Ramakrishnan |
0:f741508e07a3 | 191 | } else { |
| Maciej Bocianski |
2:3165b07182ad | 192 | printf("[InitializeFlashMem] ERROR: Reading Status Register failed\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 193 | return false; |
| Senthil Ramakrishnan |
0:f741508e07a3 | 194 | } |
| Maciej Bocianski |
2:3165b07182ad | 195 | |
| Maciej Bocianski |
2:3165b07182ad | 196 | // Send Reset Enable |
| Maciej Bocianski |
2:3165b07182ad | 197 | if (QSPI_STATUS_OK == qspi.command_transfer(QSPI_STD_CMD_RSTEN, // command to send |
| Maciej Bocianski |
2:3165b07182ad | 198 | -1, // no address to transmit |
| Maciej Bocianski |
2:3165b07182ad | 199 | NULL, 0, // do not transmit |
| Maciej Bocianski |
2:3165b07182ad | 200 | NULL, 0)) { // do not receive |
| Maciej Bocianski |
2:3165b07182ad | 201 | VERBOSE_PRINT(("[InitializeFlashMem] Sending RSTEN Success\r\n")); |
| Maciej Bocianski |
2:3165b07182ad | 202 | } else { |
| Maciej Bocianski |
2:3165b07182ad | 203 | printf("[InitializeFlashMem] ERROR: Sending RSTEN failed\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 204 | return false; |
| Senthil Ramakrishnan |
0:f741508e07a3 | 205 | } |
| Maciej Bocianski |
2:3165b07182ad | 206 | |
| Maciej Bocianski |
2:3165b07182ad | 207 | // Reset device |
| Maciej Bocianski |
2:3165b07182ad | 208 | if (QSPI_STATUS_OK == qspi.command_transfer(QSPI_STD_CMD_RST, // command to send |
| Maciej Bocianski |
2:3165b07182ad | 209 | -1, // no address to transmit |
| Maciej Bocianski |
2:3165b07182ad | 210 | NULL, 0, // do not transmit |
| Maciej Bocianski |
2:3165b07182ad | 211 | NULL, 0)) { // do not receive |
| Maciej Bocianski |
2:3165b07182ad | 212 | VERBOSE_PRINT(("[InitializeFlashMem] Sending RST Success\r\n")); |
| Maciej Bocianski |
2:3165b07182ad | 213 | } else { |
| Maciej Bocianski |
2:3165b07182ad | 214 | printf("[InitializeFlashMem] ERROR: Sending RST failed\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 215 | return false; |
| Maciej Bocianski |
2:3165b07182ad | 216 | } |
| Maciej Bocianski |
2:3165b07182ad | 217 | |
| Maciej Bocianski |
2:3165b07182ad | 218 | return true; |
| Senthil Ramakrishnan |
0:f741508e07a3 | 219 | } |
| Senthil Ramakrishnan |
0:f741508e07a3 | 220 | |
| Maciej Bocianski |
2:3165b07182ad | 221 | bool WaitForMemReady(QSPI &qspi) |
| Senthil Ramakrishnan |
0:f741508e07a3 | 222 | { |
| Maciej Bocianski |
2:3165b07182ad | 223 | char status_value[QSPI_STATUS_REG_SIZE]; |
| Maciej Bocianski |
2:3165b07182ad | 224 | Timer timer; |
| Maciej Bocianski |
2:3165b07182ad | 225 | |
| Maciej Bocianski |
2:3165b07182ad | 226 | timer.start(); |
| Maciej Bocianski |
2:3165b07182ad | 227 | do { |
| Maciej Bocianski |
2:3165b07182ad | 228 | // Read the Status Register from device |
| Maciej Bocianski |
2:3165b07182ad | 229 | if (QSPI_STATUS_OK == qspi.command_transfer(QSPI_STD_CMD_RDSR, // command to send |
| Maciej Bocianski |
2:3165b07182ad | 230 | -1, // no address to transmit |
| Maciej Bocianski |
2:3165b07182ad | 231 | NULL, 0, // do not transmit |
| Maciej Bocianski |
2:3165b07182ad | 232 | status_value, QSPI_STATUS_REG_SIZE)) { |
| Maciej Bocianski |
2:3165b07182ad | 233 | VERBOSE_PRINT(("[WaitForMemReady] Readng Status Register Success: value = 0x%02X\r\n", status_value[0])); |
| Senthil Ramakrishnan |
0:f741508e07a3 | 234 | } else { |
| Maciej Bocianski |
2:3165b07182ad | 235 | printf("[WaitForMemReady] ERROR: Reading Status Register failed\r\n"); |
| Senthil Ramakrishnan |
0:f741508e07a3 | 236 | } |
| Maciej Bocianski |
2:3165b07182ad | 237 | } while ((status_value[0] & STATUS_BIT_WIP) != 0 && timer.read_ms() < QSPI_MAX_WAIT_TIME); |
| Maciej Bocianski |
2:3165b07182ad | 238 | |
| Maciej Bocianski |
2:3165b07182ad | 239 | if ((status_value[0] & STATUS_BIT_WIP) != 0) { |
| Maciej Bocianski |
2:3165b07182ad | 240 | return false; |
| Maciej Bocianski |
2:3165b07182ad | 241 | } |
| Senthil Ramakrishnan |
0:f741508e07a3 | 242 | return true; |
| Senthil Ramakrishnan |
0:f741508e07a3 | 243 | } |
| Senthil Ramakrishnan |
0:f741508e07a3 | 244 | |
| Maciej Bocianski |
2:3165b07182ad | 245 | bool SectorErase(QSPI &qspi, unsigned int flash_addr) |
| Senthil Ramakrishnan |
0:f741508e07a3 | 246 | { |
| Maciej Bocianski |
2:3165b07182ad | 247 | // Set wite enable |
| Maciej Bocianski |
2:3165b07182ad | 248 | if (QSPI_STATUS_OK == qspi.command_transfer(QSPI_STD_CMD_WREN, // command to send |
| Maciej Bocianski |
2:3165b07182ad | 249 | -1, // no address to transmit |
| Maciej Bocianski |
2:3165b07182ad | 250 | NULL, 0, // do not transmit |
| Maciej Bocianski |
2:3165b07182ad | 251 | NULL, 0)) { // do not receive |
| Maciej Bocianski |
2:3165b07182ad | 252 | VERBOSE_PRINT(("[SectorErase] Sending WREN command success\r\n")); |
| Senthil Ramakrishnan |
0:f741508e07a3 | 253 | } else { |
| Maciej Bocianski |
2:3165b07182ad | 254 | printf("[SectorErase] ERROR: Sending WREN command failed\r\n"); |
| Senthil Ramakrishnan |
0:f741508e07a3 | 255 | return false; |
| Senthil Ramakrishnan |
0:f741508e07a3 | 256 | } |
| Maciej Bocianski |
2:3165b07182ad | 257 | // sector erase |
| Maciej Bocianski |
2:3165b07182ad | 258 | if (QSPI_STATUS_OK == qspi.command_transfer(QSPI_STD_CMD_SECT_ERASE, // command to send |
| Maciej Bocianski |
2:3165b07182ad | 259 | flash_addr, // sector address (any address within sector) |
| Maciej Bocianski |
2:3165b07182ad | 260 | NULL, 0, // do not transmit |
| Maciej Bocianski |
2:3165b07182ad | 261 | NULL, 0)) { // do not receive |
| Maciej Bocianski |
2:3165b07182ad | 262 | VERBOSE_PRINT(("[SectorErase] Sending SECT_ERASE command success\r\n")); |
| Senthil Ramakrishnan |
0:f741508e07a3 | 263 | } else { |
| Maciej Bocianski |
2:3165b07182ad | 264 | printf("[SectorErase] ERROR: Readng SECT_ERASE command failed\r\n"); |
| Senthil Ramakrishnan |
0:f741508e07a3 | 265 | return false; |
| Senthil Ramakrishnan |
0:f741508e07a3 | 266 | } |
| Maciej Bocianski |
2:3165b07182ad | 267 | |
| Maciej Bocianski |
2:3165b07182ad | 268 | if (false == WaitForMemReady(qspi)) { |
| Maciej Bocianski |
2:3165b07182ad | 269 | printf("[SectorErase] ERROR: Device not ready, tests failed\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 270 | return false; |
| Maciej Bocianski |
2:3165b07182ad | 271 | } |
| Maciej Bocianski |
2:3165b07182ad | 272 | |
| Senthil Ramakrishnan |
0:f741508e07a3 | 273 | return true; |
| Senthil Ramakrishnan |
0:f741508e07a3 | 274 | } |
| Senthil Ramakrishnan |
0:f741508e07a3 | 275 | |
| Maciej Bocianski |
2:3165b07182ad | 276 | bool QuadEnable(QSPI &qspi) |
| Maciej Bocianski |
2:3165b07182ad | 277 | { |
| Maciej Bocianski |
2:3165b07182ad | 278 | char reg_data[QSPI_STATUS_REG_SIZE]; |
| Maciej Bocianski |
2:3165b07182ad | 279 | |
| Maciej Bocianski |
2:3165b07182ad | 280 | //Read the Status Register from device |
| Maciej Bocianski |
2:3165b07182ad | 281 | if (QSPI_STATUS_OK == qspi.command_transfer(QSPI_STD_CMD_RDSR, // command to send |
| Maciej Bocianski |
2:3165b07182ad | 282 | -1, // no address to transmit |
| Maciej Bocianski |
2:3165b07182ad | 283 | NULL, 0, // do not transmit |
| Maciej Bocianski |
2:3165b07182ad | 284 | reg_data, QSPI_STATUS_REG_SIZE)) { |
| Maciej Bocianski |
2:3165b07182ad | 285 | VERBOSE_PRINT(("[QuadEnable] Reading Status Register Success: value = 0x%02X\r\n", reg_data[0])); |
| Maciej Bocianski |
2:3165b07182ad | 286 | } else { |
| Maciej Bocianski |
2:3165b07182ad | 287 | printf("ERROR: Reading Status Register failed\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 288 | return false; |
| Maciej Bocianski |
2:3165b07182ad | 289 | } |
| Maciej Bocianski |
2:3165b07182ad | 290 | |
| Maciej Bocianski |
2:3165b07182ad | 291 | if (QSPI_STATUS_OK == qspi.command_transfer(QSPI_STD_CMD_WREN, // command to send |
| Maciej Bocianski |
2:3165b07182ad | 292 | -1, // no address to transmit |
| Maciej Bocianski |
2:3165b07182ad | 293 | NULL, 0, // do not transmit |
| Maciej Bocianski |
2:3165b07182ad | 294 | NULL, 0)) { // do not receive |
| Maciej Bocianski |
2:3165b07182ad | 295 | VERBOSE_PRINT(("[QuadEnable] Sending WREN command success\r\n")); |
| Maciej Bocianski |
2:3165b07182ad | 296 | } else { |
| Maciej Bocianski |
2:3165b07182ad | 297 | printf("[QuadEnable] ERROR: Sending WREN command failed\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 298 | return false; |
| Maciej Bocianski |
2:3165b07182ad | 299 | } |
| Maciej Bocianski |
2:3165b07182ad | 300 | |
| Maciej Bocianski |
2:3165b07182ad | 301 | reg_data[0] |= (STATUS_BIT_QE); |
| Maciej Bocianski |
2:3165b07182ad | 302 | //Set the Status Register to set QE enable bit |
| Maciej Bocianski |
2:3165b07182ad | 303 | if (QSPI_STATUS_OK == qspi.command_transfer(QSPI_STD_CMD_WRSR, // command to send |
| Maciej Bocianski |
2:3165b07182ad | 304 | -1, // no address to transmit |
| Maciej Bocianski |
2:3165b07182ad | 305 | reg_data, QSPI_STATUS_REG_SIZE, |
| Maciej Bocianski |
2:3165b07182ad | 306 | NULL, 0)) { // do not receive |
| Maciej Bocianski |
2:3165b07182ad | 307 | VERBOSE_PRINT(("[QuadEnable] Writing Status Register Success\r\n")); |
| Maciej Bocianski |
2:3165b07182ad | 308 | } else { |
| Maciej Bocianski |
2:3165b07182ad | 309 | printf("[QuadEnable] ERROR: Writing Status Register failed\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 310 | return false; |
| Maciej Bocianski |
2:3165b07182ad | 311 | } |
| Maciej Bocianski |
2:3165b07182ad | 312 | |
| Maciej Bocianski |
2:3165b07182ad | 313 | if (false == WaitForMemReady(qspi)) { |
| Maciej Bocianski |
2:3165b07182ad | 314 | printf("[QuadEnable] ERROR: Device not ready, tests failed\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 315 | return false; |
| Maciej Bocianski |
2:3165b07182ad | 316 | } |
| Maciej Bocianski |
2:3165b07182ad | 317 | |
| Maciej Bocianski |
2:3165b07182ad | 318 | return true; |
| Maciej Bocianski |
2:3165b07182ad | 319 | } |
| Maciej Bocianski |
2:3165b07182ad | 320 | |
| Maciej Bocianski |
2:3165b07182ad | 321 | bool QuadDisable(QSPI &qspi) |
| Maciej Bocianski |
2:3165b07182ad | 322 | { |
| Maciej Bocianski |
2:3165b07182ad | 323 | char reg_data[QSPI_STATUS_REG_SIZE]; |
| Maciej Bocianski |
2:3165b07182ad | 324 | |
| Maciej Bocianski |
2:3165b07182ad | 325 | // Read the Status Register from device |
| Maciej Bocianski |
2:3165b07182ad | 326 | if (QSPI_STATUS_OK == qspi.command_transfer(QSPI_STD_CMD_RDSR, // command to send |
| Maciej Bocianski |
2:3165b07182ad | 327 | -1, // no address to transmit |
| Maciej Bocianski |
2:3165b07182ad | 328 | NULL, 0, // do not transmit |
| Maciej Bocianski |
2:3165b07182ad | 329 | reg_data, QSPI_STATUS_REG_SIZE)) { |
| Maciej Bocianski |
2:3165b07182ad | 330 | VERBOSE_PRINT(("[QuadDisable] Reading Status Register Success: value = 0x%02X\r\n", reg_data[0])); |
| Maciej Bocianski |
2:3165b07182ad | 331 | } else { |
| Maciej Bocianski |
2:3165b07182ad | 332 | printf("[QuadDisable] ERROR: Reading Status Register failed\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 333 | return false; |
| Maciej Bocianski |
2:3165b07182ad | 334 | } |
| Maciej Bocianski |
2:3165b07182ad | 335 | |
| Maciej Bocianski |
2:3165b07182ad | 336 | // Set write enable |
| Maciej Bocianski |
2:3165b07182ad | 337 | if (QSPI_STATUS_OK == qspi.command_transfer(QSPI_STD_CMD_WREN, // command to send |
| Maciej Bocianski |
2:3165b07182ad | 338 | -1, // no address to transmit |
| Maciej Bocianski |
2:3165b07182ad | 339 | NULL, 0, // do not transmit |
| Maciej Bocianski |
2:3165b07182ad | 340 | NULL, 0)) { // do not receive |
| Maciej Bocianski |
2:3165b07182ad | 341 | VERBOSE_PRINT(("[QuadDisable] Sending WREN command success\r\n")); |
| Maciej Bocianski |
2:3165b07182ad | 342 | } else { |
| Maciej Bocianski |
2:3165b07182ad | 343 | printf("[QuadDisable] ERROR: Sending WREN command failed\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 344 | return false; |
| Maciej Bocianski |
2:3165b07182ad | 345 | } |
| Maciej Bocianski |
2:3165b07182ad | 346 | |
| Maciej Bocianski |
2:3165b07182ad | 347 | reg_data[0] &= ~(STATUS_BIT_QE); |
| Maciej Bocianski |
2:3165b07182ad | 348 | //Set the Status Register to reset QE enable bit |
| Maciej Bocianski |
2:3165b07182ad | 349 | if (QSPI_STATUS_OK == qspi.command_transfer(QSPI_STD_CMD_WRSR, // command to send |
| Maciej Bocianski |
2:3165b07182ad | 350 | -1, // no address to transmit |
| Maciej Bocianski |
2:3165b07182ad | 351 | reg_data, QSPI_STATUS_REG_SIZE, |
| Maciej Bocianski |
2:3165b07182ad | 352 | NULL, 0)) { // do not receive |
| Maciej Bocianski |
2:3165b07182ad | 353 | VERBOSE_PRINT(("[QuadDisable] Writing Status Register Success\r\n")); |
| Maciej Bocianski |
2:3165b07182ad | 354 | } else { |
| Maciej Bocianski |
2:3165b07182ad | 355 | printf("[QuadDisable] ERROR: Writing Status Register failed\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 356 | return false; |
| Maciej Bocianski |
2:3165b07182ad | 357 | } |
| Maciej Bocianski |
2:3165b07182ad | 358 | |
| Maciej Bocianski |
2:3165b07182ad | 359 | if (false == WaitForMemReady(qspi)) { |
| Maciej Bocianski |
2:3165b07182ad | 360 | printf("[QuadDisable] ERROR: Device not ready, tests failed\r\n"); |
| Maciej Bocianski |
2:3165b07182ad | 361 | return false; |
| Maciej Bocianski |
2:3165b07182ad | 362 | } |
| Maciej Bocianski |
2:3165b07182ad | 363 | |
| Maciej Bocianski |
2:3165b07182ad | 364 | return true; |
| Maciej Bocianski |
2:3165b07182ad | 365 | } |
