Diff: FMS_all.h

Revision:

355:a5e72222ff26

Parent:

354:eb6c863756a8

Child:

356:197c93dc2012

--- a/FMS_all.h	Sat Mar 11 05:52:18 2017 +0000
+++ b/FMS_all.h	Tue Mar 28 08:50:07 2017 +0000
@@ -94,7 +94,8 @@
     SD_CARD_fromuC_ENA3 = 0; 
     SD_CARD_fromISO_ENA4 = 0;
     SD_SW_EN_DS = 0;
-    SD_STATUS = DEVICE_DISABLED;
+   // SD_STATUS = DEVICE_DISABLED;
+   SD_STATUS = 0;
    FCTN_CDMS_WR_FLASH(2,DEVICE_DISABLED);
     gPC.printf("sw off sd\n");
 }
@@ -113,8 +114,8 @@
     spi.write(0x00);//enabling halt bit in the seconds register
     gCS_RTC=1;
      EN_RTC = 0x01;
-//    CDMS_RTC_DISABLE =1;
-    FCTN_CDMS_WR_FLASH(1,DEVICE_POWERED);
+    CDMS_RTC_DISABLE =1;
+    FCTN_CDMS_WR_FLASH(6,DEVICE_POWERED);
   //  gPC.printf("0x%08X \n", READ_FROM_EERPOM(6));
     SPI_mutex.unlock();
     gPC.printf("sw on rtc\n");
@@ -134,7 +135,7 @@
     gCS_RTC=1;
    
    EN_RTC  = 0x00;
-//    CDMS_RTC_DISABLE = 0;
+   CDMS_RTC_DISABLE = 0;
     FCTN_CDMS_WR_FLASH(6,0x00);
     SPI_mutex.unlock();
     gPC.printf("sw off rtc\n");
@@ -151,7 +152,8 @@
 void SW_OFF_BAE()
 {
     BAE_SW_EN_DS = 0;
-    BAE_STATUS = DEVICE_DISABLED;
+ //   BAE_STATUS = DEVICE_DISABLED;
+     BAE_STATUS = 0;
      FCTN_CDMS_WR_FLASH(1,DEVICE_DISABLED);
     gPC.printf("sw off bae\n");
 }
@@ -178,7 +180,8 @@
     wait_us(1);
     PYLD_DFF_CLK = 0;
     wait_us(1);
-    PL_STATUS = DEVICE_DISABLED;
+ //   PL_STATUS = DEVICE_DISABLED;
+    PL_STATUS = 0;
    FCTN_CDMS_WR_FLASH(3,DEVICE_DISABLED);
 }
 
@@ -192,6 +195,7 @@
     PYLD_EPS_DFF_PWR_CLK = 0;
     wait_us(1);
     PL_EPS_LATCH_SW_EN = 1;
+    
     FCTN_CDMS_WR_FLASH(4,1);
 }
 
@@ -205,6 +209,7 @@
     PYLD_EPS_DFF_PWR_CLK = 0;
     wait_us(1);
     PL_EPS_LATCH_SW_EN = 0;
+    
     FCTN_CDMS_WR_FLASH(4,0);
 }