Team Fox / Mbed 2 deprecated CDMS_QM_03MAR2017_Flash_with_obsrs

working version

Dependencies:   mbed mbed-rtos SimpleDMA FreescaleIAP eeprom

Fork of CDMS_CODE_FM_28JAN2017 by samp Srinivasan

i2c.h@357:f3d48d62e00e, 2022-04-03 (annotated)

Committer:
samp1234
Date:
Sun Apr 03 15:35:53 2022 +0000
Revision:
357:f3d48d62e00e
Parent:
356:197c93dc2012 
First commit test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aniruddhv 52:0bd68655c651 1 #define tm_len 134
aniruddhv 52:0bd68655c651 2 #define tc_len 135
aniruddhv 52:0bd68655c651 3 #define tc_test_len 135
aniruddhv 52:0bd68655c651 4
aniruddhv 52:0bd68655c651 5 const int addr = 0x20; //slave address
ee12b079 161:a63672bf4423 6 bool write_ack = false;
ee12b079 161:a63672bf4423 7 bool read_ack = false;
ee12b079 161:a63672bf4423 8 const int addr_pl = 0x20<<1; //PL address
ee12b079 162:48fda0b8d573 9 const int addr_bae = 0x20; ///bae address
ee12b079 209:63e9c8f8b5d2 10 //uint8_t rcv_isr = 0;
aniruddhv 52:0bd68655c651 11
aniruddhv 52:0bd68655c651 12 int count = 0;
aniruddhv 52:0bd68655c651 13
ee12b079 161:a63672bf4423 14 char PL_I2C_DATA[134];//Payload i2c array
ee12b079 161:a63672bf4423 15 uint8_t PL_TM_SIZE;//size of data to bev read from i2c
ee12b079 209:63e9c8f8b5d2 16 uint32_t pdirr1;
ee12b079 209:63e9c8f8b5d2 17 uint32_t pdirw1;
aniruddhv 52:0bd68655c651 18
ee12b079 209:63e9c8f8b5d2 19 void I2C_busreset()
ee12b079 209:63e9c8f8b5d2 20 {
samp1234 357:f3d48d62e00e 21 PORTE->PCR[24] &= 0xfffffffb; //Enabling high slew rates for SDA and SCL lines
samp1234 357:f3d48d62e00e 22 PORTE->PCR[25] &= 0xfffffffb; //Enabling high slew rates for SDA and SCL lines
ee12b079 209:63e9c8f8b5d2 23 I2C0->C1 &= 0x7f; //Disabling I2C module
ee12b079 209:63e9c8f8b5d2 24 SIM->SCGC4 &= 0xffffffbf; //Disabling clock to I2C module
ee12b079 209:63e9c8f8b5d2 25 SIM->SCGC4 |= 0x00000040; //Enabling clock to I2C module
ee12b079 209:63e9c8f8b5d2 26 I2C0->C1 |= 0x80; //Enabling I2C module
samp1234 357:f3d48d62e00e 27 PORTE->PCR[24] |= 0x00000004; //Disabling high slew rates for SDA and SCL lines
samp1234 357:f3d48d62e00e 28 PORTE->PCR[25] |= 0x00000004; //Disabling high slew rates for SDA and SCL lines
ee12b079 209:63e9c8f8b5d2 29 Thread::wait(1); //Wait for all I2C registers to be updates to their their values
ee12b079 209:63e9c8f8b5d2 30 }
ee12b079 209:63e9c8f8b5d2 31 bool FCTN_I2C_READ_PL(char *data,int length) // Returns 0 for success
ee12b079 209:63e9c8f8b5d2 32 {
samp1234 357:f3d48d62e00e 33 master.frequency(400000);
ee12b079 209:63e9c8f8b5d2 34 PL_I2C_GPIO = 1;
ee12b079 184:d75cea6f5d49 35 read_ack = master.read(addr_pl|1,data,length);
ee12b079 209:63e9c8f8b5d2 36 Thread::wait(1); //as per tests Thread::wait not required on master side. But its safe to give 1ms
ee12b079 209:63e9c8f8b5d2 37 pdirr1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 38 uint8_t i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 39 if(read_ack == 0) //if read_ack says success, it may or may not be successful.Hence we check SCL and SDA
ee12b079 209:63e9c8f8b5d2 40 {
ee12b079 209:63e9c8f8b5d2 41 while(((pdirr1 & 0x03000000)!=0x03000000)&& i2c_count<10)//checking SCL and SDA for time=10ms
ee12b079 209:63e9c8f8b5d2 42 {
ee12b079 209:63e9c8f8b5d2 43 Thread::wait(1);
ee12b079 209:63e9c8f8b5d2 44 pdirr1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 45 i2c_count++;
ee12b079 209:63e9c8f8b5d2 46 }
ee12b079 209:63e9c8f8b5d2 47 if(((pdirr1 & 0x03000000)==0x03000000))//if SCL and SDA are both high
ee12b079 209:63e9c8f8b5d2 48 {
chaithanyarss 290:3159ff1081a2 49 gPC.printf("\n\rData received from PL");
ee12b079 209:63e9c8f8b5d2 50 }
ee12b079 209:63e9c8f8b5d2 51 else
ee12b079 209:63e9c8f8b5d2 52 {
ee12b079 209:63e9c8f8b5d2 53 I2C_busreset();
ee12b079 209:63e9c8f8b5d2 54 read_ack = 1;
ee12b079 209:63e9c8f8b5d2 55 }
ee12b079 209:63e9c8f8b5d2 56 }
ee12b079 209:63e9c8f8b5d2 57 else if (read_ack == 1)
ee12b079 184:d75cea6f5d49 58 {
chaithanyarss 303:b49b486a7107 59 CDMS_I2C_ERR_SPEED_COUNTER++;
ee12b079 209:63e9c8f8b5d2 60 I2C_busreset();
ee12b079 184:d75cea6f5d49 61 }
samp1234 346:204497974293 62
ee12b079 209:63e9c8f8b5d2 63 PL_I2C_GPIO = 0;
ee12b079 209:63e9c8f8b5d2 64 i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 65 return read_ack;
ee12b079 209:63e9c8f8b5d2 66
samp1234 346:204497974293 67
ee12b079 184:d75cea6f5d49 68 }
ee12b079 209:63e9c8f8b5d2 69 bool FCTN_I2C_WRITE_PL(char *data2,uint8_t tc_len2) // Returns 0 for success
ee12b079 209:63e9c8f8b5d2 70 {
samp1234 357:f3d48d62e00e 71 master.frequency(400000);
samp1234 357:f3d48d62e00e 72 write_ack = master.write(addr_pl|0x00,data2,tc_len2);//address to be defined in payload
ee12b079 209:63e9c8f8b5d2 73 Thread::wait(1); //As per the tests Thread::wait is not required on master side but its safe to give 1ms
ee12b079 209:63e9c8f8b5d2 74 pdirw1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 75 uint8_t i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 76 if(write_ack == 0)
ee12b079 209:63e9c8f8b5d2 77 {
ee12b079 209:63e9c8f8b5d2 78 while(((pdirw1 & 0x03000000)!=0x03000000)&& i2c_count<10)
ee12b079 209:63e9c8f8b5d2 79 {
ee12b079 209:63e9c8f8b5d2 80 Thread::wait(1);
ee12b079 209:63e9c8f8b5d2 81 pdirw1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 82 i2c_count++;
ee12b079 209:63e9c8f8b5d2 83 }
ee12b079 209:63e9c8f8b5d2 84 if(((pdirw1 & 0x03000000)==0x03000000))
ee12b079 209:63e9c8f8b5d2 85 {
ee12b079 209:63e9c8f8b5d2 86 gPC.printf("\n\r Data sent");
ee12b079 209:63e9c8f8b5d2 87 }
ee12b079 209:63e9c8f8b5d2 88 else
ee12b079 209:63e9c8f8b5d2 89 {
ee12b079 209:63e9c8f8b5d2 90 I2C_busreset();
ee12b079 209:63e9c8f8b5d2 91 write_ack = 1;
ee12b079 209:63e9c8f8b5d2 92 }
ee12b079 209:63e9c8f8b5d2 93 }
ee12b079 209:63e9c8f8b5d2 94 if (write_ack == 1)
ee12b079 209:63e9c8f8b5d2 95 {
ee12b079 209:63e9c8f8b5d2 96 I2C_busreset();
chaithanyarss 303:b49b486a7107 97 CDMS_I2C_ERR_SPEED_COUNTER++;
ee12b079 209:63e9c8f8b5d2 98 }
ee12b079 209:63e9c8f8b5d2 99 i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 100 return write_ack;
ee12b079 209:63e9c8f8b5d2 101 }
ee12b079 209:63e9c8f8b5d2 102 bool FCTN_I2C_READ(char *data,int length) // Returns 0 for success
ee12b079 162:48fda0b8d573 103 {
samp1234 346:204497974293 104 // gPC.printf("i2C_rd\r\n");
samp1234 357:f3d48d62e00e 105 master.frequency(400000);
ee12b079 162:48fda0b8d573 106 CDMS_I2C_GPIO = 1;
samp1234 357:f3d48d62e00e 107 read_ack = master.read(addr_bae|1,data,length);
ee12b079 209:63e9c8f8b5d2 108 Thread::wait(1); //as per tests Thread::wait not required on master side. But its safe to give 1ms
ee12b079 209:63e9c8f8b5d2 109 pdirr1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 110 uint8_t i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 111 if(read_ack == 0) //if read_ack says success, it may or may not be successful.Hence we check SCL and SDA
ee12b079 162:48fda0b8d573 112 {
ee12b079 209:63e9c8f8b5d2 113 while(((pdirr1 & 0x03000000)!=0x03000000)&& i2c_count<10)//checking SCL and SDA for time=10ms
ee12b079 209:63e9c8f8b5d2 114 {
ee12b079 209:63e9c8f8b5d2 115 Thread::wait(1);
ee12b079 209:63e9c8f8b5d2 116 pdirr1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 117 i2c_count++;
ee12b079 209:63e9c8f8b5d2 118 }
ee12b079 209:63e9c8f8b5d2 119 if(((pdirr1 & 0x03000000)==0x03000000))//if SCL and SDA are both high
ee12b079 209:63e9c8f8b5d2 120 {
chaithanyarss 328:2242ebc71be8 121 //gPC.printf("\n\rData received from BAE");
ee12b079 209:63e9c8f8b5d2 122 }
ee12b079 209:63e9c8f8b5d2 123 else
ee12b079 209:63e9c8f8b5d2 124 {
ee12b079 209:63e9c8f8b5d2 125 I2C_busreset();
ee12b079 209:63e9c8f8b5d2 126 read_ack = 1;
ee12b079 209:63e9c8f8b5d2 127 }
ee12b079 162:48fda0b8d573 128 }
samp1234 357:f3d48d62e00e 129 if (read_ack == 1)
ee12b079 209:63e9c8f8b5d2 130 {
ee12b079 209:63e9c8f8b5d2 131 I2C_busreset();
samp1234 357:f3d48d62e00e 132 CDMS_I2C_ERR_BAE_COUNTER++;
ee12b079 209:63e9c8f8b5d2 133 }
samp1234 346:204497974293 134 // gPC.printf("end_12c_RD_\r\n");
ee12b079 162:48fda0b8d573 135 CDMS_I2C_GPIO = 0;
ee12b079 209:63e9c8f8b5d2 136 i2c_count = 0;
ee12b079 198:17200a427e71 137 return read_ack;
ee12b079 162:48fda0b8d573 138 }
ee12b079 162:48fda0b8d573 139
ee12b079 209:63e9c8f8b5d2 140 bool FCTN_I2C_WRITE(char *data,int tc_len2) // Returns 0 for success
ee12b079 209:63e9c8f8b5d2 141 {
samp1234 346:204497974293 142 // gPC.printf("i2C_wr\r\n");
samp1234 357:f3d48d62e00e 143 master.frequency(400000);
ee12b079 162:48fda0b8d573 144 CDMS_I2C_GPIO = 1;
samp1234 357:f3d48d62e00e 145 write_ack = master.write(addr_bae|0x00,data,tc_len2);
samp1234 352:022c513aee03 146 Thread::wait(1); //As per the tests Thread::wait is not required on master side but its safe to give 1ms
ee12b079 209:63e9c8f8b5d2 147 pdirw1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 148 uint8_t i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 149 if(write_ack == 0)
ee12b079 162:48fda0b8d573 150 {
ee12b079 209:63e9c8f8b5d2 151 while(((pdirw1 & 0x03000000)!=0x03000000)&& i2c_count<10)
ee12b079 209:63e9c8f8b5d2 152 {
ee12b079 209:63e9c8f8b5d2 153 Thread::wait(1);
ee12b079 209:63e9c8f8b5d2 154 pdirw1=PTE->PDIR;
ee12b079 209:63e9c8f8b5d2 155 i2c_count++;
ee12b079 209:63e9c8f8b5d2 156 }
ee12b079 209:63e9c8f8b5d2 157 if(((pdirw1 & 0x03000000)==0x03000000))
ee12b079 209:63e9c8f8b5d2 158 {
chaithanyarss 328:2242ebc71be8 159 //gPC.printf("\n\r Data sent");
ee12b079 209:63e9c8f8b5d2 160 }
ee12b079 209:63e9c8f8b5d2 161 else
ee12b079 209:63e9c8f8b5d2 162 {
ee12b079 209:63e9c8f8b5d2 163 I2C_busreset();
ee12b079 209:63e9c8f8b5d2 164 write_ack = 1;
ee12b079 209:63e9c8f8b5d2 165 }
ee12b079 209:63e9c8f8b5d2 166 }
ee12b079 209:63e9c8f8b5d2 167 if (write_ack == 1)
ee12b079 209:63e9c8f8b5d2 168 {
ee12b079 209:63e9c8f8b5d2 169 I2C_busreset();
chaithanyarss 303:b49b486a7107 170 CDMS_I2C_ERR_BAE_COUNTER++;
ee12b079 162:48fda0b8d573 171 }
samp1234 346:204497974293 172 // gPC.printf("i2C_wr_end\r\n");
ee12b079 162:48fda0b8d573 173 CDMS_I2C_GPIO = 0;
ee12b079 209:63e9c8f8b5d2 174 i2c_count = 0;
ee12b079 209:63e9c8f8b5d2 175 return write_ack;
aniruddhv 52:0bd68655c651 176 }