ichinoseki_Bteam_2019
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nucleo_rotary_encoder
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stm32_hal_legacy.h@11:debd1264bae8, 2019-08-27 (annotated)
- Committer:
- TanakaTarou
- Date:
- Tue Aug 27 07:04:12 2019 +0000
- Revision:
- 11:debd1264bae8
qeiLibrary
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| TanakaTarou | 11:debd1264bae8 | 1 | #ifndef __STM32_HAL_LEGACY |
| TanakaTarou | 11:debd1264bae8 | 2 | #define __STM32_HAL_LEGACY |
| TanakaTarou | 11:debd1264bae8 | 3 | |
| TanakaTarou | 11:debd1264bae8 | 4 | #ifdef __cplusplus |
| TanakaTarou | 11:debd1264bae8 | 5 | extern "C" { |
| TanakaTarou | 11:debd1264bae8 | 6 | #endif |
| TanakaTarou | 11:debd1264bae8 | 7 | |
| TanakaTarou | 11:debd1264bae8 | 8 | #define AES_FLAG_RDERR CRYP_FLAG_RDERR |
| TanakaTarou | 11:debd1264bae8 | 9 | #define AES_FLAG_WRERR CRYP_FLAG_WRERR |
| TanakaTarou | 11:debd1264bae8 | 10 | #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF |
| TanakaTarou | 11:debd1264bae8 | 11 | #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR |
| TanakaTarou | 11:debd1264bae8 | 12 | #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR |
| TanakaTarou | 11:debd1264bae8 | 13 | |
| TanakaTarou | 11:debd1264bae8 | 14 | #define ADC_RESOLUTION12b ADC_RESOLUTION_12B |
| TanakaTarou | 11:debd1264bae8 | 15 | #define ADC_RESOLUTION10b ADC_RESOLUTION_10B |
| TanakaTarou | 11:debd1264bae8 | 16 | #define ADC_RESOLUTION8b ADC_RESOLUTION_8B |
| TanakaTarou | 11:debd1264bae8 | 17 | #define ADC_RESOLUTION6b ADC_RESOLUTION_6B |
| TanakaTarou | 11:debd1264bae8 | 18 | #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN |
| TanakaTarou | 11:debd1264bae8 | 19 | #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED |
| TanakaTarou | 11:debd1264bae8 | 20 | #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV |
| TanakaTarou | 11:debd1264bae8 | 21 | #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV |
| TanakaTarou | 11:debd1264bae8 | 22 | #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV |
| TanakaTarou | 11:debd1264bae8 | 23 | #define REGULAR_GROUP ADC_REGULAR_GROUP |
| TanakaTarou | 11:debd1264bae8 | 24 | #define INJECTED_GROUP ADC_INJECTED_GROUP |
| TanakaTarou | 11:debd1264bae8 | 25 | #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP |
| TanakaTarou | 11:debd1264bae8 | 26 | #define AWD_EVENT ADC_AWD_EVENT |
| TanakaTarou | 11:debd1264bae8 | 27 | #define AWD1_EVENT ADC_AWD1_EVENT |
| TanakaTarou | 11:debd1264bae8 | 28 | #define AWD2_EVENT ADC_AWD2_EVENT |
| TanakaTarou | 11:debd1264bae8 | 29 | #define AWD3_EVENT ADC_AWD3_EVENT |
| TanakaTarou | 11:debd1264bae8 | 30 | #define OVR_EVENT ADC_OVR_EVENT |
| TanakaTarou | 11:debd1264bae8 | 31 | #define JQOVF_EVENT ADC_JQOVF_EVENT |
| TanakaTarou | 11:debd1264bae8 | 32 | #define ALL_CHANNELS ADC_ALL_CHANNELS |
| TanakaTarou | 11:debd1264bae8 | 33 | #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS |
| TanakaTarou | 11:debd1264bae8 | 34 | #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS |
| TanakaTarou | 11:debd1264bae8 | 35 | #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR |
| TanakaTarou | 11:debd1264bae8 | 36 | #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT |
| TanakaTarou | 11:debd1264bae8 | 37 | #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 |
| TanakaTarou | 11:debd1264bae8 | 38 | #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 |
| TanakaTarou | 11:debd1264bae8 | 39 | #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 |
| TanakaTarou | 11:debd1264bae8 | 40 | #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 |
| TanakaTarou | 11:debd1264bae8 | 41 | #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 |
| TanakaTarou | 11:debd1264bae8 | 42 | #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO |
| TanakaTarou | 11:debd1264bae8 | 43 | #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 |
| TanakaTarou | 11:debd1264bae8 | 44 | #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO |
| TanakaTarou | 11:debd1264bae8 | 45 | #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 |
| TanakaTarou | 11:debd1264bae8 | 46 | #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO |
| TanakaTarou | 11:debd1264bae8 | 47 | #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 |
| TanakaTarou | 11:debd1264bae8 | 48 | #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 |
| TanakaTarou | 11:debd1264bae8 | 49 | #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE |
| TanakaTarou | 11:debd1264bae8 | 50 | #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING |
| TanakaTarou | 11:debd1264bae8 | 51 | #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING |
| TanakaTarou | 11:debd1264bae8 | 52 | #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING |
| TanakaTarou | 11:debd1264bae8 | 53 | #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 |
| TanakaTarou | 11:debd1264bae8 | 54 | |
| TanakaTarou | 11:debd1264bae8 | 55 | #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY |
| TanakaTarou | 11:debd1264bae8 | 56 | #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY |
| TanakaTarou | 11:debd1264bae8 | 57 | #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC |
| TanakaTarou | 11:debd1264bae8 | 58 | #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC |
| TanakaTarou | 11:debd1264bae8 | 59 | #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL |
| TanakaTarou | 11:debd1264bae8 | 60 | #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL |
| TanakaTarou | 11:debd1264bae8 | 61 | #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 |
| TanakaTarou | 11:debd1264bae8 | 62 | |
| TanakaTarou | 11:debd1264bae8 | 63 | #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG |
| TanakaTarou | 11:debd1264bae8 | 64 | |
| TanakaTarou | 11:debd1264bae8 | 65 | #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 66 | #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 67 | #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 |
| TanakaTarou | 11:debd1264bae8 | 68 | #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 |
| TanakaTarou | 11:debd1264bae8 | 69 | #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 |
| TanakaTarou | 11:debd1264bae8 | 70 | #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 |
| TanakaTarou | 11:debd1264bae8 | 71 | #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 |
| TanakaTarou | 11:debd1264bae8 | 72 | #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 |
| TanakaTarou | 11:debd1264bae8 | 73 | #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 |
| TanakaTarou | 11:debd1264bae8 | 74 | #define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */ |
| TanakaTarou | 11:debd1264bae8 | 75 | #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR |
| TanakaTarou | 11:debd1264bae8 | 76 | #if defined(STM32F373xC) || defined(STM32F378xx) |
| TanakaTarou | 11:debd1264bae8 | 77 | #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 |
| TanakaTarou | 11:debd1264bae8 | 78 | #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR |
| TanakaTarou | 11:debd1264bae8 | 79 | #endif /* STM32F373xC || STM32F378xx */ |
| TanakaTarou | 11:debd1264bae8 | 80 | |
| TanakaTarou | 11:debd1264bae8 | 81 | #if defined(STM32L0) || defined(STM32L4) |
| TanakaTarou | 11:debd1264bae8 | 82 | #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON |
| TanakaTarou | 11:debd1264bae8 | 83 | |
| TanakaTarou | 11:debd1264bae8 | 84 | #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 |
| TanakaTarou | 11:debd1264bae8 | 85 | #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 |
| TanakaTarou | 11:debd1264bae8 | 86 | #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 |
| TanakaTarou | 11:debd1264bae8 | 87 | #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 |
| TanakaTarou | 11:debd1264bae8 | 88 | #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 |
| TanakaTarou | 11:debd1264bae8 | 89 | #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 |
| TanakaTarou | 11:debd1264bae8 | 90 | |
| TanakaTarou | 11:debd1264bae8 | 91 | #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT |
| TanakaTarou | 11:debd1264bae8 | 92 | #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT |
| TanakaTarou | 11:debd1264bae8 | 93 | #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT |
| TanakaTarou | 11:debd1264bae8 | 94 | #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT |
| TanakaTarou | 11:debd1264bae8 | 95 | #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 |
| TanakaTarou | 11:debd1264bae8 | 96 | #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 |
| TanakaTarou | 11:debd1264bae8 | 97 | #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 |
| TanakaTarou | 11:debd1264bae8 | 98 | #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 |
| TanakaTarou | 11:debd1264bae8 | 99 | #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 |
| TanakaTarou | 11:debd1264bae8 | 100 | #if defined(STM32L0) |
| TanakaTarou | 11:debd1264bae8 | 101 | |
| TanakaTarou | 11:debd1264bae8 | 102 | #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 |
| TanakaTarou | 11:debd1264bae8 | 103 | #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 |
| TanakaTarou | 11:debd1264bae8 | 104 | #else |
| TanakaTarou | 11:debd1264bae8 | 105 | #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 |
| TanakaTarou | 11:debd1264bae8 | 106 | #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 |
| TanakaTarou | 11:debd1264bae8 | 107 | #endif |
| TanakaTarou | 11:debd1264bae8 | 108 | #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 |
| TanakaTarou | 11:debd1264bae8 | 109 | #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 |
| TanakaTarou | 11:debd1264bae8 | 110 | |
| TanakaTarou | 11:debd1264bae8 | 111 | #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW |
| TanakaTarou | 11:debd1264bae8 | 112 | #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH |
| TanakaTarou | 11:debd1264bae8 | 113 | |
| TanakaTarou | 11:debd1264bae8 | 114 | #if defined(COMP_CSR_LOCK) |
| TanakaTarou | 11:debd1264bae8 | 115 | #define COMP_FLAG_LOCK COMP_CSR_LOCK |
| TanakaTarou | 11:debd1264bae8 | 116 | #elif defined(COMP_CSR_COMP1LOCK) |
| TanakaTarou | 11:debd1264bae8 | 117 | #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK |
| TanakaTarou | 11:debd1264bae8 | 118 | #elif defined(COMP_CSR_COMPxLOCK) |
| TanakaTarou | 11:debd1264bae8 | 119 | #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK |
| TanakaTarou | 11:debd1264bae8 | 120 | #endif |
| TanakaTarou | 11:debd1264bae8 | 121 | |
| TanakaTarou | 11:debd1264bae8 | 122 | #if defined(STM32L4) |
| TanakaTarou | 11:debd1264bae8 | 123 | #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 |
| TanakaTarou | 11:debd1264bae8 | 124 | #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 |
| TanakaTarou | 11:debd1264bae8 | 125 | #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 |
| TanakaTarou | 11:debd1264bae8 | 126 | #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 |
| TanakaTarou | 11:debd1264bae8 | 127 | #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 |
| TanakaTarou | 11:debd1264bae8 | 128 | #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 |
| TanakaTarou | 11:debd1264bae8 | 129 | #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE |
| TanakaTarou | 11:debd1264bae8 | 130 | #endif |
| TanakaTarou | 11:debd1264bae8 | 131 | |
| TanakaTarou | 11:debd1264bae8 | 132 | #if defined(STM32L0) |
| TanakaTarou | 11:debd1264bae8 | 133 | #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED |
| TanakaTarou | 11:debd1264bae8 | 134 | #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER |
| TanakaTarou | 11:debd1264bae8 | 135 | #else |
| TanakaTarou | 11:debd1264bae8 | 136 | #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED |
| TanakaTarou | 11:debd1264bae8 | 137 | #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED |
| TanakaTarou | 11:debd1264bae8 | 138 | #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER |
| TanakaTarou | 11:debd1264bae8 | 139 | #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER |
| TanakaTarou | 11:debd1264bae8 | 140 | #endif |
| TanakaTarou | 11:debd1264bae8 | 141 | |
| TanakaTarou | 11:debd1264bae8 | 142 | #endif |
| TanakaTarou | 11:debd1264bae8 | 143 | |
| TanakaTarou | 11:debd1264bae8 | 144 | #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig |
| TanakaTarou | 11:debd1264bae8 | 145 | |
| TanakaTarou | 11:debd1264bae8 | 146 | #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 147 | #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 148 | |
| TanakaTarou | 11:debd1264bae8 | 149 | #define DAC1_CHANNEL_1 DAC_CHANNEL_1 |
| TanakaTarou | 11:debd1264bae8 | 150 | #define DAC1_CHANNEL_2 DAC_CHANNEL_2 |
| TanakaTarou | 11:debd1264bae8 | 151 | #define DAC2_CHANNEL_1 DAC_CHANNEL_1 |
| TanakaTarou | 11:debd1264bae8 | 152 | #define DAC_WAVE_NONE 0x00000000U |
| TanakaTarou | 11:debd1264bae8 | 153 | #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 |
| TanakaTarou | 11:debd1264bae8 | 154 | #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 |
| TanakaTarou | 11:debd1264bae8 | 155 | #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE |
| TanakaTarou | 11:debd1264bae8 | 156 | #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE |
| TanakaTarou | 11:debd1264bae8 | 157 | #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE |
| TanakaTarou | 11:debd1264bae8 | 158 | |
| TanakaTarou | 11:debd1264bae8 | 159 | #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 |
| TanakaTarou | 11:debd1264bae8 | 160 | #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 |
| TanakaTarou | 11:debd1264bae8 | 161 | #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 |
| TanakaTarou | 11:debd1264bae8 | 162 | #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 |
| TanakaTarou | 11:debd1264bae8 | 163 | #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 |
| TanakaTarou | 11:debd1264bae8 | 164 | #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 |
| TanakaTarou | 11:debd1264bae8 | 165 | #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 |
| TanakaTarou | 11:debd1264bae8 | 166 | #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 |
| TanakaTarou | 11:debd1264bae8 | 167 | #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 |
| TanakaTarou | 11:debd1264bae8 | 168 | #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 |
| TanakaTarou | 11:debd1264bae8 | 169 | #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 |
| TanakaTarou | 11:debd1264bae8 | 170 | #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 |
| TanakaTarou | 11:debd1264bae8 | 171 | #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 |
| TanakaTarou | 11:debd1264bae8 | 172 | #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 |
| TanakaTarou | 11:debd1264bae8 | 173 | #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 |
| TanakaTarou | 11:debd1264bae8 | 174 | |
| TanakaTarou | 11:debd1264bae8 | 175 | #define IS_HAL_REMAPDMA IS_DMA_REMAP |
| TanakaTarou | 11:debd1264bae8 | 176 | #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 177 | #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 178 | |
| TanakaTarou | 11:debd1264bae8 | 179 | #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE |
| TanakaTarou | 11:debd1264bae8 | 180 | #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD |
| TanakaTarou | 11:debd1264bae8 | 181 | #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD |
| TanakaTarou | 11:debd1264bae8 | 182 | #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD |
| TanakaTarou | 11:debd1264bae8 | 183 | #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS |
| TanakaTarou | 11:debd1264bae8 | 184 | #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES |
| TanakaTarou | 11:debd1264bae8 | 185 | #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES |
| TanakaTarou | 11:debd1264bae8 | 186 | #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE |
| TanakaTarou | 11:debd1264bae8 | 187 | #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 188 | #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 189 | #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE |
| TanakaTarou | 11:debd1264bae8 | 190 | #define OBEX_PCROP OPTIONBYTE_PCROP |
| TanakaTarou | 11:debd1264bae8 | 191 | #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG |
| TanakaTarou | 11:debd1264bae8 | 192 | #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 193 | #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 194 | #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE |
| TanakaTarou | 11:debd1264bae8 | 195 | #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD |
| TanakaTarou | 11:debd1264bae8 | 196 | #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD |
| TanakaTarou | 11:debd1264bae8 | 197 | #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE |
| TanakaTarou | 11:debd1264bae8 | 198 | #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD |
| TanakaTarou | 11:debd1264bae8 | 199 | #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD |
| TanakaTarou | 11:debd1264bae8 | 200 | #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE |
| TanakaTarou | 11:debd1264bae8 | 201 | #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD |
| TanakaTarou | 11:debd1264bae8 | 202 | #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD |
| TanakaTarou | 11:debd1264bae8 | 203 | #define PAGESIZE FLASH_PAGE_SIZE |
| TanakaTarou | 11:debd1264bae8 | 204 | #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE |
| TanakaTarou | 11:debd1264bae8 | 205 | #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD |
| TanakaTarou | 11:debd1264bae8 | 206 | #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD |
| TanakaTarou | 11:debd1264bae8 | 207 | #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 |
| TanakaTarou | 11:debd1264bae8 | 208 | #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 |
| TanakaTarou | 11:debd1264bae8 | 209 | #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 |
| TanakaTarou | 11:debd1264bae8 | 210 | #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 |
| TanakaTarou | 11:debd1264bae8 | 211 | #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST |
| TanakaTarou | 11:debd1264bae8 | 212 | #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST |
| TanakaTarou | 11:debd1264bae8 | 213 | #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA |
| TanakaTarou | 11:debd1264bae8 | 214 | #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB |
| TanakaTarou | 11:debd1264bae8 | 215 | #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA |
| TanakaTarou | 11:debd1264bae8 | 216 | #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB |
| TanakaTarou | 11:debd1264bae8 | 217 | #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE |
| TanakaTarou | 11:debd1264bae8 | 218 | #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN |
| TanakaTarou | 11:debd1264bae8 | 219 | #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE |
| TanakaTarou | 11:debd1264bae8 | 220 | #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN |
| TanakaTarou | 11:debd1264bae8 | 221 | #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE |
| TanakaTarou | 11:debd1264bae8 | 222 | #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD |
| TanakaTarou | 11:debd1264bae8 | 223 | #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG |
| TanakaTarou | 11:debd1264bae8 | 224 | #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS |
| TanakaTarou | 11:debd1264bae8 | 225 | #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP |
| TanakaTarou | 11:debd1264bae8 | 226 | #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV |
| TanakaTarou | 11:debd1264bae8 | 227 | #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR |
| TanakaTarou | 11:debd1264bae8 | 228 | #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG |
| TanakaTarou | 11:debd1264bae8 | 229 | #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION |
| TanakaTarou | 11:debd1264bae8 | 230 | #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA |
| TanakaTarou | 11:debd1264bae8 | 231 | #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE |
| TanakaTarou | 11:debd1264bae8 | 232 | #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE |
| TanakaTarou | 11:debd1264bae8 | 233 | #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS |
| TanakaTarou | 11:debd1264bae8 | 234 | #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS |
| TanakaTarou | 11:debd1264bae8 | 235 | #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST |
| TanakaTarou | 11:debd1264bae8 | 236 | #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR |
| TanakaTarou | 11:debd1264bae8 | 237 | #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO |
| TanakaTarou | 11:debd1264bae8 | 238 | #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION |
| TanakaTarou | 11:debd1264bae8 | 239 | #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS |
| TanakaTarou | 11:debd1264bae8 | 240 | #define OB_WDG_SW OB_IWDG_SW |
| TanakaTarou | 11:debd1264bae8 | 241 | #define OB_WDG_HW OB_IWDG_HW |
| TanakaTarou | 11:debd1264bae8 | 242 | #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET |
| TanakaTarou | 11:debd1264bae8 | 243 | #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET |
| TanakaTarou | 11:debd1264bae8 | 244 | #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET |
| TanakaTarou | 11:debd1264bae8 | 245 | #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET |
| TanakaTarou | 11:debd1264bae8 | 246 | #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR |
| TanakaTarou | 11:debd1264bae8 | 247 | #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 |
| TanakaTarou | 11:debd1264bae8 | 248 | #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 |
| TanakaTarou | 11:debd1264bae8 | 249 | #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 |
| TanakaTarou | 11:debd1264bae8 | 250 | |
| TanakaTarou | 11:debd1264bae8 | 251 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 |
| TanakaTarou | 11:debd1264bae8 | 252 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 |
| TanakaTarou | 11:debd1264bae8 | 253 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 |
| TanakaTarou | 11:debd1264bae8 | 254 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 |
| TanakaTarou | 11:debd1264bae8 | 255 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 |
| TanakaTarou | 11:debd1264bae8 | 256 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 |
| TanakaTarou | 11:debd1264bae8 | 257 | #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 |
| TanakaTarou | 11:debd1264bae8 | 258 | #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 |
| TanakaTarou | 11:debd1264bae8 | 259 | #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 |
| TanakaTarou | 11:debd1264bae8 | 260 | |
| TanakaTarou | 11:debd1264bae8 | 261 | #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) |
| TanakaTarou | 11:debd1264bae8 | 262 | #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 263 | #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 264 | #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 |
| TanakaTarou | 11:debd1264bae8 | 265 | #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 |
| TanakaTarou | 11:debd1264bae8 | 266 | #else |
| TanakaTarou | 11:debd1264bae8 | 267 | #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 268 | #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 269 | #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 |
| TanakaTarou | 11:debd1264bae8 | 270 | #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |
| TanakaTarou | 11:debd1264bae8 | 271 | #endif |
| TanakaTarou | 11:debd1264bae8 | 272 | |
| TanakaTarou | 11:debd1264bae8 | 273 | #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef |
| TanakaTarou | 11:debd1264bae8 | 274 | #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef |
| TanakaTarou | 11:debd1264bae8 | 275 | |
| TanakaTarou | 11:debd1264bae8 | 276 | #define GET_GPIO_SOURCE GPIO_GET_INDEX |
| TanakaTarou | 11:debd1264bae8 | 277 | #define GET_GPIO_INDEX GPIO_GET_INDEX |
| TanakaTarou | 11:debd1264bae8 | 278 | |
| TanakaTarou | 11:debd1264bae8 | 279 | #if defined(STM32F4) |
| TanakaTarou | 11:debd1264bae8 | 280 | #define GPIO_AF12_SDMMC GPIO_AF12_SDIO |
| TanakaTarou | 11:debd1264bae8 | 281 | #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO |
| TanakaTarou | 11:debd1264bae8 | 282 | #endif |
| TanakaTarou | 11:debd1264bae8 | 283 | |
| TanakaTarou | 11:debd1264bae8 | 284 | #if defined(STM32F7) |
| TanakaTarou | 11:debd1264bae8 | 285 | #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 |
| TanakaTarou | 11:debd1264bae8 | 286 | #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 |
| TanakaTarou | 11:debd1264bae8 | 287 | #endif |
| TanakaTarou | 11:debd1264bae8 | 288 | |
| TanakaTarou | 11:debd1264bae8 | 289 | #if defined(STM32L4) |
| TanakaTarou | 11:debd1264bae8 | 290 | #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 |
| TanakaTarou | 11:debd1264bae8 | 291 | #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 |
| TanakaTarou | 11:debd1264bae8 | 292 | #endif |
| TanakaTarou | 11:debd1264bae8 | 293 | |
| TanakaTarou | 11:debd1264bae8 | 294 | #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 |
| TanakaTarou | 11:debd1264bae8 | 295 | #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 |
| TanakaTarou | 11:debd1264bae8 | 296 | #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 |
| TanakaTarou | 11:debd1264bae8 | 297 | |
| TanakaTarou | 11:debd1264bae8 | 298 | #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) |
| TanakaTarou | 11:debd1264bae8 | 299 | #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW |
| TanakaTarou | 11:debd1264bae8 | 300 | #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM |
| TanakaTarou | 11:debd1264bae8 | 301 | #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH |
| TanakaTarou | 11:debd1264bae8 | 302 | #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH |
| TanakaTarou | 11:debd1264bae8 | 303 | #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ |
| TanakaTarou | 11:debd1264bae8 | 304 | |
| TanakaTarou | 11:debd1264bae8 | 305 | #if defined(STM32L1) |
| TanakaTarou | 11:debd1264bae8 | 306 | #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW |
| TanakaTarou | 11:debd1264bae8 | 307 | #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM |
| TanakaTarou | 11:debd1264bae8 | 308 | #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH |
| TanakaTarou | 11:debd1264bae8 | 309 | #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH |
| TanakaTarou | 11:debd1264bae8 | 310 | #endif /* STM32L1 */ |
| TanakaTarou | 11:debd1264bae8 | 311 | |
| TanakaTarou | 11:debd1264bae8 | 312 | #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) |
| TanakaTarou | 11:debd1264bae8 | 313 | #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW |
| TanakaTarou | 11:debd1264bae8 | 314 | #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM |
| TanakaTarou | 11:debd1264bae8 | 315 | #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH |
| TanakaTarou | 11:debd1264bae8 | 316 | #endif /* STM32F0 || STM32F3 || STM32F1 */ |
| TanakaTarou | 11:debd1264bae8 | 317 | |
| TanakaTarou | 11:debd1264bae8 | 318 | #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 |
| TanakaTarou | 11:debd1264bae8 | 319 | |
| TanakaTarou | 11:debd1264bae8 | 320 | #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 321 | #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 |
| TanakaTarou | 11:debd1264bae8 | 322 | #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 |
| TanakaTarou | 11:debd1264bae8 | 323 | #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 |
| TanakaTarou | 11:debd1264bae8 | 324 | #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 |
| TanakaTarou | 11:debd1264bae8 | 325 | #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 |
| TanakaTarou | 11:debd1264bae8 | 326 | #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 |
| TanakaTarou | 11:debd1264bae8 | 327 | #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 |
| TanakaTarou | 11:debd1264bae8 | 328 | #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 |
| TanakaTarou | 11:debd1264bae8 | 329 | |
| TanakaTarou | 11:debd1264bae8 | 330 | #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER |
| TanakaTarou | 11:debd1264bae8 | 331 | #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER |
| TanakaTarou | 11:debd1264bae8 | 332 | #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD |
| TanakaTarou | 11:debd1264bae8 | 333 | #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD |
| TanakaTarou | 11:debd1264bae8 | 334 | #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER |
| TanakaTarou | 11:debd1264bae8 | 335 | #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER |
| TanakaTarou | 11:debd1264bae8 | 336 | #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE |
| TanakaTarou | 11:debd1264bae8 | 337 | #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE |
| TanakaTarou | 11:debd1264bae8 | 338 | |
| TanakaTarou | 11:debd1264bae8 | 339 | #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 340 | #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 341 | #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 342 | #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 343 | #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 344 | #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 345 | #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 346 | #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 347 | #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) |
| TanakaTarou | 11:debd1264bae8 | 348 | #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX |
| TanakaTarou | 11:debd1264bae8 | 349 | #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX |
| TanakaTarou | 11:debd1264bae8 | 350 | #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX |
| TanakaTarou | 11:debd1264bae8 | 351 | #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX |
| TanakaTarou | 11:debd1264bae8 | 352 | #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX |
| TanakaTarou | 11:debd1264bae8 | 353 | #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX |
| TanakaTarou | 11:debd1264bae8 | 354 | #endif |
| TanakaTarou | 11:debd1264bae8 | 355 | |
| TanakaTarou | 11:debd1264bae8 | 356 | #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 357 | #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 358 | |
| TanakaTarou | 11:debd1264bae8 | 359 | #define KR_KEY_RELOAD IWDG_KEY_RELOAD |
| TanakaTarou | 11:debd1264bae8 | 360 | #define KR_KEY_ENABLE IWDG_KEY_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 361 | #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 362 | #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 363 | |
| TanakaTarou | 11:debd1264bae8 | 364 | |
| TanakaTarou | 11:debd1264bae8 | 365 | #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION |
| TanakaTarou | 11:debd1264bae8 | 366 | #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS |
| TanakaTarou | 11:debd1264bae8 | 367 | #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS |
| TanakaTarou | 11:debd1264bae8 | 368 | #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS |
| TanakaTarou | 11:debd1264bae8 | 369 | |
| TanakaTarou | 11:debd1264bae8 | 370 | #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING |
| TanakaTarou | 11:debd1264bae8 | 371 | #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING |
| TanakaTarou | 11:debd1264bae8 | 372 | #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING |
| TanakaTarou | 11:debd1264bae8 | 373 | |
| TanakaTarou | 11:debd1264bae8 | 374 | #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION |
| TanakaTarou | 11:debd1264bae8 | 375 | #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS |
| TanakaTarou | 11:debd1264bae8 | 376 | #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS |
| TanakaTarou | 11:debd1264bae8 | 377 | #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS |
| TanakaTarou | 11:debd1264bae8 | 378 | |
| TanakaTarou | 11:debd1264bae8 | 379 | #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS |
| TanakaTarou | 11:debd1264bae8 | 380 | #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS |
| TanakaTarou | 11:debd1264bae8 | 381 | #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS |
| TanakaTarou | 11:debd1264bae8 | 382 | |
| TanakaTarou | 11:debd1264bae8 | 383 | #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b |
| TanakaTarou | 11:debd1264bae8 | 384 | #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b |
| TanakaTarou | 11:debd1264bae8 | 385 | #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b |
| TanakaTarou | 11:debd1264bae8 | 386 | #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b |
| TanakaTarou | 11:debd1264bae8 | 387 | |
| TanakaTarou | 11:debd1264bae8 | 388 | #define NAND_AddressTypedef NAND_AddressTypeDef |
| TanakaTarou | 11:debd1264bae8 | 389 | |
| TanakaTarou | 11:debd1264bae8 | 390 | #define __ARRAY_ADDRESS ARRAY_ADDRESS |
| TanakaTarou | 11:debd1264bae8 | 391 | #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE |
| TanakaTarou | 11:debd1264bae8 | 392 | #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE |
| TanakaTarou | 11:debd1264bae8 | 393 | #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE |
| TanakaTarou | 11:debd1264bae8 | 394 | #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE |
| TanakaTarou | 11:debd1264bae8 | 395 | |
| TanakaTarou | 11:debd1264bae8 | 396 | #define NOR_StatusTypedef HAL_NOR_StatusTypeDef |
| TanakaTarou | 11:debd1264bae8 | 397 | #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS |
| TanakaTarou | 11:debd1264bae8 | 398 | #define NOR_ONGOING HAL_NOR_STATUS_ONGOING |
| TanakaTarou | 11:debd1264bae8 | 399 | #define NOR_ERROR HAL_NOR_STATUS_ERROR |
| TanakaTarou | 11:debd1264bae8 | 400 | #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT |
| TanakaTarou | 11:debd1264bae8 | 401 | |
| TanakaTarou | 11:debd1264bae8 | 402 | #define __NOR_WRITE NOR_WRITE |
| TanakaTarou | 11:debd1264bae8 | 403 | #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT |
| TanakaTarou | 11:debd1264bae8 | 404 | |
| TanakaTarou | 11:debd1264bae8 | 405 | #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 |
| TanakaTarou | 11:debd1264bae8 | 406 | #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 |
| TanakaTarou | 11:debd1264bae8 | 407 | #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 |
| TanakaTarou | 11:debd1264bae8 | 408 | #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 |
| TanakaTarou | 11:debd1264bae8 | 409 | |
| TanakaTarou | 11:debd1264bae8 | 410 | #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 |
| TanakaTarou | 11:debd1264bae8 | 411 | #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 |
| TanakaTarou | 11:debd1264bae8 | 412 | #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 |
| TanakaTarou | 11:debd1264bae8 | 413 | #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 |
| TanakaTarou | 11:debd1264bae8 | 414 | |
| TanakaTarou | 11:debd1264bae8 | 415 | #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 |
| TanakaTarou | 11:debd1264bae8 | 416 | #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 |
| TanakaTarou | 11:debd1264bae8 | 417 | |
| TanakaTarou | 11:debd1264bae8 | 418 | #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 |
| TanakaTarou | 11:debd1264bae8 | 419 | #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 |
| TanakaTarou | 11:debd1264bae8 | 420 | |
| TanakaTarou | 11:debd1264bae8 | 421 | #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 |
| TanakaTarou | 11:debd1264bae8 | 422 | #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 |
| TanakaTarou | 11:debd1264bae8 | 423 | |
| TanakaTarou | 11:debd1264bae8 | 424 | #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 |
| TanakaTarou | 11:debd1264bae8 | 425 | |
| TanakaTarou | 11:debd1264bae8 | 426 | #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO |
| TanakaTarou | 11:debd1264bae8 | 427 | #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 |
| TanakaTarou | 11:debd1264bae8 | 428 | #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 |
| TanakaTarou | 11:debd1264bae8 | 429 | |
| TanakaTarou | 11:debd1264bae8 | 430 | #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS |
| TanakaTarou | 11:debd1264bae8 | 431 | #if defined(STM32F7) |
| TanakaTarou | 11:debd1264bae8 | 432 | #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL |
| TanakaTarou | 11:debd1264bae8 | 433 | #endif |
| TanakaTarou | 11:debd1264bae8 | 434 | |
| TanakaTarou | 11:debd1264bae8 | 435 | /* Compact Flash-ATA registers description */ |
| TanakaTarou | 11:debd1264bae8 | 436 | #define CF_DATA ATA_DATA |
| TanakaTarou | 11:debd1264bae8 | 437 | #define CF_SECTOR_COUNT ATA_SECTOR_COUNT |
| TanakaTarou | 11:debd1264bae8 | 438 | #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 439 | #define CF_CYLINDER_LOW ATA_CYLINDER_LOW |
| TanakaTarou | 11:debd1264bae8 | 440 | #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH |
| TanakaTarou | 11:debd1264bae8 | 441 | #define CF_CARD_HEAD ATA_CARD_HEAD |
| TanakaTarou | 11:debd1264bae8 | 442 | #define CF_STATUS_CMD ATA_STATUS_CMD |
| TanakaTarou | 11:debd1264bae8 | 443 | #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE |
| TanakaTarou | 11:debd1264bae8 | 444 | #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA |
| TanakaTarou | 11:debd1264bae8 | 445 | |
| TanakaTarou | 11:debd1264bae8 | 446 | /* Compact Flash-ATA commands */ |
| TanakaTarou | 11:debd1264bae8 | 447 | #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD |
| TanakaTarou | 11:debd1264bae8 | 448 | #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD |
| TanakaTarou | 11:debd1264bae8 | 449 | #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD |
| TanakaTarou | 11:debd1264bae8 | 450 | #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD |
| TanakaTarou | 11:debd1264bae8 | 451 | |
| TanakaTarou | 11:debd1264bae8 | 452 | #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef |
| TanakaTarou | 11:debd1264bae8 | 453 | #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS |
| TanakaTarou | 11:debd1264bae8 | 454 | #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING |
| TanakaTarou | 11:debd1264bae8 | 455 | #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR |
| TanakaTarou | 11:debd1264bae8 | 456 | #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT |
| TanakaTarou | 11:debd1264bae8 | 457 | |
| TanakaTarou | 11:debd1264bae8 | 458 | #define FORMAT_BIN RTC_FORMAT_BIN |
| TanakaTarou | 11:debd1264bae8 | 459 | #define FORMAT_BCD RTC_FORMAT_BCD |
| TanakaTarou | 11:debd1264bae8 | 460 | |
| TanakaTarou | 11:debd1264bae8 | 461 | #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE |
| TanakaTarou | 11:debd1264bae8 | 462 | #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 463 | #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 464 | #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 465 | #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 466 | |
| TanakaTarou | 11:debd1264bae8 | 467 | #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 468 | #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 469 | #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 470 | #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 471 | #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 472 | #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 473 | #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT |
| TanakaTarou | 11:debd1264bae8 | 474 | #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT |
| TanakaTarou | 11:debd1264bae8 | 475 | |
| TanakaTarou | 11:debd1264bae8 | 476 | #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT |
| TanakaTarou | 11:debd1264bae8 | 477 | #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 |
| TanakaTarou | 11:debd1264bae8 | 478 | #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 |
| TanakaTarou | 11:debd1264bae8 | 479 | #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 |
| TanakaTarou | 11:debd1264bae8 | 480 | |
| TanakaTarou | 11:debd1264bae8 | 481 | #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE |
| TanakaTarou | 11:debd1264bae8 | 482 | #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 |
| TanakaTarou | 11:debd1264bae8 | 483 | #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 |
| TanakaTarou | 11:debd1264bae8 | 484 | |
| TanakaTarou | 11:debd1264bae8 | 485 | #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT |
| TanakaTarou | 11:debd1264bae8 | 486 | #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 |
| TanakaTarou | 11:debd1264bae8 | 487 | #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 |
| TanakaTarou | 11:debd1264bae8 | 488 | |
| TanakaTarou | 11:debd1264bae8 | 489 | #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 490 | #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 491 | |
| TanakaTarou | 11:debd1264bae8 | 492 | #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 493 | #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 494 | #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 495 | #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 496 | |
| TanakaTarou | 11:debd1264bae8 | 497 | #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 498 | #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 499 | |
| TanakaTarou | 11:debd1264bae8 | 500 | #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 501 | #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 502 | |
| TanakaTarou | 11:debd1264bae8 | 503 | #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 504 | #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 505 | #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 506 | #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 507 | #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 508 | #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 509 | #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 510 | #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 511 | #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 512 | #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 513 | #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN |
| TanakaTarou | 11:debd1264bae8 | 514 | |
| TanakaTarou | 11:debd1264bae8 | 515 | #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 516 | #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 517 | |
| TanakaTarou | 11:debd1264bae8 | 518 | #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 519 | #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 520 | |
| TanakaTarou | 11:debd1264bae8 | 521 | #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 522 | #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 523 | |
| TanakaTarou | 11:debd1264bae8 | 524 | |
| TanakaTarou | 11:debd1264bae8 | 525 | #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK |
| TanakaTarou | 11:debd1264bae8 | 526 | #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK |
| TanakaTarou | 11:debd1264bae8 | 527 | |
| TanakaTarou | 11:debd1264bae8 | 528 | #define TIM_DMABase_CR1 TIM_DMABASE_CR1 |
| TanakaTarou | 11:debd1264bae8 | 529 | #define TIM_DMABase_CR2 TIM_DMABASE_CR2 |
| TanakaTarou | 11:debd1264bae8 | 530 | #define TIM_DMABase_SMCR TIM_DMABASE_SMCR |
| TanakaTarou | 11:debd1264bae8 | 531 | #define TIM_DMABase_DIER TIM_DMABASE_DIER |
| TanakaTarou | 11:debd1264bae8 | 532 | #define TIM_DMABase_SR TIM_DMABASE_SR |
| TanakaTarou | 11:debd1264bae8 | 533 | #define TIM_DMABase_EGR TIM_DMABASE_EGR |
| TanakaTarou | 11:debd1264bae8 | 534 | #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 |
| TanakaTarou | 11:debd1264bae8 | 535 | #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 |
| TanakaTarou | 11:debd1264bae8 | 536 | #define TIM_DMABase_CCER TIM_DMABASE_CCER |
| TanakaTarou | 11:debd1264bae8 | 537 | #define TIM_DMABase_CNT TIM_DMABASE_CNT |
| TanakaTarou | 11:debd1264bae8 | 538 | #define TIM_DMABase_PSC TIM_DMABASE_PSC |
| TanakaTarou | 11:debd1264bae8 | 539 | #define TIM_DMABase_ARR TIM_DMABASE_ARR |
| TanakaTarou | 11:debd1264bae8 | 540 | #define TIM_DMABase_RCR TIM_DMABASE_RCR |
| TanakaTarou | 11:debd1264bae8 | 541 | #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 |
| TanakaTarou | 11:debd1264bae8 | 542 | #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 |
| TanakaTarou | 11:debd1264bae8 | 543 | #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 |
| TanakaTarou | 11:debd1264bae8 | 544 | #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 |
| TanakaTarou | 11:debd1264bae8 | 545 | #define TIM_DMABase_BDTR TIM_DMABASE_BDTR |
| TanakaTarou | 11:debd1264bae8 | 546 | #define TIM_DMABase_DCR TIM_DMABASE_DCR |
| TanakaTarou | 11:debd1264bae8 | 547 | #define TIM_DMABase_DMAR TIM_DMABASE_DMAR |
| TanakaTarou | 11:debd1264bae8 | 548 | #define TIM_DMABase_OR1 TIM_DMABASE_OR1 |
| TanakaTarou | 11:debd1264bae8 | 549 | #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 |
| TanakaTarou | 11:debd1264bae8 | 550 | #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 |
| TanakaTarou | 11:debd1264bae8 | 551 | #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 |
| TanakaTarou | 11:debd1264bae8 | 552 | #define TIM_DMABase_OR2 TIM_DMABASE_OR2 |
| TanakaTarou | 11:debd1264bae8 | 553 | #define TIM_DMABase_OR3 TIM_DMABASE_OR3 |
| TanakaTarou | 11:debd1264bae8 | 554 | #define TIM_DMABase_OR TIM_DMABASE_OR |
| TanakaTarou | 11:debd1264bae8 | 555 | |
| TanakaTarou | 11:debd1264bae8 | 556 | #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE |
| TanakaTarou | 11:debd1264bae8 | 557 | #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 |
| TanakaTarou | 11:debd1264bae8 | 558 | #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 |
| TanakaTarou | 11:debd1264bae8 | 559 | #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 |
| TanakaTarou | 11:debd1264bae8 | 560 | #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 |
| TanakaTarou | 11:debd1264bae8 | 561 | #define TIM_EventSource_COM TIM_EVENTSOURCE_COM |
| TanakaTarou | 11:debd1264bae8 | 562 | #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER |
| TanakaTarou | 11:debd1264bae8 | 563 | #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK |
| TanakaTarou | 11:debd1264bae8 | 564 | #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 |
| TanakaTarou | 11:debd1264bae8 | 565 | |
| TanakaTarou | 11:debd1264bae8 | 566 | #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER |
| TanakaTarou | 11:debd1264bae8 | 567 | #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS |
| TanakaTarou | 11:debd1264bae8 | 568 | #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS |
| TanakaTarou | 11:debd1264bae8 | 569 | #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS |
| TanakaTarou | 11:debd1264bae8 | 570 | #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS |
| TanakaTarou | 11:debd1264bae8 | 571 | #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS |
| TanakaTarou | 11:debd1264bae8 | 572 | #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS |
| TanakaTarou | 11:debd1264bae8 | 573 | #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS |
| TanakaTarou | 11:debd1264bae8 | 574 | #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS |
| TanakaTarou | 11:debd1264bae8 | 575 | #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS |
| TanakaTarou | 11:debd1264bae8 | 576 | #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS |
| TanakaTarou | 11:debd1264bae8 | 577 | #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS |
| TanakaTarou | 11:debd1264bae8 | 578 | #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS |
| TanakaTarou | 11:debd1264bae8 | 579 | #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS |
| TanakaTarou | 11:debd1264bae8 | 580 | #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS |
| TanakaTarou | 11:debd1264bae8 | 581 | #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS |
| TanakaTarou | 11:debd1264bae8 | 582 | #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS |
| TanakaTarou | 11:debd1264bae8 | 583 | #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS |
| TanakaTarou | 11:debd1264bae8 | 584 | |
| TanakaTarou | 11:debd1264bae8 | 585 | #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING |
| TanakaTarou | 11:debd1264bae8 | 586 | #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING |
| TanakaTarou | 11:debd1264bae8 | 587 | |
| TanakaTarou | 11:debd1264bae8 | 588 | #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 589 | #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 590 | #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 591 | #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 592 | |
| TanakaTarou | 11:debd1264bae8 | 593 | #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 594 | #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 595 | |
| TanakaTarou | 11:debd1264bae8 | 596 | #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 |
| TanakaTarou | 11:debd1264bae8 | 597 | #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 |
| TanakaTarou | 11:debd1264bae8 | 598 | #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 |
| TanakaTarou | 11:debd1264bae8 | 599 | #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 |
| TanakaTarou | 11:debd1264bae8 | 600 | |
| TanakaTarou | 11:debd1264bae8 | 601 | #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 |
| TanakaTarou | 11:debd1264bae8 | 602 | #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 |
| TanakaTarou | 11:debd1264bae8 | 603 | #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 |
| TanakaTarou | 11:debd1264bae8 | 604 | #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 |
| TanakaTarou | 11:debd1264bae8 | 605 | |
| TanakaTarou | 11:debd1264bae8 | 606 | #define __DIV_LPUART UART_DIV_LPUART |
| TanakaTarou | 11:debd1264bae8 | 607 | |
| TanakaTarou | 11:debd1264bae8 | 608 | #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE |
| TanakaTarou | 11:debd1264bae8 | 609 | #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK |
| TanakaTarou | 11:debd1264bae8 | 610 | |
| TanakaTarou | 11:debd1264bae8 | 611 | #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 612 | #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 613 | |
| TanakaTarou | 11:debd1264bae8 | 614 | #define USARTNACK_ENABLED USART_NACK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 615 | #define USARTNACK_DISABLED USART_NACK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 616 | |
| TanakaTarou | 11:debd1264bae8 | 617 | #define CFR_BASE WWDG_CFR_BASE |
| TanakaTarou | 11:debd1264bae8 | 618 | |
| TanakaTarou | 11:debd1264bae8 | 619 | #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 |
| TanakaTarou | 11:debd1264bae8 | 620 | #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 |
| TanakaTarou | 11:debd1264bae8 | 621 | #define CAN_IT_RQCP0 CAN_IT_TME |
| TanakaTarou | 11:debd1264bae8 | 622 | #define CAN_IT_RQCP1 CAN_IT_TME |
| TanakaTarou | 11:debd1264bae8 | 623 | #define CAN_IT_RQCP2 CAN_IT_TME |
| TanakaTarou | 11:debd1264bae8 | 624 | #define INAK_TIMEOUT CAN_TIMEOUT_VALUE |
| TanakaTarou | 11:debd1264bae8 | 625 | #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE |
| TanakaTarou | 11:debd1264bae8 | 626 | #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) |
| TanakaTarou | 11:debd1264bae8 | 627 | #define CAN_TXSTATUS_OK ((uint8_t)0x01U) |
| TanakaTarou | 11:debd1264bae8 | 628 | #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) |
| TanakaTarou | 11:debd1264bae8 | 629 | |
| TanakaTarou | 11:debd1264bae8 | 630 | #define VLAN_TAG ETH_VLAN_TAG |
| TanakaTarou | 11:debd1264bae8 | 631 | #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD |
| TanakaTarou | 11:debd1264bae8 | 632 | #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD |
| TanakaTarou | 11:debd1264bae8 | 633 | #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD |
| TanakaTarou | 11:debd1264bae8 | 634 | #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK |
| TanakaTarou | 11:debd1264bae8 | 635 | #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK |
| TanakaTarou | 11:debd1264bae8 | 636 | #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK |
| TanakaTarou | 11:debd1264bae8 | 637 | #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK |
| TanakaTarou | 11:debd1264bae8 | 638 | |
| TanakaTarou | 11:debd1264bae8 | 639 | #define ETH_MMCCR 0x00000100U |
| TanakaTarou | 11:debd1264bae8 | 640 | #define ETH_MMCRIR 0x00000104U |
| TanakaTarou | 11:debd1264bae8 | 641 | #define ETH_MMCTIR 0x00000108U |
| TanakaTarou | 11:debd1264bae8 | 642 | #define ETH_MMCRIMR 0x0000010CU |
| TanakaTarou | 11:debd1264bae8 | 643 | #define ETH_MMCTIMR 0x00000110U |
| TanakaTarou | 11:debd1264bae8 | 644 | #define ETH_MMCTGFSCCR 0x0000014CU |
| TanakaTarou | 11:debd1264bae8 | 645 | #define ETH_MMCTGFMSCCR 0x00000150U |
| TanakaTarou | 11:debd1264bae8 | 646 | #define ETH_MMCTGFCR 0x00000168U |
| TanakaTarou | 11:debd1264bae8 | 647 | #define ETH_MMCRFCECR 0x00000194U |
| TanakaTarou | 11:debd1264bae8 | 648 | #define ETH_MMCRFAECR 0x00000198U |
| TanakaTarou | 11:debd1264bae8 | 649 | #define ETH_MMCRGUFCR 0x000001C4U |
| TanakaTarou | 11:debd1264bae8 | 650 | |
| TanakaTarou | 11:debd1264bae8 | 651 | #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ |
| TanakaTarou | 11:debd1264bae8 | 652 | #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ |
| TanakaTarou | 11:debd1264bae8 | 653 | #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ |
| TanakaTarou | 11:debd1264bae8 | 654 | #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ |
| TanakaTarou | 11:debd1264bae8 | 655 | #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ |
| TanakaTarou | 11:debd1264bae8 | 656 | #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ |
| TanakaTarou | 11:debd1264bae8 | 657 | #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ |
| TanakaTarou | 11:debd1264bae8 | 658 | #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ |
| TanakaTarou | 11:debd1264bae8 | 659 | #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ |
| TanakaTarou | 11:debd1264bae8 | 660 | #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ |
| TanakaTarou | 11:debd1264bae8 | 661 | #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ |
| TanakaTarou | 11:debd1264bae8 | 662 | #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ |
| TanakaTarou | 11:debd1264bae8 | 663 | #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ |
| TanakaTarou | 11:debd1264bae8 | 664 | #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ |
| TanakaTarou | 11:debd1264bae8 | 665 | #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ |
| TanakaTarou | 11:debd1264bae8 | 666 | #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ |
| TanakaTarou | 11:debd1264bae8 | 667 | #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ |
| TanakaTarou | 11:debd1264bae8 | 668 | #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ |
| TanakaTarou | 11:debd1264bae8 | 669 | #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ |
| TanakaTarou | 11:debd1264bae8 | 670 | #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ |
| TanakaTarou | 11:debd1264bae8 | 671 | #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ |
| TanakaTarou | 11:debd1264bae8 | 672 | #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ |
| TanakaTarou | 11:debd1264bae8 | 673 | #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ |
| TanakaTarou | 11:debd1264bae8 | 674 | #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ |
| TanakaTarou | 11:debd1264bae8 | 675 | #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ |
| TanakaTarou | 11:debd1264bae8 | 676 | #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ |
| TanakaTarou | 11:debd1264bae8 | 677 | #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ |
| TanakaTarou | 11:debd1264bae8 | 678 | |
| TanakaTarou | 11:debd1264bae8 | 679 | #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR |
| TanakaTarou | 11:debd1264bae8 | 680 | #define DCMI_IT_OVF DCMI_IT_OVR |
| TanakaTarou | 11:debd1264bae8 | 681 | #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI |
| TanakaTarou | 11:debd1264bae8 | 682 | #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI |
| TanakaTarou | 11:debd1264bae8 | 683 | |
| TanakaTarou | 11:debd1264bae8 | 684 | #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop |
| TanakaTarou | 11:debd1264bae8 | 685 | #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop |
| TanakaTarou | 11:debd1264bae8 | 686 | #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop |
| TanakaTarou | 11:debd1264bae8 | 687 | |
| TanakaTarou | 11:debd1264bae8 | 688 | |
| TanakaTarou | 11:debd1264bae8 | 689 | #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ |
| TanakaTarou | 11:debd1264bae8 | 690 | defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| TanakaTarou | 11:debd1264bae8 | 691 | |
| TanakaTarou | 11:debd1264bae8 | 692 | #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 |
| TanakaTarou | 11:debd1264bae8 | 693 | #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 |
| TanakaTarou | 11:debd1264bae8 | 694 | #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 |
| TanakaTarou | 11:debd1264bae8 | 695 | #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 |
| TanakaTarou | 11:debd1264bae8 | 696 | #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 |
| TanakaTarou | 11:debd1264bae8 | 697 | |
| TanakaTarou | 11:debd1264bae8 | 698 | #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 |
| TanakaTarou | 11:debd1264bae8 | 699 | #define CM_RGB888 DMA2D_INPUT_RGB888 |
| TanakaTarou | 11:debd1264bae8 | 700 | #define CM_RGB565 DMA2D_INPUT_RGB565 |
| TanakaTarou | 11:debd1264bae8 | 701 | #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 |
| TanakaTarou | 11:debd1264bae8 | 702 | #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 |
| TanakaTarou | 11:debd1264bae8 | 703 | #define CM_L8 DMA2D_INPUT_L8 |
| TanakaTarou | 11:debd1264bae8 | 704 | #define CM_AL44 DMA2D_INPUT_AL44 |
| TanakaTarou | 11:debd1264bae8 | 705 | #define CM_AL88 DMA2D_INPUT_AL88 |
| TanakaTarou | 11:debd1264bae8 | 706 | #define CM_L4 DMA2D_INPUT_L4 |
| TanakaTarou | 11:debd1264bae8 | 707 | #define CM_A8 DMA2D_INPUT_A8 |
| TanakaTarou | 11:debd1264bae8 | 708 | #define CM_A4 DMA2D_INPUT_A4 |
| TanakaTarou | 11:debd1264bae8 | 709 | |
| TanakaTarou | 11:debd1264bae8 | 710 | #endif /* STM32L4 || STM32F7*/ |
| TanakaTarou | 11:debd1264bae8 | 711 | |
| TanakaTarou | 11:debd1264bae8 | 712 | #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback |
| TanakaTarou | 11:debd1264bae8 | 713 | |
| TanakaTarou | 11:debd1264bae8 | 714 | #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef |
| TanakaTarou | 11:debd1264bae8 | 715 | #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef |
| TanakaTarou | 11:debd1264bae8 | 716 | #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish |
| TanakaTarou | 11:debd1264bae8 | 717 | #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish |
| TanakaTarou | 11:debd1264bae8 | 718 | #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish |
| TanakaTarou | 11:debd1264bae8 | 719 | #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish |
| TanakaTarou | 11:debd1264bae8 | 720 | |
| TanakaTarou | 11:debd1264bae8 | 721 | /*HASH Algorithm Selection*/ |
| TanakaTarou | 11:debd1264bae8 | 722 | |
| TanakaTarou | 11:debd1264bae8 | 723 | #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 |
| TanakaTarou | 11:debd1264bae8 | 724 | #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 |
| TanakaTarou | 11:debd1264bae8 | 725 | #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 |
| TanakaTarou | 11:debd1264bae8 | 726 | #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 |
| TanakaTarou | 11:debd1264bae8 | 727 | |
| TanakaTarou | 11:debd1264bae8 | 728 | #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH |
| TanakaTarou | 11:debd1264bae8 | 729 | #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC |
| TanakaTarou | 11:debd1264bae8 | 730 | |
| TanakaTarou | 11:debd1264bae8 | 731 | #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY |
| TanakaTarou | 11:debd1264bae8 | 732 | #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY |
| TanakaTarou | 11:debd1264bae8 | 733 | |
| TanakaTarou | 11:debd1264bae8 | 734 | #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode |
| TanakaTarou | 11:debd1264bae8 | 735 | #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode |
| TanakaTarou | 11:debd1264bae8 | 736 | #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode |
| TanakaTarou | 11:debd1264bae8 | 737 | #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode |
| TanakaTarou | 11:debd1264bae8 | 738 | #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode |
| TanakaTarou | 11:debd1264bae8 | 739 | #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode |
| TanakaTarou | 11:debd1264bae8 | 740 | #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) |
| TanakaTarou | 11:debd1264bae8 | 741 | #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect |
| TanakaTarou | 11:debd1264bae8 | 742 | #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) |
| TanakaTarou | 11:debd1264bae8 | 743 | #if defined(STM32L0) |
| TanakaTarou | 11:debd1264bae8 | 744 | #else |
| TanakaTarou | 11:debd1264bae8 | 745 | #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) |
| TanakaTarou | 11:debd1264bae8 | 746 | #endif |
| TanakaTarou | 11:debd1264bae8 | 747 | #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) |
| TanakaTarou | 11:debd1264bae8 | 748 | #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) |
| TanakaTarou | 11:debd1264bae8 | 749 | |
| TanakaTarou | 11:debd1264bae8 | 750 | #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram |
| TanakaTarou | 11:debd1264bae8 | 751 | #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown |
| TanakaTarou | 11:debd1264bae8 | 752 | #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown |
| TanakaTarou | 11:debd1264bae8 | 753 | #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock |
| TanakaTarou | 11:debd1264bae8 | 754 | #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock |
| TanakaTarou | 11:debd1264bae8 | 755 | #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase |
| TanakaTarou | 11:debd1264bae8 | 756 | #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program |
| TanakaTarou | 11:debd1264bae8 | 757 | |
| TanakaTarou | 11:debd1264bae8 | 758 | #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter |
| TanakaTarou | 11:debd1264bae8 | 759 | #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter |
| TanakaTarou | 11:debd1264bae8 | 760 | #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter |
| TanakaTarou | 11:debd1264bae8 | 761 | #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter |
| TanakaTarou | 11:debd1264bae8 | 762 | |
| TanakaTarou | 11:debd1264bae8 | 763 | #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) |
| TanakaTarou | 11:debd1264bae8 | 764 | |
| TanakaTarou | 11:debd1264bae8 | 765 | #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD |
| TanakaTarou | 11:debd1264bae8 | 766 | #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg |
| TanakaTarou | 11:debd1264bae8 | 767 | #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown |
| TanakaTarou | 11:debd1264bae8 | 768 | #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor |
| TanakaTarou | 11:debd1264bae8 | 769 | #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg |
| TanakaTarou | 11:debd1264bae8 | 770 | #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown |
| TanakaTarou | 11:debd1264bae8 | 771 | #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor |
| TanakaTarou | 11:debd1264bae8 | 772 | #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler |
| TanakaTarou | 11:debd1264bae8 | 773 | #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD |
| TanakaTarou | 11:debd1264bae8 | 774 | #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler |
| TanakaTarou | 11:debd1264bae8 | 775 | #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback |
| TanakaTarou | 11:debd1264bae8 | 776 | #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive |
| TanakaTarou | 11:debd1264bae8 | 777 | #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive |
| TanakaTarou | 11:debd1264bae8 | 778 | #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC |
| TanakaTarou | 11:debd1264bae8 | 779 | #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC |
| TanakaTarou | 11:debd1264bae8 | 780 | #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM |
| TanakaTarou | 11:debd1264bae8 | 781 | |
| TanakaTarou | 11:debd1264bae8 | 782 | #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL |
| TanakaTarou | 11:debd1264bae8 | 783 | #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING |
| TanakaTarou | 11:debd1264bae8 | 784 | #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING |
| TanakaTarou | 11:debd1264bae8 | 785 | #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING |
| TanakaTarou | 11:debd1264bae8 | 786 | #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING |
| TanakaTarou | 11:debd1264bae8 | 787 | #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING |
| TanakaTarou | 11:debd1264bae8 | 788 | #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING |
| TanakaTarou | 11:debd1264bae8 | 789 | |
| TanakaTarou | 11:debd1264bae8 | 790 | #define CR_OFFSET_BB PWR_CR_OFFSET_BB |
| TanakaTarou | 11:debd1264bae8 | 791 | #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB |
| TanakaTarou | 11:debd1264bae8 | 792 | |
| TanakaTarou | 11:debd1264bae8 | 793 | #define DBP_BitNumber DBP_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 794 | #define PVDE_BitNumber PVDE_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 795 | #define PMODE_BitNumber PMODE_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 796 | #define EWUP_BitNumber EWUP_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 797 | #define FPDS_BitNumber FPDS_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 798 | #define ODEN_BitNumber ODEN_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 799 | #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 800 | #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 801 | #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 802 | #define BRE_BitNumber BRE_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 803 | |
| TanakaTarou | 11:debd1264bae8 | 804 | #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL |
| TanakaTarou | 11:debd1264bae8 | 805 | |
| TanakaTarou | 11:debd1264bae8 | 806 | #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT |
| TanakaTarou | 11:debd1264bae8 | 807 | #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback |
| TanakaTarou | 11:debd1264bae8 | 808 | #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback |
| TanakaTarou | 11:debd1264bae8 | 809 | |
| TanakaTarou | 11:debd1264bae8 | 810 | #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo |
| TanakaTarou | 11:debd1264bae8 | 811 | |
| TanakaTarou | 11:debd1264bae8 | 812 | #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt |
| TanakaTarou | 11:debd1264bae8 | 813 | #define HAL_TIM_DMAError TIM_DMAError |
| TanakaTarou | 11:debd1264bae8 | 814 | #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt |
| TanakaTarou | 11:debd1264bae8 | 815 | #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt |
| TanakaTarou | 11:debd1264bae8 | 816 | |
| TanakaTarou | 11:debd1264bae8 | 817 | #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback |
| TanakaTarou | 11:debd1264bae8 | 818 | |
| TanakaTarou | 11:debd1264bae8 | 819 | #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback |
| TanakaTarou | 11:debd1264bae8 | 820 | #define HAL_LTDC_Relaod HAL_LTDC_Reload |
| TanakaTarou | 11:debd1264bae8 | 821 | #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig |
| TanakaTarou | 11:debd1264bae8 | 822 | #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig |
| TanakaTarou | 11:debd1264bae8 | 823 | |
| TanakaTarou | 11:debd1264bae8 | 824 | #define AES_IT_CC CRYP_IT_CC |
| TanakaTarou | 11:debd1264bae8 | 825 | #define AES_IT_ERR CRYP_IT_ERR |
| TanakaTarou | 11:debd1264bae8 | 826 | #define AES_FLAG_CCF CRYP_FLAG_CCF |
| TanakaTarou | 11:debd1264bae8 | 827 | |
| TanakaTarou | 11:debd1264bae8 | 828 | #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE |
| TanakaTarou | 11:debd1264bae8 | 829 | #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH |
| TanakaTarou | 11:debd1264bae8 | 830 | #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH |
| TanakaTarou | 11:debd1264bae8 | 831 | #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM |
| TanakaTarou | 11:debd1264bae8 | 832 | #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC |
| TanakaTarou | 11:debd1264bae8 | 833 | #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM |
| TanakaTarou | 11:debd1264bae8 | 834 | #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC |
| TanakaTarou | 11:debd1264bae8 | 835 | #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI |
| TanakaTarou | 11:debd1264bae8 | 836 | #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK |
| TanakaTarou | 11:debd1264bae8 | 837 | #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG |
| TanakaTarou | 11:debd1264bae8 | 838 | #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG |
| TanakaTarou | 11:debd1264bae8 | 839 | #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 840 | #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 841 | |
| TanakaTarou | 11:debd1264bae8 | 842 | #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY |
| TanakaTarou | 11:debd1264bae8 | 843 | #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 |
| TanakaTarou | 11:debd1264bae8 | 844 | #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS |
| TanakaTarou | 11:debd1264bae8 | 845 | #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 846 | #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 847 | |
| TanakaTarou | 11:debd1264bae8 | 848 | #define __ADC_ENABLE __HAL_ADC_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 849 | #define __ADC_DISABLE __HAL_ADC_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 850 | #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS |
| TanakaTarou | 11:debd1264bae8 | 851 | #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS |
| TanakaTarou | 11:debd1264bae8 | 852 | #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 853 | #define __ADC_IS_ENABLED ADC_IS_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 854 | #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR |
| TanakaTarou | 11:debd1264bae8 | 855 | #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED |
| TanakaTarou | 11:debd1264bae8 | 856 | #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED |
| TanakaTarou | 11:debd1264bae8 | 857 | #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR |
| TanakaTarou | 11:debd1264bae8 | 858 | #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED |
| TanakaTarou | 11:debd1264bae8 | 859 | #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING |
| TanakaTarou | 11:debd1264bae8 | 860 | #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE |
| TanakaTarou | 11:debd1264bae8 | 861 | |
| TanakaTarou | 11:debd1264bae8 | 862 | #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION |
| TanakaTarou | 11:debd1264bae8 | 863 | #define __HAL_ADC_JSQR_RK ADC_JSQR_RK |
| TanakaTarou | 11:debd1264bae8 | 864 | #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT |
| TanakaTarou | 11:debd1264bae8 | 865 | #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR |
| TanakaTarou | 11:debd1264bae8 | 866 | #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION |
| TanakaTarou | 11:debd1264bae8 | 867 | #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE |
| TanakaTarou | 11:debd1264bae8 | 868 | #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS |
| TanakaTarou | 11:debd1264bae8 | 869 | #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS |
| TanakaTarou | 11:debd1264bae8 | 870 | #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM |
| TanakaTarou | 11:debd1264bae8 | 871 | #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT |
| TanakaTarou | 11:debd1264bae8 | 872 | #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS |
| TanakaTarou | 11:debd1264bae8 | 873 | #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN |
| TanakaTarou | 11:debd1264bae8 | 874 | #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ |
| TanakaTarou | 11:debd1264bae8 | 875 | #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET |
| TanakaTarou | 11:debd1264bae8 | 876 | #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET |
| TanakaTarou | 11:debd1264bae8 | 877 | #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL |
| TanakaTarou | 11:debd1264bae8 | 878 | #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL |
| TanakaTarou | 11:debd1264bae8 | 879 | #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET |
| TanakaTarou | 11:debd1264bae8 | 880 | #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET |
| TanakaTarou | 11:debd1264bae8 | 881 | #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD |
| TanakaTarou | 11:debd1264bae8 | 882 | |
| TanakaTarou | 11:debd1264bae8 | 883 | #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION |
| TanakaTarou | 11:debd1264bae8 | 884 | #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION |
| TanakaTarou | 11:debd1264bae8 | 885 | #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION |
| TanakaTarou | 11:debd1264bae8 | 886 | #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER |
| TanakaTarou | 11:debd1264bae8 | 887 | #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI |
| TanakaTarou | 11:debd1264bae8 | 888 | #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 889 | #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 890 | #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER |
| TanakaTarou | 11:debd1264bae8 | 891 | #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER |
| TanakaTarou | 11:debd1264bae8 | 892 | #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE |
| TanakaTarou | 11:debd1264bae8 | 893 | |
| TanakaTarou | 11:debd1264bae8 | 894 | #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT |
| TanakaTarou | 11:debd1264bae8 | 895 | #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT |
| TanakaTarou | 11:debd1264bae8 | 896 | #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL |
| TanakaTarou | 11:debd1264bae8 | 897 | #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM |
| TanakaTarou | 11:debd1264bae8 | 898 | #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET |
| TanakaTarou | 11:debd1264bae8 | 899 | #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE |
| TanakaTarou | 11:debd1264bae8 | 900 | #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE |
| TanakaTarou | 11:debd1264bae8 | 901 | #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER |
| TanakaTarou | 11:debd1264bae8 | 902 | |
| TanakaTarou | 11:debd1264bae8 | 903 | #define __HAL_ADC_SQR1 ADC_SQR1 |
| TanakaTarou | 11:debd1264bae8 | 904 | #define __HAL_ADC_SMPR1 ADC_SMPR1 |
| TanakaTarou | 11:debd1264bae8 | 905 | #define __HAL_ADC_SMPR2 ADC_SMPR2 |
| TanakaTarou | 11:debd1264bae8 | 906 | #define __HAL_ADC_SQR3_RK ADC_SQR3_RK |
| TanakaTarou | 11:debd1264bae8 | 907 | #define __HAL_ADC_SQR2_RK ADC_SQR2_RK |
| TanakaTarou | 11:debd1264bae8 | 908 | #define __HAL_ADC_SQR1_RK ADC_SQR1_RK |
| TanakaTarou | 11:debd1264bae8 | 909 | #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS |
| TanakaTarou | 11:debd1264bae8 | 910 | #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS |
| TanakaTarou | 11:debd1264bae8 | 911 | #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV |
| TanakaTarou | 11:debd1264bae8 | 912 | #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection |
| TanakaTarou | 11:debd1264bae8 | 913 | #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq |
| TanakaTarou | 11:debd1264bae8 | 914 | #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION |
| TanakaTarou | 11:debd1264bae8 | 915 | #define __HAL_ADC_JSQR ADC_JSQR |
| TanakaTarou | 11:debd1264bae8 | 916 | |
| TanakaTarou | 11:debd1264bae8 | 917 | #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL |
| TanakaTarou | 11:debd1264bae8 | 918 | #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS |
| TanakaTarou | 11:debd1264bae8 | 919 | #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF |
| TanakaTarou | 11:debd1264bae8 | 920 | #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT |
| TanakaTarou | 11:debd1264bae8 | 921 | #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS |
| TanakaTarou | 11:debd1264bae8 | 922 | #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN |
| TanakaTarou | 11:debd1264bae8 | 923 | #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR |
| TanakaTarou | 11:debd1264bae8 | 924 | #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ |
| TanakaTarou | 11:debd1264bae8 | 925 | |
| TanakaTarou | 11:debd1264bae8 | 926 | #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT |
| TanakaTarou | 11:debd1264bae8 | 927 | #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT |
| TanakaTarou | 11:debd1264bae8 | 928 | #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT |
| TanakaTarou | 11:debd1264bae8 | 929 | #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE |
| TanakaTarou | 11:debd1264bae8 | 930 | |
| TanakaTarou | 11:debd1264bae8 | 931 | #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 |
| TanakaTarou | 11:debd1264bae8 | 932 | #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 |
| TanakaTarou | 11:debd1264bae8 | 933 | #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 |
| TanakaTarou | 11:debd1264bae8 | 934 | #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 |
| TanakaTarou | 11:debd1264bae8 | 935 | #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 |
| TanakaTarou | 11:debd1264bae8 | 936 | #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 |
| TanakaTarou | 11:debd1264bae8 | 937 | #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 |
| TanakaTarou | 11:debd1264bae8 | 938 | #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 |
| TanakaTarou | 11:debd1264bae8 | 939 | #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 |
| TanakaTarou | 11:debd1264bae8 | 940 | #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 |
| TanakaTarou | 11:debd1264bae8 | 941 | #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 |
| TanakaTarou | 11:debd1264bae8 | 942 | #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 |
| TanakaTarou | 11:debd1264bae8 | 943 | #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 |
| TanakaTarou | 11:debd1264bae8 | 944 | #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 |
| TanakaTarou | 11:debd1264bae8 | 945 | #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 |
| TanakaTarou | 11:debd1264bae8 | 946 | #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 |
| TanakaTarou | 11:debd1264bae8 | 947 | |
| TanakaTarou | 11:debd1264bae8 | 948 | #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 |
| TanakaTarou | 11:debd1264bae8 | 949 | #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 |
| TanakaTarou | 11:debd1264bae8 | 950 | #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 |
| TanakaTarou | 11:debd1264bae8 | 951 | #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 |
| TanakaTarou | 11:debd1264bae8 | 952 | #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 |
| TanakaTarou | 11:debd1264bae8 | 953 | #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 |
| TanakaTarou | 11:debd1264bae8 | 954 | #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 |
| TanakaTarou | 11:debd1264bae8 | 955 | #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 |
| TanakaTarou | 11:debd1264bae8 | 956 | #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 |
| TanakaTarou | 11:debd1264bae8 | 957 | #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 |
| TanakaTarou | 11:debd1264bae8 | 958 | #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 |
| TanakaTarou | 11:debd1264bae8 | 959 | #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 |
| TanakaTarou | 11:debd1264bae8 | 960 | #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 |
| TanakaTarou | 11:debd1264bae8 | 961 | #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 |
| TanakaTarou | 11:debd1264bae8 | 962 | |
| TanakaTarou | 11:debd1264bae8 | 963 | |
| TanakaTarou | 11:debd1264bae8 | 964 | #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 |
| TanakaTarou | 11:debd1264bae8 | 965 | #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 |
| TanakaTarou | 11:debd1264bae8 | 966 | #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 |
| TanakaTarou | 11:debd1264bae8 | 967 | #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 |
| TanakaTarou | 11:debd1264bae8 | 968 | #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 |
| TanakaTarou | 11:debd1264bae8 | 969 | #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 |
| TanakaTarou | 11:debd1264bae8 | 970 | #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC |
| TanakaTarou | 11:debd1264bae8 | 971 | #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC |
| TanakaTarou | 11:debd1264bae8 | 972 | #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG |
| TanakaTarou | 11:debd1264bae8 | 973 | #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG |
| TanakaTarou | 11:debd1264bae8 | 974 | #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG |
| TanakaTarou | 11:debd1264bae8 | 975 | #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG |
| TanakaTarou | 11:debd1264bae8 | 976 | #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT |
| TanakaTarou | 11:debd1264bae8 | 977 | #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT |
| TanakaTarou | 11:debd1264bae8 | 978 | #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT |
| TanakaTarou | 11:debd1264bae8 | 979 | #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT |
| TanakaTarou | 11:debd1264bae8 | 980 | #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT |
| TanakaTarou | 11:debd1264bae8 | 981 | #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT |
| TanakaTarou | 11:debd1264bae8 | 982 | #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 |
| TanakaTarou | 11:debd1264bae8 | 983 | #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 |
| TanakaTarou | 11:debd1264bae8 | 984 | #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 |
| TanakaTarou | 11:debd1264bae8 | 985 | #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 |
| TanakaTarou | 11:debd1264bae8 | 986 | #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 |
| TanakaTarou | 11:debd1264bae8 | 987 | #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 |
| TanakaTarou | 11:debd1264bae8 | 988 | |
| TanakaTarou | 11:debd1264bae8 | 989 | #if defined(STM32F3) |
| TanakaTarou | 11:debd1264bae8 | 990 | #define COMP_START __HAL_COMP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 991 | #define COMP_STOP __HAL_COMP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 992 | #define COMP_LOCK __HAL_COMP_LOCK |
| TanakaTarou | 11:debd1264bae8 | 993 | |
| TanakaTarou | 11:debd1264bae8 | 994 | #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
| TanakaTarou | 11:debd1264bae8 | 995 | #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 996 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 997 | __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 998 | #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 999 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1000 | __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1001 | #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1002 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1003 | __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1004 | #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1005 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1006 | __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1007 | #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1008 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1009 | __HAL_COMP_COMP6_EXTI_ENABLE_IT()) |
| TanakaTarou | 11:debd1264bae8 | 1010 | #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1011 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1012 | __HAL_COMP_COMP6_EXTI_DISABLE_IT()) |
| TanakaTarou | 11:debd1264bae8 | 1013 | #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1014 | ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1015 | __HAL_COMP_COMP6_EXTI_GET_FLAG()) |
| TanakaTarou | 11:debd1264bae8 | 1016 | #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1017 | ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1018 | __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) |
| TanakaTarou | 11:debd1264bae8 | 1019 | # endif |
| TanakaTarou | 11:debd1264bae8 | 1020 | # if defined(STM32F302xE) || defined(STM32F302xC) |
| TanakaTarou | 11:debd1264bae8 | 1021 | #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1022 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1023 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1024 | __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1025 | #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1026 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1027 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1028 | __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1029 | #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1030 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1031 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1032 | __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1033 | #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1034 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1035 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1036 | __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1037 | #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1038 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1039 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1040 | __HAL_COMP_COMP6_EXTI_ENABLE_IT()) |
| TanakaTarou | 11:debd1264bae8 | 1041 | #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1042 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1043 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1044 | __HAL_COMP_COMP6_EXTI_DISABLE_IT()) |
| TanakaTarou | 11:debd1264bae8 | 1045 | #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1046 | ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1047 | ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1048 | __HAL_COMP_COMP6_EXTI_GET_FLAG()) |
| TanakaTarou | 11:debd1264bae8 | 1049 | #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1050 | ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1051 | ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1052 | __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) |
| TanakaTarou | 11:debd1264bae8 | 1053 | # endif |
| TanakaTarou | 11:debd1264bae8 | 1054 | # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) |
| TanakaTarou | 11:debd1264bae8 | 1055 | #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1056 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1057 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1058 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1059 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1060 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1061 | __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1062 | #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1063 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1064 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1065 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1066 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1067 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1068 | __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1069 | #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1070 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1071 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1072 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1073 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1074 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1075 | __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1076 | #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1077 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1078 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1079 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1080 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1081 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1082 | __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1083 | #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1084 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1085 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1086 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1087 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1088 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1089 | __HAL_COMP_COMP7_EXTI_ENABLE_IT()) |
| TanakaTarou | 11:debd1264bae8 | 1090 | #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1091 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1092 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1093 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1094 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1095 | ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1096 | __HAL_COMP_COMP7_EXTI_DISABLE_IT()) |
| TanakaTarou | 11:debd1264bae8 | 1097 | #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1098 | ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1099 | ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1100 | ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1101 | ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1102 | ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1103 | __HAL_COMP_COMP7_EXTI_GET_FLAG()) |
| TanakaTarou | 11:debd1264bae8 | 1104 | #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1105 | ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1106 | ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1107 | ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1108 | ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1109 | ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1110 | __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) |
| TanakaTarou | 11:debd1264bae8 | 1111 | # endif |
| TanakaTarou | 11:debd1264bae8 | 1112 | # if defined(STM32F373xC) ||defined(STM32F378xx) |
| TanakaTarou | 11:debd1264bae8 | 1113 | #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1114 | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1115 | #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1116 | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1117 | #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1118 | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1119 | #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1120 | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1121 | #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1122 | __HAL_COMP_COMP2_EXTI_ENABLE_IT()) |
| TanakaTarou | 11:debd1264bae8 | 1123 | #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1124 | __HAL_COMP_COMP2_EXTI_DISABLE_IT()) |
| TanakaTarou | 11:debd1264bae8 | 1125 | #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1126 | __HAL_COMP_COMP2_EXTI_GET_FLAG()) |
| TanakaTarou | 11:debd1264bae8 | 1127 | #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1128 | __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) |
| TanakaTarou | 11:debd1264bae8 | 1129 | # endif |
| TanakaTarou | 11:debd1264bae8 | 1130 | #else |
| TanakaTarou | 11:debd1264bae8 | 1131 | #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1132 | __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1133 | #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1134 | __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1135 | #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1136 | __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1137 | #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ |
| TanakaTarou | 11:debd1264bae8 | 1138 | __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) |
| TanakaTarou | 11:debd1264bae8 | 1139 | #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1140 | __HAL_COMP_COMP2_EXTI_ENABLE_IT()) |
| TanakaTarou | 11:debd1264bae8 | 1141 | #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 1142 | __HAL_COMP_COMP2_EXTI_DISABLE_IT()) |
| TanakaTarou | 11:debd1264bae8 | 1143 | #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1144 | __HAL_COMP_COMP2_EXTI_GET_FLAG()) |
| TanakaTarou | 11:debd1264bae8 | 1145 | #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 1146 | __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) |
| TanakaTarou | 11:debd1264bae8 | 1147 | #endif |
| TanakaTarou | 11:debd1264bae8 | 1148 | |
| TanakaTarou | 11:debd1264bae8 | 1149 | #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE |
| TanakaTarou | 11:debd1264bae8 | 1150 | |
| TanakaTarou | 11:debd1264bae8 | 1151 | #if defined(STM32L0) || defined(STM32L4) |
| TanakaTarou | 11:debd1264bae8 | 1152 | |
| TanakaTarou | 11:debd1264bae8 | 1153 | #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) |
| TanakaTarou | 11:debd1264bae8 | 1154 | #endif |
| TanakaTarou | 11:debd1264bae8 | 1155 | |
| TanakaTarou | 11:debd1264bae8 | 1156 | #if defined(STM32L0) || defined(STM32L4) |
| TanakaTarou | 11:debd1264bae8 | 1157 | |
| TanakaTarou | 11:debd1264bae8 | 1158 | #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ |
| TanakaTarou | 11:debd1264bae8 | 1159 | #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ |
| TanakaTarou | 11:debd1264bae8 | 1160 | |
| TanakaTarou | 11:debd1264bae8 | 1161 | #endif |
| TanakaTarou | 11:debd1264bae8 | 1162 | |
| TanakaTarou | 11:debd1264bae8 | 1163 | #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ |
| TanakaTarou | 11:debd1264bae8 | 1164 | ((WAVE) == DAC_WAVE_NOISE)|| \ |
| TanakaTarou | 11:debd1264bae8 | 1165 | ((WAVE) == DAC_WAVE_TRIANGLE)) |
| TanakaTarou | 11:debd1264bae8 | 1166 | |
| TanakaTarou | 11:debd1264bae8 | 1167 | |
| TanakaTarou | 11:debd1264bae8 | 1168 | #define IS_WRPAREA IS_OB_WRPAREA |
| TanakaTarou | 11:debd1264bae8 | 1169 | #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM |
| TanakaTarou | 11:debd1264bae8 | 1170 | #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM |
| TanakaTarou | 11:debd1264bae8 | 1171 | #define IS_TYPEERASE IS_FLASH_TYPEERASE |
| TanakaTarou | 11:debd1264bae8 | 1172 | #define IS_NBSECTORS IS_FLASH_NBSECTORS |
| TanakaTarou | 11:debd1264bae8 | 1173 | #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE |
| TanakaTarou | 11:debd1264bae8 | 1174 | |
| TanakaTarou | 11:debd1264bae8 | 1175 | |
| TanakaTarou | 11:debd1264bae8 | 1176 | #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 |
| TanakaTarou | 11:debd1264bae8 | 1177 | #define __HAL_I2C_GENERATE_START I2C_GENERATE_START |
| TanakaTarou | 11:debd1264bae8 | 1178 | #if defined(STM32F1) |
| TanakaTarou | 11:debd1264bae8 | 1179 | #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE |
| TanakaTarou | 11:debd1264bae8 | 1180 | #else |
| TanakaTarou | 11:debd1264bae8 | 1181 | #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE |
| TanakaTarou | 11:debd1264bae8 | 1182 | #endif /* STM32F1 */ |
| TanakaTarou | 11:debd1264bae8 | 1183 | #define __HAL_I2C_RISE_TIME I2C_RISE_TIME |
| TanakaTarou | 11:debd1264bae8 | 1184 | #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD |
| TanakaTarou | 11:debd1264bae8 | 1185 | #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST |
| TanakaTarou | 11:debd1264bae8 | 1186 | #define __HAL_I2C_SPEED I2C_SPEED |
| TanakaTarou | 11:debd1264bae8 | 1187 | #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE |
| TanakaTarou | 11:debd1264bae8 | 1188 | #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ |
| TanakaTarou | 11:debd1264bae8 | 1189 | #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS |
| TanakaTarou | 11:debd1264bae8 | 1190 | #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE |
| TanakaTarou | 11:debd1264bae8 | 1191 | #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ |
| TanakaTarou | 11:debd1264bae8 | 1192 | #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB |
| TanakaTarou | 11:debd1264bae8 | 1193 | #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB |
| TanakaTarou | 11:debd1264bae8 | 1194 | #define __HAL_I2C_FREQRANGE I2C_FREQRANGE |
| TanakaTarou | 11:debd1264bae8 | 1195 | |
| TanakaTarou | 11:debd1264bae8 | 1196 | #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE |
| TanakaTarou | 11:debd1264bae8 | 1197 | #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT |
| TanakaTarou | 11:debd1264bae8 | 1198 | |
| TanakaTarou | 11:debd1264bae8 | 1199 | #define __IRDA_DISABLE __HAL_IRDA_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1200 | #define __IRDA_ENABLE __HAL_IRDA_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1201 | |
| TanakaTarou | 11:debd1264bae8 | 1202 | #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE |
| TanakaTarou | 11:debd1264bae8 | 1203 | #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION |
| TanakaTarou | 11:debd1264bae8 | 1204 | #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE |
| TanakaTarou | 11:debd1264bae8 | 1205 | #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION |
| TanakaTarou | 11:debd1264bae8 | 1206 | |
| TanakaTarou | 11:debd1264bae8 | 1207 | #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE |
| TanakaTarou | 11:debd1264bae8 | 1208 | |
| TanakaTarou | 11:debd1264bae8 | 1209 | #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS |
| TanakaTarou | 11:debd1264bae8 | 1210 | #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS |
| TanakaTarou | 11:debd1264bae8 | 1211 | |
| TanakaTarou | 11:debd1264bae8 | 1212 | #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 1213 | #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 1214 | #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE |
| TanakaTarou | 11:debd1264bae8 | 1215 | |
| TanakaTarou | 11:debd1264bae8 | 1216 | #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD |
| TanakaTarou | 11:debd1264bae8 | 1217 | #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX |
| TanakaTarou | 11:debd1264bae8 | 1218 | #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX |
| TanakaTarou | 11:debd1264bae8 | 1219 | #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX |
| TanakaTarou | 11:debd1264bae8 | 1220 | #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX |
| TanakaTarou | 11:debd1264bae8 | 1221 | #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L |
| TanakaTarou | 11:debd1264bae8 | 1222 | #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H |
| TanakaTarou | 11:debd1264bae8 | 1223 | #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM |
| TanakaTarou | 11:debd1264bae8 | 1224 | #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES |
| TanakaTarou | 11:debd1264bae8 | 1225 | #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX |
| TanakaTarou | 11:debd1264bae8 | 1226 | #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT |
| TanakaTarou | 11:debd1264bae8 | 1227 | #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION |
| TanakaTarou | 11:debd1264bae8 | 1228 | #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET |
| TanakaTarou | 11:debd1264bae8 | 1229 | |
| TanakaTarou | 11:debd1264bae8 | 1230 | #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT |
| TanakaTarou | 11:debd1264bae8 | 1231 | #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT |
| TanakaTarou | 11:debd1264bae8 | 1232 | #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 1233 | #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 1234 | #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 1235 | #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 1236 | #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1237 | #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1238 | #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1239 | #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1240 | #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1241 | #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1242 | #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine |
| TanakaTarou | 11:debd1264bae8 | 1243 | #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine |
| TanakaTarou | 11:debd1264bae8 | 1244 | #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig |
| TanakaTarou | 11:debd1264bae8 | 1245 | #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig |
| TanakaTarou | 11:debd1264bae8 | 1246 | #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) |
| TanakaTarou | 11:debd1264bae8 | 1247 | #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT |
| TanakaTarou | 11:debd1264bae8 | 1248 | #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT |
| TanakaTarou | 11:debd1264bae8 | 1249 | #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 1250 | #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 1251 | #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 1252 | #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 1253 | #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 1254 | #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 1255 | #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) |
| TanakaTarou | 11:debd1264bae8 | 1256 | #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) |
| TanakaTarou | 11:debd1264bae8 | 1257 | #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention |
| TanakaTarou | 11:debd1264bae8 | 1258 | #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention |
| TanakaTarou | 11:debd1264bae8 | 1259 | #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 |
| TanakaTarou | 11:debd1264bae8 | 1260 | #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 |
| TanakaTarou | 11:debd1264bae8 | 1261 | #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 1262 | #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 1263 | #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB |
| TanakaTarou | 11:debd1264bae8 | 1264 | #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB |
| TanakaTarou | 11:debd1264bae8 | 1265 | |
| TanakaTarou | 11:debd1264bae8 | 1266 | #if defined (STM32F4) |
| TanakaTarou | 11:debd1264bae8 | 1267 | #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() |
| TanakaTarou | 11:debd1264bae8 | 1268 | #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() |
| TanakaTarou | 11:debd1264bae8 | 1269 | #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() |
| TanakaTarou | 11:debd1264bae8 | 1270 | #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() |
| TanakaTarou | 11:debd1264bae8 | 1271 | #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() |
| TanakaTarou | 11:debd1264bae8 | 1272 | #else |
| TanakaTarou | 11:debd1264bae8 | 1273 | #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG |
| TanakaTarou | 11:debd1264bae8 | 1274 | #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 1275 | #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 1276 | #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT |
| TanakaTarou | 11:debd1264bae8 | 1277 | #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG |
| TanakaTarou | 11:debd1264bae8 | 1278 | #endif /* STM32F4 */ |
| TanakaTarou | 11:debd1264bae8 | 1279 | |
| TanakaTarou | 11:debd1264bae8 | 1280 | #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI |
| TanakaTarou | 11:debd1264bae8 | 1281 | #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI |
| TanakaTarou | 11:debd1264bae8 | 1282 | |
| TanakaTarou | 11:debd1264bae8 | 1283 | #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback |
| TanakaTarou | 11:debd1264bae8 | 1284 | #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) |
| TanakaTarou | 11:debd1264bae8 | 1285 | |
| TanakaTarou | 11:debd1264bae8 | 1286 | #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1287 | #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1288 | #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1289 | #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1290 | #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1291 | #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1292 | #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1293 | #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1294 | #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1295 | #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1296 | #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1297 | #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1298 | #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1299 | #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1300 | #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1301 | #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1302 | #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1303 | #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1304 | #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1305 | #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1306 | #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1307 | #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1308 | #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1309 | #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1310 | #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1311 | #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1312 | #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1313 | #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1314 | #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1315 | #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1316 | #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1317 | #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1318 | #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1319 | #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1320 | #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1321 | #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1322 | #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1323 | #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1324 | #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1325 | #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1326 | #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1327 | #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1328 | #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1329 | #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1330 | #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1331 | #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1332 | #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1333 | #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1334 | #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1335 | #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1336 | #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1337 | #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1338 | #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1339 | #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1340 | #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1341 | #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1342 | #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1343 | #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1344 | #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1345 | #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1346 | #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1347 | #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1348 | #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1349 | #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1350 | #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1351 | #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1352 | #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1353 | #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1354 | #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1355 | #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1356 | #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1357 | #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1358 | #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1359 | #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1360 | #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1361 | #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1362 | #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1363 | #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1364 | #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1365 | #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1366 | #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1367 | #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1368 | #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1369 | #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1370 | #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1371 | #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1372 | #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1373 | #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1374 | #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1375 | #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1376 | #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1377 | #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1378 | #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1379 | #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1380 | #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1381 | #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1382 | #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1383 | #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1384 | #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1385 | #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1386 | #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1387 | #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1388 | #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1389 | #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1390 | #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1391 | #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1392 | #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1393 | #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1394 | #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1395 | #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1396 | #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1397 | #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1398 | #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1399 | #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1400 | #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1401 | #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1402 | #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1403 | #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1404 | #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1405 | #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1406 | #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1407 | #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1408 | #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1409 | #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1410 | #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1411 | #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1412 | #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1413 | #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1414 | #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1415 | #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1416 | #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1417 | #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1418 | #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1419 | #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1420 | #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1421 | #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1422 | #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1423 | #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1424 | #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1425 | #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1426 | #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1427 | #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1428 | #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1429 | #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1430 | #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1431 | #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1432 | #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1433 | #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1434 | #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1435 | #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1436 | #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1437 | #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1438 | #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1439 | #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1440 | #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1441 | #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1442 | #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1443 | #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1444 | #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1445 | #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1446 | #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1447 | #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1448 | #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1449 | #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1450 | #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1451 | #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1452 | #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1453 | #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1454 | #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1455 | #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1456 | #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1457 | #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1458 | #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1459 | #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1460 | #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1461 | #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1462 | #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1463 | #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1464 | #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1465 | #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1466 | #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1467 | #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1468 | #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1469 | #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1470 | #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1471 | #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1472 | #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1473 | #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1474 | #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1475 | #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1476 | #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1477 | #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1478 | #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1479 | #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1480 | #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1481 | #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1482 | #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1483 | #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1484 | #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1485 | #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1486 | #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1487 | #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1488 | #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1489 | #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1490 | #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1491 | #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1492 | #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1493 | #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1494 | #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1495 | #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1496 | #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1497 | #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1498 | #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1499 | #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1500 | #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1501 | #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1502 | #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1503 | #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1504 | #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1505 | #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1506 | #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1507 | #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1508 | #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1509 | #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1510 | #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1511 | #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1512 | #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1513 | #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1514 | #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1515 | #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1516 | #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1517 | #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1518 | #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1519 | #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1520 | #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1521 | #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1522 | #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1523 | #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1524 | #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1525 | #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1526 | #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1527 | #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1528 | #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1529 | #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1530 | #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1531 | #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1532 | #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1533 | #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1534 | #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1535 | #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1536 | #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1537 | #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1538 | #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1539 | #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1540 | #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1541 | #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1542 | #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1543 | #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1544 | #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1545 | #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1546 | #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1547 | #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1548 | #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1549 | #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1550 | #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1551 | #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1552 | #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1553 | #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1554 | #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1555 | #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1556 | #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1557 | #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1558 | #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1559 | #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1560 | #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1561 | #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1562 | #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1563 | #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1564 | #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1565 | #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1566 | #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1567 | #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1568 | #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1569 | #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1570 | #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1571 | #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1572 | #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1573 | #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1574 | #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1575 | #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1576 | #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1577 | #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1578 | #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1579 | #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1580 | #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1581 | #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1582 | #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1583 | #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1584 | #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1585 | #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1586 | #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1587 | #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1588 | #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1589 | #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1590 | #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1591 | #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1592 | #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1593 | #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1594 | #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1595 | #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1596 | #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1597 | #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1598 | #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1599 | #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1600 | #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1601 | #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1602 | #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1603 | #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1604 | #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1605 | #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1606 | #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1607 | #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1608 | #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1609 | #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1610 | #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1611 | #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1612 | #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1613 | #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1614 | #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1615 | #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1616 | #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1617 | #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1618 | #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1619 | #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1620 | #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1621 | #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1622 | #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1623 | #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1624 | #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1625 | #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1626 | #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1627 | #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1628 | #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1629 | #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1630 | #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1631 | #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1632 | #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1633 | #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1634 | #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1635 | #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1636 | #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1637 | #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1638 | #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1639 | #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1640 | #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1641 | #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1642 | #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1643 | #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1644 | #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1645 | #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1646 | #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1647 | #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1648 | #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1649 | #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1650 | #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1651 | #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1652 | #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1653 | #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1654 | #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1655 | #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1656 | #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1657 | #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1658 | #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1659 | #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1660 | #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1661 | #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1662 | #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1663 | #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1664 | #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1665 | #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1666 | #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1667 | #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1668 | #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1669 | #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1670 | #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1671 | #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1672 | #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1673 | #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1674 | #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1675 | #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1676 | #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1677 | #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1678 | #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1679 | #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1680 | #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1681 | #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1682 | #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1683 | #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1684 | #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1685 | #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1686 | #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1687 | #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1688 | #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1689 | #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1690 | #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1691 | #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1692 | #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1693 | #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1694 | #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1695 | #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1696 | #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1697 | #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1698 | #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1699 | #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1700 | #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1701 | #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1702 | #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1703 | #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1704 | #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1705 | #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1706 | #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1707 | #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1708 | #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1709 | #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1710 | #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1711 | #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1712 | #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1713 | #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1714 | #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1715 | #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1716 | #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1717 | #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1718 | #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1719 | #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1720 | #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1721 | #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1722 | #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1723 | #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1724 | #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1725 | #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1726 | #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1727 | #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1728 | #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1729 | #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1730 | #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1731 | #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1732 | #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1733 | #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1734 | #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1735 | #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1736 | #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1737 | #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1738 | #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1739 | #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1740 | #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1741 | #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1742 | #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1743 | #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1744 | #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1745 | #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1746 | #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1747 | #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1748 | #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1749 | #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1750 | #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1751 | #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1752 | #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1753 | #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1754 | #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1755 | #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1756 | #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1757 | #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1758 | #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1759 | #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1760 | #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1761 | #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1762 | #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1763 | #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1764 | #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1765 | #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1766 | #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1767 | #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1768 | #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1769 | #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1770 | #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1771 | #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1772 | #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1773 | #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1774 | #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1775 | #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1776 | #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1777 | #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1778 | #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1779 | #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1780 | #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1781 | #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1782 | #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1783 | #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1784 | #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE |
| TanakaTarou | 11:debd1264bae8 | 1785 | #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE |
| TanakaTarou | 11:debd1264bae8 | 1786 | |
| TanakaTarou | 11:debd1264bae8 | 1787 | #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1788 | #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1789 | #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1790 | #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1791 | #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1792 | #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1793 | #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1794 | #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1795 | #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1796 | #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1797 | #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1798 | #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1799 | #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1800 | #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1801 | #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1802 | #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1803 | #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1804 | #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1805 | #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1806 | #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1807 | #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1808 | #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1809 | #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1810 | #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1811 | #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1812 | #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1813 | #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1814 | #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1815 | #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1816 | #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1817 | #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1818 | #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1819 | #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1820 | #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1821 | #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1822 | #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1823 | #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1824 | #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1825 | #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1826 | #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1827 | #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1828 | #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1829 | #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1830 | #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1831 | #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1832 | #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1833 | #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1834 | #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1835 | #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1836 | #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1837 | #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1838 | #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1839 | #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1840 | #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1841 | #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1842 | #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1843 | #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1844 | #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1845 | #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1846 | #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1847 | #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1848 | #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1849 | #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1850 | #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1851 | #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1852 | #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1853 | #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1854 | #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1855 | #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1856 | #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1857 | #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1858 | #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1859 | #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1860 | #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1861 | #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1862 | #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1863 | #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1864 | #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1865 | #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1866 | #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1867 | #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1868 | #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1869 | #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1870 | #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1871 | #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1872 | #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1873 | #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1874 | #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1875 | #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1876 | #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1877 | #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1878 | #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1879 | #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1880 | #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1881 | #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1882 | #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1883 | #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1884 | #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1885 | #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1886 | #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1887 | #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1888 | #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1889 | #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1890 | #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1891 | #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1892 | #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1893 | #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1894 | #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1895 | #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1896 | #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1897 | #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1898 | #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1899 | #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1900 | #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1901 | #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1902 | #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1903 | #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 1904 | #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 1905 | #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1906 | #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1907 | #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1908 | #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1909 | #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 1910 | #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 1911 | #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1912 | #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1913 | #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1914 | #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1915 | #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1916 | #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1917 | #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1918 | #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1919 | #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1920 | #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1921 | #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1922 | #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1923 | #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1924 | #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1925 | #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1926 | #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1927 | #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1928 | #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1929 | #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1930 | #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1931 | #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1932 | #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1933 | #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1934 | #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1935 | |
| TanakaTarou | 11:debd1264bae8 | 1936 | /* alias define maintained for legacy */ |
| TanakaTarou | 11:debd1264bae8 | 1937 | #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1938 | #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1939 | |
| TanakaTarou | 11:debd1264bae8 | 1940 | #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1941 | #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1942 | #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1943 | #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1944 | #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1945 | #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1946 | #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1947 | #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1948 | #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1949 | #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1950 | #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1951 | #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1952 | #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1953 | #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1954 | #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1955 | #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1956 | #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1957 | #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1958 | #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 1959 | #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1960 | #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1961 | #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 1962 | |
| TanakaTarou | 11:debd1264bae8 | 1963 | #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1964 | #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1965 | #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1966 | #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1967 | #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1968 | #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1969 | #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1970 | #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1971 | #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1972 | #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1973 | #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1974 | #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1975 | #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1976 | #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1977 | #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1978 | #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1979 | #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1980 | #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1981 | #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1982 | #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1983 | #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1984 | #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 1985 | |
| TanakaTarou | 11:debd1264bae8 | 1986 | #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 1987 | #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 1988 | #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 1989 | #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 1990 | #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 1991 | #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 1992 | #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 1993 | #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 1994 | #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 1995 | #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 1996 | #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 1997 | #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 1998 | #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 1999 | #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2000 | #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2001 | #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2002 | #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2003 | #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2004 | #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2005 | #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2006 | #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2007 | #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2008 | #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2009 | #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2010 | #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2011 | #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2012 | #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2013 | #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2014 | #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2015 | #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2016 | #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2017 | #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2018 | #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2019 | #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2020 | #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2021 | #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2022 | #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2023 | #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2024 | #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2025 | #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2026 | #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2027 | #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2028 | #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2029 | #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2030 | #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2031 | #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2032 | #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2033 | #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2034 | #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2035 | #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2036 | #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2037 | #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2038 | #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2039 | #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2040 | #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2041 | #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2042 | #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2043 | #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2044 | #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2045 | #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2046 | #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2047 | #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2048 | #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2049 | #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2050 | #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2051 | #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2052 | #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2053 | #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2054 | #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2055 | #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2056 | #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2057 | #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2058 | #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2059 | #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2060 | #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2061 | #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2062 | #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2063 | #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2064 | #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2065 | #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2066 | #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2067 | #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2068 | #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2069 | #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2070 | #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2071 | #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2072 | #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2073 | #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2074 | #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2075 | #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2076 | #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2077 | #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2078 | #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2079 | #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2080 | #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2081 | #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2082 | #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2083 | #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2084 | #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2085 | #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2086 | #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2087 | #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2088 | #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2089 | #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2090 | #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2091 | #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2092 | #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2093 | #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2094 | #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2095 | #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2096 | #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2097 | #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2098 | #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2099 | #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2100 | #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2101 | #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2102 | |
| TanakaTarou | 11:debd1264bae8 | 2103 | #if defined(STM32F4) |
| TanakaTarou | 11:debd1264bae8 | 2104 | #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 2105 | #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 2106 | #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2107 | #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 2108 | #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2109 | #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 2110 | #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2111 | #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2112 | #define Sdmmc1ClockSelection SdioClockSelection |
| TanakaTarou | 11:debd1264bae8 | 2113 | #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO |
| TanakaTarou | 11:debd1264bae8 | 2114 | #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 |
| TanakaTarou | 11:debd1264bae8 | 2115 | #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK |
| TanakaTarou | 11:debd1264bae8 | 2116 | #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG |
| TanakaTarou | 11:debd1264bae8 | 2117 | #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE |
| TanakaTarou | 11:debd1264bae8 | 2118 | #endif |
| TanakaTarou | 11:debd1264bae8 | 2119 | |
| TanakaTarou | 11:debd1264bae8 | 2120 | #if defined(STM32F7) || defined(STM32L4) |
| TanakaTarou | 11:debd1264bae8 | 2121 | #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 2122 | #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 2123 | #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2124 | #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 2125 | #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2126 | #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 2127 | #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2128 | #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2129 | #define SdioClockSelection Sdmmc1ClockSelection |
| TanakaTarou | 11:debd1264bae8 | 2130 | #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 |
| TanakaTarou | 11:debd1264bae8 | 2131 | #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG |
| TanakaTarou | 11:debd1264bae8 | 2132 | #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE |
| TanakaTarou | 11:debd1264bae8 | 2133 | #endif |
| TanakaTarou | 11:debd1264bae8 | 2134 | |
| TanakaTarou | 11:debd1264bae8 | 2135 | #if defined(STM32F7) |
| TanakaTarou | 11:debd1264bae8 | 2136 | #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 |
| TanakaTarou | 11:debd1264bae8 | 2137 | #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK |
| TanakaTarou | 11:debd1264bae8 | 2138 | #endif |
| TanakaTarou | 11:debd1264bae8 | 2139 | |
| TanakaTarou | 11:debd1264bae8 | 2140 | #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG |
| TanakaTarou | 11:debd1264bae8 | 2141 | #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG |
| TanakaTarou | 11:debd1264bae8 | 2142 | |
| TanakaTarou | 11:debd1264bae8 | 2143 | #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE |
| TanakaTarou | 11:debd1264bae8 | 2144 | |
| TanakaTarou | 11:debd1264bae8 | 2145 | #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE |
| TanakaTarou | 11:debd1264bae8 | 2146 | #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE |
| TanakaTarou | 11:debd1264bae8 | 2147 | #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK |
| TanakaTarou | 11:debd1264bae8 | 2148 | #define IS_RCC_HCLK_DIV IS_RCC_PCLK |
| TanakaTarou | 11:debd1264bae8 | 2149 | #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK |
| TanakaTarou | 11:debd1264bae8 | 2150 | |
| TanakaTarou | 11:debd1264bae8 | 2151 | #define RCC_IT_HSI14 RCC_IT_HSI14RDY |
| TanakaTarou | 11:debd1264bae8 | 2152 | |
| TanakaTarou | 11:debd1264bae8 | 2153 | #define RCC_IT_CSSLSE RCC_IT_LSECSS |
| TanakaTarou | 11:debd1264bae8 | 2154 | #define RCC_IT_CSSHSE RCC_IT_CSS |
| TanakaTarou | 11:debd1264bae8 | 2155 | |
| TanakaTarou | 11:debd1264bae8 | 2156 | #define RCC_PLLMUL_3 RCC_PLL_MUL3 |
| TanakaTarou | 11:debd1264bae8 | 2157 | #define RCC_PLLMUL_4 RCC_PLL_MUL4 |
| TanakaTarou | 11:debd1264bae8 | 2158 | #define RCC_PLLMUL_6 RCC_PLL_MUL6 |
| TanakaTarou | 11:debd1264bae8 | 2159 | #define RCC_PLLMUL_8 RCC_PLL_MUL8 |
| TanakaTarou | 11:debd1264bae8 | 2160 | #define RCC_PLLMUL_12 RCC_PLL_MUL12 |
| TanakaTarou | 11:debd1264bae8 | 2161 | #define RCC_PLLMUL_16 RCC_PLL_MUL16 |
| TanakaTarou | 11:debd1264bae8 | 2162 | #define RCC_PLLMUL_24 RCC_PLL_MUL24 |
| TanakaTarou | 11:debd1264bae8 | 2163 | #define RCC_PLLMUL_32 RCC_PLL_MUL32 |
| TanakaTarou | 11:debd1264bae8 | 2164 | #define RCC_PLLMUL_48 RCC_PLL_MUL48 |
| TanakaTarou | 11:debd1264bae8 | 2165 | |
| TanakaTarou | 11:debd1264bae8 | 2166 | #define RCC_PLLDIV_2 RCC_PLL_DIV2 |
| TanakaTarou | 11:debd1264bae8 | 2167 | #define RCC_PLLDIV_3 RCC_PLL_DIV3 |
| TanakaTarou | 11:debd1264bae8 | 2168 | #define RCC_PLLDIV_4 RCC_PLL_DIV4 |
| TanakaTarou | 11:debd1264bae8 | 2169 | |
| TanakaTarou | 11:debd1264bae8 | 2170 | #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE |
| TanakaTarou | 11:debd1264bae8 | 2171 | #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG |
| TanakaTarou | 11:debd1264bae8 | 2172 | #define RCC_MCO_NODIV RCC_MCODIV_1 |
| TanakaTarou | 11:debd1264bae8 | 2173 | #define RCC_MCO_DIV1 RCC_MCODIV_1 |
| TanakaTarou | 11:debd1264bae8 | 2174 | #define RCC_MCO_DIV2 RCC_MCODIV_2 |
| TanakaTarou | 11:debd1264bae8 | 2175 | #define RCC_MCO_DIV4 RCC_MCODIV_4 |
| TanakaTarou | 11:debd1264bae8 | 2176 | #define RCC_MCO_DIV8 RCC_MCODIV_8 |
| TanakaTarou | 11:debd1264bae8 | 2177 | #define RCC_MCO_DIV16 RCC_MCODIV_16 |
| TanakaTarou | 11:debd1264bae8 | 2178 | #define RCC_MCO_DIV32 RCC_MCODIV_32 |
| TanakaTarou | 11:debd1264bae8 | 2179 | #define RCC_MCO_DIV64 RCC_MCODIV_64 |
| TanakaTarou | 11:debd1264bae8 | 2180 | #define RCC_MCO_DIV128 RCC_MCODIV_128 |
| TanakaTarou | 11:debd1264bae8 | 2181 | #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK |
| TanakaTarou | 11:debd1264bae8 | 2182 | #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI |
| TanakaTarou | 11:debd1264bae8 | 2183 | #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE |
| TanakaTarou | 11:debd1264bae8 | 2184 | #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK |
| TanakaTarou | 11:debd1264bae8 | 2185 | #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI |
| TanakaTarou | 11:debd1264bae8 | 2186 | #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 |
| TanakaTarou | 11:debd1264bae8 | 2187 | #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 |
| TanakaTarou | 11:debd1264bae8 | 2188 | #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE |
| TanakaTarou | 11:debd1264bae8 | 2189 | #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK |
| TanakaTarou | 11:debd1264bae8 | 2190 | #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK |
| TanakaTarou | 11:debd1264bae8 | 2191 | #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 |
| TanakaTarou | 11:debd1264bae8 | 2192 | |
| TanakaTarou | 11:debd1264bae8 | 2193 | #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK |
| TanakaTarou | 11:debd1264bae8 | 2194 | |
| TanakaTarou | 11:debd1264bae8 | 2195 | #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 |
| TanakaTarou | 11:debd1264bae8 | 2196 | #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL |
| TanakaTarou | 11:debd1264bae8 | 2197 | #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI |
| TanakaTarou | 11:debd1264bae8 | 2198 | #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL |
| TanakaTarou | 11:debd1264bae8 | 2199 | #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL |
| TanakaTarou | 11:debd1264bae8 | 2200 | #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 |
| TanakaTarou | 11:debd1264bae8 | 2201 | #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 |
| TanakaTarou | 11:debd1264bae8 | 2202 | #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 |
| TanakaTarou | 11:debd1264bae8 | 2203 | |
| TanakaTarou | 11:debd1264bae8 | 2204 | #define HSION_BitNumber RCC_HSION_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2205 | #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2206 | #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2207 | #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2208 | #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2209 | #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2210 | #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2211 | #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2212 | #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2213 | #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2214 | #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2215 | #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2216 | #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2217 | #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2218 | #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2219 | #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2220 | #define LSION_BitNumber RCC_LSION_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2221 | #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2222 | #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2223 | #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2224 | #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2225 | #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2226 | #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2227 | #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2228 | #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2229 | #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER |
| TanakaTarou | 11:debd1264bae8 | 2230 | #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS |
| TanakaTarou | 11:debd1264bae8 | 2231 | #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS |
| TanakaTarou | 11:debd1264bae8 | 2232 | #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS |
| TanakaTarou | 11:debd1264bae8 | 2233 | #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS |
| TanakaTarou | 11:debd1264bae8 | 2234 | #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE |
| TanakaTarou | 11:debd1264bae8 | 2235 | #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE |
| TanakaTarou | 11:debd1264bae8 | 2236 | |
| TanakaTarou | 11:debd1264bae8 | 2237 | #define CR_HSION_BB RCC_CR_HSION_BB |
| TanakaTarou | 11:debd1264bae8 | 2238 | #define CR_CSSON_BB RCC_CR_CSSON_BB |
| TanakaTarou | 11:debd1264bae8 | 2239 | #define CR_PLLON_BB RCC_CR_PLLON_BB |
| TanakaTarou | 11:debd1264bae8 | 2240 | #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB |
| TanakaTarou | 11:debd1264bae8 | 2241 | #define CR_MSION_BB RCC_CR_MSION_BB |
| TanakaTarou | 11:debd1264bae8 | 2242 | #define CSR_LSION_BB RCC_CSR_LSION_BB |
| TanakaTarou | 11:debd1264bae8 | 2243 | #define CSR_LSEON_BB RCC_CSR_LSEON_BB |
| TanakaTarou | 11:debd1264bae8 | 2244 | #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB |
| TanakaTarou | 11:debd1264bae8 | 2245 | #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB |
| TanakaTarou | 11:debd1264bae8 | 2246 | #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB |
| TanakaTarou | 11:debd1264bae8 | 2247 | #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB |
| TanakaTarou | 11:debd1264bae8 | 2248 | #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB |
| TanakaTarou | 11:debd1264bae8 | 2249 | #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB |
| TanakaTarou | 11:debd1264bae8 | 2250 | #define CR_HSEON_BB RCC_CR_HSEON_BB |
| TanakaTarou | 11:debd1264bae8 | 2251 | #define CSR_RMVF_BB RCC_CSR_RMVF_BB |
| TanakaTarou | 11:debd1264bae8 | 2252 | #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB |
| TanakaTarou | 11:debd1264bae8 | 2253 | #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB |
| TanakaTarou | 11:debd1264bae8 | 2254 | |
| TanakaTarou | 11:debd1264bae8 | 2255 | #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2256 | #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 2257 | #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2258 | #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 2259 | #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE |
| TanakaTarou | 11:debd1264bae8 | 2260 | |
| TanakaTarou | 11:debd1264bae8 | 2261 | #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT |
| TanakaTarou | 11:debd1264bae8 | 2262 | |
| TanakaTarou | 11:debd1264bae8 | 2263 | #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN |
| TanakaTarou | 11:debd1264bae8 | 2264 | #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF |
| TanakaTarou | 11:debd1264bae8 | 2265 | |
| TanakaTarou | 11:debd1264bae8 | 2266 | #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 |
| TanakaTarou | 11:debd1264bae8 | 2267 | #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ |
| TanakaTarou | 11:debd1264bae8 | 2268 | #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP |
| TanakaTarou | 11:debd1264bae8 | 2269 | #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ |
| TanakaTarou | 11:debd1264bae8 | 2270 | #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE |
| TanakaTarou | 11:debd1264bae8 | 2271 | #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 |
| TanakaTarou | 11:debd1264bae8 | 2272 | |
| TanakaTarou | 11:debd1264bae8 | 2273 | #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2274 | #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 2275 | #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2276 | #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2277 | #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET |
| TanakaTarou | 11:debd1264bae8 | 2278 | #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET |
| TanakaTarou | 11:debd1264bae8 | 2279 | #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2280 | #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 2281 | #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2282 | #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2283 | #define DfsdmClockSelection Dfsdm1ClockSelection |
| TanakaTarou | 11:debd1264bae8 | 2284 | #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 |
| TanakaTarou | 11:debd1264bae8 | 2285 | #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 |
| TanakaTarou | 11:debd1264bae8 | 2286 | #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK |
| TanakaTarou | 11:debd1264bae8 | 2287 | #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG |
| TanakaTarou | 11:debd1264bae8 | 2288 | #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE |
| TanakaTarou | 11:debd1264bae8 | 2289 | #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 |
| TanakaTarou | 11:debd1264bae8 | 2290 | #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 |
| TanakaTarou | 11:debd1264bae8 | 2291 | #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 |
| TanakaTarou | 11:debd1264bae8 | 2292 | #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 |
| TanakaTarou | 11:debd1264bae8 | 2293 | |
| TanakaTarou | 11:debd1264bae8 | 2294 | #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 |
| TanakaTarou | 11:debd1264bae8 | 2295 | #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 |
| TanakaTarou | 11:debd1264bae8 | 2296 | #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 |
| TanakaTarou | 11:debd1264bae8 | 2297 | #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 |
| TanakaTarou | 11:debd1264bae8 | 2298 | #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 |
| TanakaTarou | 11:debd1264bae8 | 2299 | #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 |
| TanakaTarou | 11:debd1264bae8 | 2300 | #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 |
| TanakaTarou | 11:debd1264bae8 | 2301 | |
| TanakaTarou | 11:debd1264bae8 | 2302 | #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) |
| TanakaTarou | 11:debd1264bae8 | 2303 | |
| TanakaTarou | 11:debd1264bae8 | 2304 | #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG |
| TanakaTarou | 11:debd1264bae8 | 2305 | #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 2306 | #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 2307 | |
| TanakaTarou | 11:debd1264bae8 | 2308 | #if defined (STM32F1) |
| TanakaTarou | 11:debd1264bae8 | 2309 | #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() |
| TanakaTarou | 11:debd1264bae8 | 2310 | |
| TanakaTarou | 11:debd1264bae8 | 2311 | #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() |
| TanakaTarou | 11:debd1264bae8 | 2312 | |
| TanakaTarou | 11:debd1264bae8 | 2313 | #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() |
| TanakaTarou | 11:debd1264bae8 | 2314 | |
| TanakaTarou | 11:debd1264bae8 | 2315 | #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() |
| TanakaTarou | 11:debd1264bae8 | 2316 | |
| TanakaTarou | 11:debd1264bae8 | 2317 | #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() |
| TanakaTarou | 11:debd1264bae8 | 2318 | #else |
| TanakaTarou | 11:debd1264bae8 | 2319 | #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 2320 | (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 2321 | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) |
| TanakaTarou | 11:debd1264bae8 | 2322 | #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 2323 | (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 2324 | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) |
| TanakaTarou | 11:debd1264bae8 | 2325 | #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 2326 | (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ |
| TanakaTarou | 11:debd1264bae8 | 2327 | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) |
| TanakaTarou | 11:debd1264bae8 | 2328 | #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 2329 | (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ |
| TanakaTarou | 11:debd1264bae8 | 2330 | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) |
| TanakaTarou | 11:debd1264bae8 | 2331 | #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ |
| TanakaTarou | 11:debd1264bae8 | 2332 | (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ |
| TanakaTarou | 11:debd1264bae8 | 2333 | __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) |
| TanakaTarou | 11:debd1264bae8 | 2334 | #endif /* STM32F1 */ |
| TanakaTarou | 11:debd1264bae8 | 2335 | |
| TanakaTarou | 11:debd1264bae8 | 2336 | #define IS_ALARM IS_RTC_ALARM |
| TanakaTarou | 11:debd1264bae8 | 2337 | #define IS_ALARM_MASK IS_RTC_ALARM_MASK |
| TanakaTarou | 11:debd1264bae8 | 2338 | #define IS_TAMPER IS_RTC_TAMPER |
| TanakaTarou | 11:debd1264bae8 | 2339 | #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE |
| TanakaTarou | 11:debd1264bae8 | 2340 | #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER |
| TanakaTarou | 11:debd1264bae8 | 2341 | #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT |
| TanakaTarou | 11:debd1264bae8 | 2342 | #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE |
| TanakaTarou | 11:debd1264bae8 | 2343 | #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION |
| TanakaTarou | 11:debd1264bae8 | 2344 | #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE |
| TanakaTarou | 11:debd1264bae8 | 2345 | #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ |
| TanakaTarou | 11:debd1264bae8 | 2346 | #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION |
| TanakaTarou | 11:debd1264bae8 | 2347 | #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER |
| TanakaTarou | 11:debd1264bae8 | 2348 | #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK |
| TanakaTarou | 11:debd1264bae8 | 2349 | #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER |
| TanakaTarou | 11:debd1264bae8 | 2350 | |
| TanakaTarou | 11:debd1264bae8 | 2351 | #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2352 | #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 2353 | |
| TanakaTarou | 11:debd1264bae8 | 2354 | #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE |
| TanakaTarou | 11:debd1264bae8 | 2355 | #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS |
| TanakaTarou | 11:debd1264bae8 | 2356 | |
| TanakaTarou | 11:debd1264bae8 | 2357 | #if defined(STM32F4) |
| TanakaTarou | 11:debd1264bae8 | 2358 | #define SD_SDMMC_DISABLED SD_SDIO_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2359 | #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY |
| TanakaTarou | 11:debd1264bae8 | 2360 | #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED |
| TanakaTarou | 11:debd1264bae8 | 2361 | #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION |
| TanakaTarou | 11:debd1264bae8 | 2362 | #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND |
| TanakaTarou | 11:debd1264bae8 | 2363 | #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT |
| TanakaTarou | 11:debd1264bae8 | 2364 | #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED |
| TanakaTarou | 11:debd1264bae8 | 2365 | #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2366 | #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 2367 | #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2368 | #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL |
| TanakaTarou | 11:debd1264bae8 | 2369 | #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 2370 | #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 2371 | #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG |
| TanakaTarou | 11:debd1264bae8 | 2372 | #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG |
| TanakaTarou | 11:debd1264bae8 | 2373 | #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT |
| TanakaTarou | 11:debd1264bae8 | 2374 | #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT |
| TanakaTarou | 11:debd1264bae8 | 2375 | #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS |
| TanakaTarou | 11:debd1264bae8 | 2376 | #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT |
| TanakaTarou | 11:debd1264bae8 | 2377 | #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND |
| TanakaTarou | 11:debd1264bae8 | 2378 | /* alias CMSIS */ |
| TanakaTarou | 11:debd1264bae8 | 2379 | #define SDMMC1_IRQn SDIO_IRQn |
| TanakaTarou | 11:debd1264bae8 | 2380 | #define SDMMC1_IRQHandler SDIO_IRQHandler |
| TanakaTarou | 11:debd1264bae8 | 2381 | #endif |
| TanakaTarou | 11:debd1264bae8 | 2382 | |
| TanakaTarou | 11:debd1264bae8 | 2383 | #if defined(STM32F7) || defined(STM32L4) |
| TanakaTarou | 11:debd1264bae8 | 2384 | #define SD_SDIO_DISABLED SD_SDMMC_DISABLED |
| TanakaTarou | 11:debd1264bae8 | 2385 | #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY |
| TanakaTarou | 11:debd1264bae8 | 2386 | #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED |
| TanakaTarou | 11:debd1264bae8 | 2387 | #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION |
| TanakaTarou | 11:debd1264bae8 | 2388 | #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND |
| TanakaTarou | 11:debd1264bae8 | 2389 | #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT |
| TanakaTarou | 11:debd1264bae8 | 2390 | #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED |
| TanakaTarou | 11:debd1264bae8 | 2391 | #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2392 | #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 2393 | #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2394 | #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 2395 | #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 2396 | #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 2397 | #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG |
| TanakaTarou | 11:debd1264bae8 | 2398 | #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG |
| TanakaTarou | 11:debd1264bae8 | 2399 | #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT |
| TanakaTarou | 11:debd1264bae8 | 2400 | #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT |
| TanakaTarou | 11:debd1264bae8 | 2401 | #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS |
| TanakaTarou | 11:debd1264bae8 | 2402 | #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT |
| TanakaTarou | 11:debd1264bae8 | 2403 | #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND |
| TanakaTarou | 11:debd1264bae8 | 2404 | /* alias CMSIS for compatibilities */ |
| TanakaTarou | 11:debd1264bae8 | 2405 | #define SDIO_IRQn SDMMC1_IRQn |
| TanakaTarou | 11:debd1264bae8 | 2406 | #define SDIO_IRQHandler SDMMC1_IRQHandler |
| TanakaTarou | 11:debd1264bae8 | 2407 | #endif |
| TanakaTarou | 11:debd1264bae8 | 2408 | |
| TanakaTarou | 11:debd1264bae8 | 2409 | #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) |
| TanakaTarou | 11:debd1264bae8 | 2410 | #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef |
| TanakaTarou | 11:debd1264bae8 | 2411 | #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef |
| TanakaTarou | 11:debd1264bae8 | 2412 | #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef |
| TanakaTarou | 11:debd1264bae8 | 2413 | #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef |
| TanakaTarou | 11:debd1264bae8 | 2414 | #endif |
| TanakaTarou | 11:debd1264bae8 | 2415 | |
| TanakaTarou | 11:debd1264bae8 | 2416 | #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 2417 | #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 2418 | #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2419 | #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 2420 | #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2421 | #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 2422 | |
| TanakaTarou | 11:debd1264bae8 | 2423 | #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE |
| TanakaTarou | 11:debd1264bae8 | 2424 | #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE |
| TanakaTarou | 11:debd1264bae8 | 2425 | |
| TanakaTarou | 11:debd1264bae8 | 2426 | #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE |
| TanakaTarou | 11:debd1264bae8 | 2427 | |
| TanakaTarou | 11:debd1264bae8 | 2428 | #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 |
| TanakaTarou | 11:debd1264bae8 | 2429 | #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 |
| TanakaTarou | 11:debd1264bae8 | 2430 | #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START |
| TanakaTarou | 11:debd1264bae8 | 2431 | #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH |
| TanakaTarou | 11:debd1264bae8 | 2432 | #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR |
| TanakaTarou | 11:debd1264bae8 | 2433 | #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE |
| TanakaTarou | 11:debd1264bae8 | 2434 | #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE |
| TanakaTarou | 11:debd1264bae8 | 2435 | #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED |
| TanakaTarou | 11:debd1264bae8 | 2436 | |
| TanakaTarou | 11:debd1264bae8 | 2437 | #define __HAL_SPI_1LINE_TX SPI_1LINE_TX |
| TanakaTarou | 11:debd1264bae8 | 2438 | #define __HAL_SPI_1LINE_RX SPI_1LINE_RX |
| TanakaTarou | 11:debd1264bae8 | 2439 | #define __HAL_SPI_RESET_CRC SPI_RESET_CRC |
| TanakaTarou | 11:debd1264bae8 | 2440 | |
| TanakaTarou | 11:debd1264bae8 | 2441 | #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE |
| TanakaTarou | 11:debd1264bae8 | 2442 | #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION |
| TanakaTarou | 11:debd1264bae8 | 2443 | #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE |
| TanakaTarou | 11:debd1264bae8 | 2444 | #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION |
| TanakaTarou | 11:debd1264bae8 | 2445 | |
| TanakaTarou | 11:debd1264bae8 | 2446 | #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD |
| TanakaTarou | 11:debd1264bae8 | 2447 | |
| TanakaTarou | 11:debd1264bae8 | 2448 | #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE |
| TanakaTarou | 11:debd1264bae8 | 2449 | #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE |
| TanakaTarou | 11:debd1264bae8 | 2450 | |
| TanakaTarou | 11:debd1264bae8 | 2451 | #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 2452 | #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 2453 | #define __USART_ENABLE __HAL_USART_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2454 | #define __USART_DISABLE __HAL_USART_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 2455 | |
| TanakaTarou | 11:debd1264bae8 | 2456 | #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE |
| TanakaTarou | 11:debd1264bae8 | 2457 | #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE |
| TanakaTarou | 11:debd1264bae8 | 2458 | |
| TanakaTarou | 11:debd1264bae8 | 2459 | #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE |
| TanakaTarou | 11:debd1264bae8 | 2460 | |
| TanakaTarou | 11:debd1264bae8 | 2461 | #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 2462 | #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 2463 | #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 2464 | #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE |
| TanakaTarou | 11:debd1264bae8 | 2465 | |
| TanakaTarou | 11:debd1264bae8 | 2466 | #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 2467 | #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 2468 | #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 2469 | #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE |
| TanakaTarou | 11:debd1264bae8 | 2470 | |
| TanakaTarou | 11:debd1264bae8 | 2471 | #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 2472 | #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 2473 | #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG |
| TanakaTarou | 11:debd1264bae8 | 2474 | #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG |
| TanakaTarou | 11:debd1264bae8 | 2475 | #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 2476 | #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 2477 | #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 2478 | |
| TanakaTarou | 11:debd1264bae8 | 2479 | #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 2480 | #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 2481 | #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG |
| TanakaTarou | 11:debd1264bae8 | 2482 | #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG |
| TanakaTarou | 11:debd1264bae8 | 2483 | #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 2484 | #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 2485 | #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 2486 | #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT |
| TanakaTarou | 11:debd1264bae8 | 2487 | |
| TanakaTarou | 11:debd1264bae8 | 2488 | #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 2489 | #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 2490 | #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG |
| TanakaTarou | 11:debd1264bae8 | 2491 | #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG |
| TanakaTarou | 11:debd1264bae8 | 2492 | #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 2493 | #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 2494 | #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE |
| TanakaTarou | 11:debd1264bae8 | 2495 | #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT |
| TanakaTarou | 11:debd1264bae8 | 2496 | |
| TanakaTarou | 11:debd1264bae8 | 2497 | #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup |
| TanakaTarou | 11:debd1264bae8 | 2498 | #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup |
| TanakaTarou | 11:debd1264bae8 | 2499 | |
| TanakaTarou | 11:debd1264bae8 | 2500 | #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo |
| TanakaTarou | 11:debd1264bae8 | 2501 | #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo |
| TanakaTarou | 11:debd1264bae8 | 2502 | |
| TanakaTarou | 11:debd1264bae8 | 2503 | #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE |
| TanakaTarou | 11:debd1264bae8 | 2504 | #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE |
| TanakaTarou | 11:debd1264bae8 | 2505 | |
| TanakaTarou | 11:debd1264bae8 | 2506 | #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE |
| TanakaTarou | 11:debd1264bae8 | 2507 | #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT |
| TanakaTarou | 11:debd1264bae8 | 2508 | |
| TanakaTarou | 11:debd1264bae8 | 2509 | #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE |
| TanakaTarou | 11:debd1264bae8 | 2510 | |
| TanakaTarou | 11:debd1264bae8 | 2511 | #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN |
| TanakaTarou | 11:debd1264bae8 | 2512 | #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER |
| TanakaTarou | 11:debd1264bae8 | 2513 | #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER |
| TanakaTarou | 11:debd1264bae8 | 2514 | #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER |
| TanakaTarou | 11:debd1264bae8 | 2515 | #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD |
| TanakaTarou | 11:debd1264bae8 | 2516 | #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD |
| TanakaTarou | 11:debd1264bae8 | 2517 | #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION |
| TanakaTarou | 11:debd1264bae8 | 2518 | #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION |
| TanakaTarou | 11:debd1264bae8 | 2519 | #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER |
| TanakaTarou | 11:debd1264bae8 | 2520 | #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER |
| TanakaTarou | 11:debd1264bae8 | 2521 | #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE |
| TanakaTarou | 11:debd1264bae8 | 2522 | #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE |
| TanakaTarou | 11:debd1264bae8 | 2523 | |
| TanakaTarou | 11:debd1264bae8 | 2524 | #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 |
| TanakaTarou | 11:debd1264bae8 | 2525 | |
| TanakaTarou | 11:debd1264bae8 | 2526 | #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 2527 | #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT |
| TanakaTarou | 11:debd1264bae8 | 2528 | #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG |
| TanakaTarou | 11:debd1264bae8 | 2529 | #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG |
| TanakaTarou | 11:debd1264bae8 | 2530 | #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER |
| TanakaTarou | 11:debd1264bae8 | 2531 | #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER |
| TanakaTarou | 11:debd1264bae8 | 2532 | #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER |
| TanakaTarou | 11:debd1264bae8 | 2533 | |
| TanakaTarou | 11:debd1264bae8 | 2534 | #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2535 | #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 2536 | #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE |
| TanakaTarou | 11:debd1264bae8 | 2537 | |
| TanakaTarou | 11:debd1264bae8 | 2538 | #define __HAL_LTDC_LAYER LTDC_LAYER |
| TanakaTarou | 11:debd1264bae8 | 2539 | #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG |
| TanakaTarou | 11:debd1264bae8 | 2540 | |
| TanakaTarou | 11:debd1264bae8 | 2541 | #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 2542 | #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2543 | #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2544 | #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE |
| TanakaTarou | 11:debd1264bae8 | 2545 | #define SAI_STREOMODE SAI_STEREOMODE |
| TanakaTarou | 11:debd1264bae8 | 2546 | #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY |
| TanakaTarou | 11:debd1264bae8 | 2547 | #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL |
| TanakaTarou | 11:debd1264bae8 | 2548 | #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL |
| TanakaTarou | 11:debd1264bae8 | 2549 | #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL |
| TanakaTarou | 11:debd1264bae8 | 2550 | #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL |
| TanakaTarou | 11:debd1264bae8 | 2551 | #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL |
| TanakaTarou | 11:debd1264bae8 | 2552 | #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE |
| TanakaTarou | 11:debd1264bae8 | 2553 | #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 |
| TanakaTarou | 11:debd1264bae8 | 2554 | #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE |
| TanakaTarou | 11:debd1264bae8 | 2555 | |
| TanakaTarou | 11:debd1264bae8 | 2556 | #ifdef __cplusplus |
| TanakaTarou | 11:debd1264bae8 | 2557 | } |
| TanakaTarou | 11:debd1264bae8 | 2558 | #endif |
| TanakaTarou | 11:debd1264bae8 | 2559 | |
| TanakaTarou | 11:debd1264bae8 | 2560 | #endif /* ___STM32_HAL_LEGACY */ |