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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_ldma.h@161:2cc1468da177, 2017-03-30 (annotated)

Committer:
<>
Date:
Thu Mar 30 13:45:57 2017 +0100
Revision:
161:2cc1468da177
Parent:
153:fa9ff456f731 
This updates the lib to the mbed lib v139

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 153:fa9ff456f731 1 /**************************************************************************//**
<> 153:fa9ff456f731 2 * @file efr32mg1p_ldma.h
<> 153:fa9ff456f731 3 * @brief EFR32MG1P_LDMA register and bit field definitions
<> 161:2cc1468da177 4 * @version 5.1.2
<> 153:fa9ff456f731 5 ******************************************************************************
<> 153:fa9ff456f731 6 * @section License
<> 161:2cc1468da177 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 153:fa9ff456f731 8 ******************************************************************************
<> 153:fa9ff456f731 9 *
<> 153:fa9ff456f731 10 * Permission is granted to anyone to use this software for any purpose,
<> 153:fa9ff456f731 11 * including commercial applications, and to alter it and redistribute it
<> 153:fa9ff456f731 12 * freely, subject to the following restrictions:
<> 153:fa9ff456f731 13 *
<> 153:fa9ff456f731 14 * 1. The origin of this software must not be misrepresented; you must not
<> 153:fa9ff456f731 15 * claim that you wrote the original software.@n
<> 153:fa9ff456f731 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 153:fa9ff456f731 17 * misrepresented as being the original software.@n
<> 153:fa9ff456f731 18 * 3. This notice may not be removed or altered from any source distribution.
<> 153:fa9ff456f731 19 *
<> 153:fa9ff456f731 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 153:fa9ff456f731 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 153:fa9ff456f731 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 153:fa9ff456f731 23 * kind, including, but not limited to, any implied warranties of
<> 153:fa9ff456f731 24 * merchantability or fitness for any particular purpose or warranties against
<> 153:fa9ff456f731 25 * infringement of any proprietary rights of a third party.
<> 153:fa9ff456f731 26 *
<> 153:fa9ff456f731 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 153:fa9ff456f731 28 * incidental, or special damages, or any other relief, or for any claim by
<> 153:fa9ff456f731 29 * any third party, arising from your use of this Software.
<> 153:fa9ff456f731 30 *
<> 153:fa9ff456f731 31 *****************************************************************************/
<> 153:fa9ff456f731 32 /**************************************************************************//**
<> 153:fa9ff456f731 33 * @addtogroup Parts
<> 153:fa9ff456f731 34 * @{
<> 153:fa9ff456f731 35 ******************************************************************************/
<> 153:fa9ff456f731 36 /**************************************************************************//**
<> 153:fa9ff456f731 37 * @defgroup EFR32MG1P_LDMA
<> 153:fa9ff456f731 38 * @{
<> 153:fa9ff456f731 39 * @brief EFR32MG1P_LDMA Register Declaration
<> 153:fa9ff456f731 40 *****************************************************************************/
<> 153:fa9ff456f731 41 typedef struct
<> 153:fa9ff456f731 42 {
<> 153:fa9ff456f731 43 __IOM uint32_t CTRL; /**< DMA Control Register */
<> 153:fa9ff456f731 44 __IM uint32_t STATUS; /**< DMA Status Register */
<> 153:fa9ff456f731 45 __IOM uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */
<> 153:fa9ff456f731 46 uint32_t RESERVED0[5]; /**< Reserved for future use **/
<> 153:fa9ff456f731 47 __IOM uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */
<> 153:fa9ff456f731 48 __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */
<> 153:fa9ff456f731 49 __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */
<> 153:fa9ff456f731 50 __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */
<> 153:fa9ff456f731 51 __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request Register */
<> 153:fa9ff456f731 52 __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */
<> 153:fa9ff456f731 53 __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */
<> 153:fa9ff456f731 54 __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */
<> 153:fa9ff456f731 55 __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */
<> 153:fa9ff456f731 56 uint32_t RESERVED1[7]; /**< Reserved for future use **/
<> 153:fa9ff456f731 57 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 153:fa9ff456f731 58 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 153:fa9ff456f731 59 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 153:fa9ff456f731 60 __IOM uint32_t IEN; /**< Interrupt Enable register */
<> 153:fa9ff456f731 61
<> 153:fa9ff456f731 62 uint32_t RESERVED2[4]; /**< Reserved registers */
<> 153:fa9ff456f731 63 LDMA_CH_TypeDef CH[8]; /**< DMA Channel Registers */
<> 153:fa9ff456f731 64 } LDMA_TypeDef; /** @} */
<> 153:fa9ff456f731 65
<> 153:fa9ff456f731 66 /**************************************************************************//**
<> 153:fa9ff456f731 67 * @defgroup EFR32MG1P_LDMA_BitFields
<> 153:fa9ff456f731 68 * @{
<> 153:fa9ff456f731 69 *****************************************************************************/
<> 153:fa9ff456f731 70
<> 153:fa9ff456f731 71 /* Bit fields for LDMA CTRL */
<> 153:fa9ff456f731 72 #define _LDMA_CTRL_RESETVALUE 0x07000000UL /**< Default value for LDMA_CTRL */
<> 153:fa9ff456f731 73 #define _LDMA_CTRL_MASK 0x0700FFFFUL /**< Mask for LDMA_CTRL */
<> 153:fa9ff456f731 74 #define _LDMA_CTRL_SYNCPRSSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCPRSSETEN */
<> 153:fa9ff456f731 75 #define _LDMA_CTRL_SYNCPRSSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCPRSSETEN */
<> 153:fa9ff456f731 76 #define _LDMA_CTRL_SYNCPRSSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */
<> 153:fa9ff456f731 77 #define LDMA_CTRL_SYNCPRSSETEN_DEFAULT (_LDMA_CTRL_SYNCPRSSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CTRL */
<> 153:fa9ff456f731 78 #define _LDMA_CTRL_SYNCPRSCLREN_SHIFT 8 /**< Shift value for LDMA_SYNCPRSCLREN */
<> 153:fa9ff456f731 79 #define _LDMA_CTRL_SYNCPRSCLREN_MASK 0xFF00UL /**< Bit mask for LDMA_SYNCPRSCLREN */
<> 153:fa9ff456f731 80 #define _LDMA_CTRL_SYNCPRSCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */
<> 153:fa9ff456f731 81 #define LDMA_CTRL_SYNCPRSCLREN_DEFAULT (_LDMA_CTRL_SYNCPRSCLREN_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_CTRL */
<> 153:fa9ff456f731 82 #define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */
<> 153:fa9ff456f731 83 #define _LDMA_CTRL_NUMFIXED_MASK 0x7000000UL /**< Bit mask for LDMA_NUMFIXED */
<> 153:fa9ff456f731 84 #define _LDMA_CTRL_NUMFIXED_DEFAULT 0x00000007UL /**< Mode DEFAULT for LDMA_CTRL */
<> 153:fa9ff456f731 85 #define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */
<> 153:fa9ff456f731 86
<> 153:fa9ff456f731 87 /* Bit fields for LDMA STATUS */
<> 153:fa9ff456f731 88 #define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */
<> 153:fa9ff456f731 89 #define _LDMA_STATUS_MASK 0x1F1F073BUL /**< Mask for LDMA_STATUS */
<> 153:fa9ff456f731 90 #define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */
<> 153:fa9ff456f731 91 #define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */
<> 153:fa9ff456f731 92 #define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */
<> 153:fa9ff456f731 93 #define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
<> 153:fa9ff456f731 94 #define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */
<> 153:fa9ff456f731 95 #define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */
<> 153:fa9ff456f731 96 #define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */
<> 153:fa9ff456f731 97 #define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */
<> 153:fa9ff456f731 98 #define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
<> 153:fa9ff456f731 99 #define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */
<> 153:fa9ff456f731 100 #define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */
<> 153:fa9ff456f731 101 #define _LDMA_STATUS_CHGRANT_MASK 0x38UL /**< Bit mask for LDMA_CHGRANT */
<> 153:fa9ff456f731 102 #define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
<> 153:fa9ff456f731 103 #define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */
<> 153:fa9ff456f731 104 #define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */
<> 153:fa9ff456f731 105 #define _LDMA_STATUS_CHERROR_MASK 0x700UL /**< Bit mask for LDMA_CHERROR */
<> 153:fa9ff456f731 106 #define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
<> 153:fa9ff456f731 107 #define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */
<> 153:fa9ff456f731 108 #define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */
<> 153:fa9ff456f731 109 #define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */
<> 153:fa9ff456f731 110 #define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */
<> 153:fa9ff456f731 111 #define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */
<> 153:fa9ff456f731 112 #define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */
<> 153:fa9ff456f731 113 #define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */
<> 153:fa9ff456f731 114 #define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */
<> 153:fa9ff456f731 115 #define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */
<> 153:fa9ff456f731 116
<> 153:fa9ff456f731 117 /* Bit fields for LDMA SYNC */
<> 153:fa9ff456f731 118 #define _LDMA_SYNC_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNC */
<> 153:fa9ff456f731 119 #define _LDMA_SYNC_MASK 0x000000FFUL /**< Mask for LDMA_SYNC */
<> 153:fa9ff456f731 120 #define _LDMA_SYNC_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */
<> 153:fa9ff456f731 121 #define _LDMA_SYNC_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */
<> 153:fa9ff456f731 122 #define _LDMA_SYNC_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNC */
<> 153:fa9ff456f731 123 #define LDMA_SYNC_SYNCTRIG_DEFAULT (_LDMA_SYNC_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNC */
<> 153:fa9ff456f731 124
<> 153:fa9ff456f731 125 /* Bit fields for LDMA CHEN */
<> 153:fa9ff456f731 126 #define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */
<> 153:fa9ff456f731 127 #define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */
<> 153:fa9ff456f731 128 #define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */
<> 153:fa9ff456f731 129 #define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */
<> 153:fa9ff456f731 130 #define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */
<> 153:fa9ff456f731 131 #define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */
<> 153:fa9ff456f731 132
<> 153:fa9ff456f731 133 /* Bit fields for LDMA CHBUSY */
<> 153:fa9ff456f731 134 #define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */
<> 153:fa9ff456f731 135 #define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */
<> 153:fa9ff456f731 136 #define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */
<> 153:fa9ff456f731 137 #define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */
<> 153:fa9ff456f731 138 #define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */
<> 153:fa9ff456f731 139 #define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */
<> 153:fa9ff456f731 140
<> 153:fa9ff456f731 141 /* Bit fields for LDMA CHDONE */
<> 153:fa9ff456f731 142 #define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */
<> 153:fa9ff456f731 143 #define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */
<> 153:fa9ff456f731 144 #define _LDMA_CHDONE_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */
<> 153:fa9ff456f731 145 #define _LDMA_CHDONE_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */
<> 153:fa9ff456f731 146 #define _LDMA_CHDONE_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
<> 153:fa9ff456f731 147 #define LDMA_CHDONE_CHDONE_DEFAULT (_LDMA_CHDONE_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */
<> 153:fa9ff456f731 148
<> 153:fa9ff456f731 149 /* Bit fields for LDMA DBGHALT */
<> 153:fa9ff456f731 150 #define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */
<> 153:fa9ff456f731 151 #define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */
<> 153:fa9ff456f731 152 #define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */
<> 153:fa9ff456f731 153 #define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */
<> 153:fa9ff456f731 154 #define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */
<> 153:fa9ff456f731 155 #define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */
<> 153:fa9ff456f731 156
<> 153:fa9ff456f731 157 /* Bit fields for LDMA SWREQ */
<> 153:fa9ff456f731 158 #define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */
<> 153:fa9ff456f731 159 #define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */
<> 153:fa9ff456f731 160 #define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */
<> 153:fa9ff456f731 161 #define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */
<> 153:fa9ff456f731 162 #define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */
<> 153:fa9ff456f731 163 #define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */
<> 153:fa9ff456f731 164
<> 153:fa9ff456f731 165 /* Bit fields for LDMA REQDIS */
<> 153:fa9ff456f731 166 #define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */
<> 153:fa9ff456f731 167 #define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */
<> 153:fa9ff456f731 168 #define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */
<> 153:fa9ff456f731 169 #define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */
<> 153:fa9ff456f731 170 #define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */
<> 153:fa9ff456f731 171 #define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */
<> 153:fa9ff456f731 172
<> 153:fa9ff456f731 173 /* Bit fields for LDMA REQPEND */
<> 153:fa9ff456f731 174 #define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */
<> 153:fa9ff456f731 175 #define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */
<> 153:fa9ff456f731 176 #define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */
<> 153:fa9ff456f731 177 #define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */
<> 153:fa9ff456f731 178 #define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */
<> 153:fa9ff456f731 179 #define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */
<> 153:fa9ff456f731 180
<> 153:fa9ff456f731 181 /* Bit fields for LDMA LINKLOAD */
<> 153:fa9ff456f731 182 #define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */
<> 153:fa9ff456f731 183 #define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */
<> 153:fa9ff456f731 184 #define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */
<> 153:fa9ff456f731 185 #define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */
<> 153:fa9ff456f731 186 #define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */
<> 153:fa9ff456f731 187 #define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */
<> 153:fa9ff456f731 188
<> 153:fa9ff456f731 189 /* Bit fields for LDMA REQCLEAR */
<> 153:fa9ff456f731 190 #define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */
<> 153:fa9ff456f731 191 #define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */
<> 153:fa9ff456f731 192 #define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */
<> 153:fa9ff456f731 193 #define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */
<> 153:fa9ff456f731 194 #define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */
<> 153:fa9ff456f731 195 #define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */
<> 153:fa9ff456f731 196
<> 153:fa9ff456f731 197 /* Bit fields for LDMA IF */
<> 153:fa9ff456f731 198 #define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */
<> 153:fa9ff456f731 199 #define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */
<> 153:fa9ff456f731 200 #define _LDMA_IF_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
<> 153:fa9ff456f731 201 #define _LDMA_IF_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */
<> 153:fa9ff456f731 202 #define _LDMA_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
<> 153:fa9ff456f731 203 #define LDMA_IF_DONE_DEFAULT (_LDMA_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */
<> 153:fa9ff456f731 204 #define LDMA_IF_ERROR (0x1UL << 31) /**< Transfer Error Interrupt Flag */
<> 153:fa9ff456f731 205 #define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
<> 153:fa9ff456f731 206 #define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
<> 153:fa9ff456f731 207 #define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
<> 153:fa9ff456f731 208 #define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */
<> 153:fa9ff456f731 209
<> 153:fa9ff456f731 210 /* Bit fields for LDMA IFS */
<> 153:fa9ff456f731 211 #define _LDMA_IFS_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFS */
<> 153:fa9ff456f731 212 #define _LDMA_IFS_MASK 0x800000FFUL /**< Mask for LDMA_IFS */
<> 153:fa9ff456f731 213 #define _LDMA_IFS_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
<> 153:fa9ff456f731 214 #define _LDMA_IFS_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */
<> 153:fa9ff456f731 215 #define _LDMA_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */
<> 153:fa9ff456f731 216 #define LDMA_IFS_DONE_DEFAULT (_LDMA_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFS */
<> 153:fa9ff456f731 217 #define LDMA_IFS_ERROR (0x1UL << 31) /**< Set ERROR Interrupt Flag */
<> 153:fa9ff456f731 218 #define _LDMA_IFS_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
<> 153:fa9ff456f731 219 #define _LDMA_IFS_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
<> 153:fa9ff456f731 220 #define _LDMA_IFS_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */
<> 153:fa9ff456f731 221 #define LDMA_IFS_ERROR_DEFAULT (_LDMA_IFS_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFS */
<> 153:fa9ff456f731 222
<> 153:fa9ff456f731 223 /* Bit fields for LDMA IFC */
<> 153:fa9ff456f731 224 #define _LDMA_IFC_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFC */
<> 153:fa9ff456f731 225 #define _LDMA_IFC_MASK 0x800000FFUL /**< Mask for LDMA_IFC */
<> 153:fa9ff456f731 226 #define _LDMA_IFC_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
<> 153:fa9ff456f731 227 #define _LDMA_IFC_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */
<> 153:fa9ff456f731 228 #define _LDMA_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */
<> 153:fa9ff456f731 229 #define LDMA_IFC_DONE_DEFAULT (_LDMA_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFC */
<> 153:fa9ff456f731 230 #define LDMA_IFC_ERROR (0x1UL << 31) /**< Clear ERROR Interrupt Flag */
<> 153:fa9ff456f731 231 #define _LDMA_IFC_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
<> 153:fa9ff456f731 232 #define _LDMA_IFC_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
<> 153:fa9ff456f731 233 #define _LDMA_IFC_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */
<> 153:fa9ff456f731 234 #define LDMA_IFC_ERROR_DEFAULT (_LDMA_IFC_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFC */
<> 153:fa9ff456f731 235
<> 153:fa9ff456f731 236 /* Bit fields for LDMA IEN */
<> 153:fa9ff456f731 237 #define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */
<> 153:fa9ff456f731 238 #define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */
<> 153:fa9ff456f731 239 #define _LDMA_IEN_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
<> 153:fa9ff456f731 240 #define _LDMA_IEN_DONE_MASK 0xFFUL /**< Bit mask for LDMA_DONE */
<> 153:fa9ff456f731 241 #define _LDMA_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */
<> 153:fa9ff456f731 242 #define LDMA_IEN_DONE_DEFAULT (_LDMA_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */
<> 153:fa9ff456f731 243 #define LDMA_IEN_ERROR (0x1UL << 31) /**< ERROR Interrupt Enable */
<> 153:fa9ff456f731 244 #define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
<> 153:fa9ff456f731 245 #define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
<> 153:fa9ff456f731 246 #define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */
<> 153:fa9ff456f731 247 #define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */
<> 153:fa9ff456f731 248
<> 153:fa9ff456f731 249 /* Bit fields for LDMA CH_REQSEL */
<> 153:fa9ff456f731 250 #define _LDMA_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 251 #define _LDMA_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 252 #define _LDMA_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMA_SIGSEL */
<> 153:fa9ff456f731 253 #define _LDMA_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMA_SIGSEL */
<> 153:fa9ff456f731 254 #define _LDMA_CH_REQSEL_SIGSEL_PRSREQ0 0x00000000UL /**< Mode PRSREQ0 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 255 #define _LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 256 #define _LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 257 #define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 258 #define _LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 259 #define _LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 260 #define _LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 261 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 262 #define _LDMA_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 263 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR 0x00000000UL /**< Mode CRYPTODATA0WR for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 264 #define _LDMA_CH_REQSEL_SIGSEL_PRSREQ1 0x00000001UL /**< Mode PRSREQ1 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 265 #define _LDMA_CH_REQSEL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 266 #define _LDMA_CH_REQSEL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 267 #define _LDMA_CH_REQSEL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 268 #define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 269 #define _LDMA_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 270 #define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 271 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 272 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR 0x00000001UL /**< Mode CRYPTODATA0XWR for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 273 #define _LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 274 #define _LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 275 #define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 276 #define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 277 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 278 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD 0x00000002UL /**< Mode CRYPTODATA0RD for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 279 #define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 280 #define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 281 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 282 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR 0x00000003UL /**< Mode CRYPTODATA1WR for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 283 #define _LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 284 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 0x00000004UL /**< Mode TIMER1CC3 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 285 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD 0x00000004UL /**< Mode CRYPTODATA1RD for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 286 #define LDMA_CH_REQSEL_SIGSEL_PRSREQ0 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ0 << 0) /**< Shifted mode PRSREQ0 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 287 #define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 288 #define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 289 #define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 290 #define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 291 #define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 292 #define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 293 #define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 294 #define LDMA_CH_REQSEL_SIGSEL_MSCWDATA (_LDMA_CH_REQSEL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 295 #define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR << 0) /**< Shifted mode CRYPTODATA0WR for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 296 #define LDMA_CH_REQSEL_SIGSEL_PRSREQ1 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ1 << 0) /**< Shifted mode PRSREQ1 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 297 #define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 298 #define LDMA_CH_REQSEL_SIGSEL_USART0TXBL (_LDMA_CH_REQSEL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 299 #define LDMA_CH_REQSEL_SIGSEL_USART1TXBL (_LDMA_CH_REQSEL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 300 #define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 301 #define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 302 #define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 303 #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 304 #define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR << 0) /**< Shifted mode CRYPTODATA0XWR for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 305 #define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 306 #define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 307 #define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 308 #define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 309 #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 310 #define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD << 0) /**< Shifted mode CRYPTODATA0RD for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 311 #define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 312 #define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 313 #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 314 #define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR << 0) /**< Shifted mode CRYPTODATA1WR for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 315 #define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 316 #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 317 #define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD << 0) /**< Shifted mode CRYPTODATA1RD for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 318 #define _LDMA_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMA_SOURCESEL */
<> 153:fa9ff456f731 319 #define _LDMA_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMA_SOURCESEL */
<> 153:fa9ff456f731 320 #define _LDMA_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 321 #define _LDMA_CH_REQSEL_SOURCESEL_PRS 0x00000001UL /**< Mode PRS for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 322 #define _LDMA_CH_REQSEL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 323 #define _LDMA_CH_REQSEL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 324 #define _LDMA_CH_REQSEL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 325 #define _LDMA_CH_REQSEL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 326 #define _LDMA_CH_REQSEL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 327 #define _LDMA_CH_REQSEL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 328 #define _LDMA_CH_REQSEL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 329 #define _LDMA_CH_REQSEL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 330 #define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO 0x00000031UL /**< Mode CRYPTO for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 331 #define LDMA_CH_REQSEL_SOURCESEL_NONE (_LDMA_CH_REQSEL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 332 #define LDMA_CH_REQSEL_SOURCESEL_PRS (_LDMA_CH_REQSEL_SOURCESEL_PRS << 16) /**< Shifted mode PRS for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 333 #define LDMA_CH_REQSEL_SOURCESEL_ADC0 (_LDMA_CH_REQSEL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 334 #define LDMA_CH_REQSEL_SOURCESEL_USART0 (_LDMA_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 335 #define LDMA_CH_REQSEL_SOURCESEL_USART1 (_LDMA_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 336 #define LDMA_CH_REQSEL_SOURCESEL_LEUART0 (_LDMA_CH_REQSEL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 337 #define LDMA_CH_REQSEL_SOURCESEL_I2C0 (_LDMA_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 338 #define LDMA_CH_REQSEL_SOURCESEL_TIMER0 (_LDMA_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 339 #define LDMA_CH_REQSEL_SOURCESEL_TIMER1 (_LDMA_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 340 #define LDMA_CH_REQSEL_SOURCESEL_MSC (_LDMA_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 341 #define LDMA_CH_REQSEL_SOURCESEL_CRYPTO (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO << 16) /**< Shifted mode CRYPTO for LDMA_CH_REQSEL */
<> 153:fa9ff456f731 342
<> 153:fa9ff456f731 343 /* Bit fields for LDMA CH_CFG */
<> 153:fa9ff456f731 344 #define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */
<> 153:fa9ff456f731 345 #define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */
<> 153:fa9ff456f731 346 #define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */
<> 153:fa9ff456f731 347 #define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */
<> 153:fa9ff456f731 348 #define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
<> 153:fa9ff456f731 349 #define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */
<> 153:fa9ff456f731 350 #define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */
<> 153:fa9ff456f731 351 #define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */
<> 153:fa9ff456f731 352 #define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */
<> 153:fa9ff456f731 353 #define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
<> 153:fa9ff456f731 354 #define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */
<> 153:fa9ff456f731 355 #define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */
<> 153:fa9ff456f731 356 #define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */
<> 153:fa9ff456f731 357 #define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */
<> 153:fa9ff456f731 358 #define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */
<> 153:fa9ff456f731 359 #define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */
<> 153:fa9ff456f731 360 #define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */
<> 153:fa9ff456f731 361 #define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
<> 153:fa9ff456f731 362 #define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */
<> 153:fa9ff456f731 363 #define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */
<> 153:fa9ff456f731 364 #define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
<> 153:fa9ff456f731 365 #define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
<> 153:fa9ff456f731 366 #define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
<> 153:fa9ff456f731 367 #define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */
<> 153:fa9ff456f731 368 #define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */
<> 153:fa9ff456f731 369 #define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */
<> 153:fa9ff456f731 370 #define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
<> 153:fa9ff456f731 371 #define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */
<> 153:fa9ff456f731 372 #define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */
<> 153:fa9ff456f731 373 #define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
<> 153:fa9ff456f731 374 #define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
<> 153:fa9ff456f731 375 #define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
<> 153:fa9ff456f731 376
<> 153:fa9ff456f731 377 /* Bit fields for LDMA CH_LOOP */
<> 153:fa9ff456f731 378 #define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */
<> 153:fa9ff456f731 379 #define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */
<> 153:fa9ff456f731 380 #define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */
<> 153:fa9ff456f731 381 #define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */
<> 153:fa9ff456f731 382 #define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */
<> 153:fa9ff456f731 383 #define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */
<> 153:fa9ff456f731 384
<> 153:fa9ff456f731 385 /* Bit fields for LDMA CH_CTRL */
<> 153:fa9ff456f731 386 #define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */
<> 153:fa9ff456f731 387 #define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */
<> 153:fa9ff456f731 388 #define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */
<> 153:fa9ff456f731 389 #define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */
<> 153:fa9ff456f731 390 #define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 391 #define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */
<> 153:fa9ff456f731 392 #define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 393 #define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 394 #define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 395 #define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */
<> 153:fa9ff456f731 396 #define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 397 #define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 398 #define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */
<> 153:fa9ff456f731 399 #define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */
<> 153:fa9ff456f731 400 #define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */
<> 153:fa9ff456f731 401 #define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 402 #define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 403 #define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */
<> 153:fa9ff456f731 404 #define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */
<> 153:fa9ff456f731 405 #define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 406 #define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 407 #define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */
<> 153:fa9ff456f731 408 #define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */
<> 153:fa9ff456f731 409 #define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */
<> 153:fa9ff456f731 410 #define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 411 #define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 412 #define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */
<> 153:fa9ff456f731 413 #define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */
<> 153:fa9ff456f731 414 #define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 415 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 416 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 417 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 418 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 419 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 420 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 421 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 422 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 423 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 424 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 425 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 426 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 427 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 428 #define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */
<> 153:fa9ff456f731 429 #define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 430 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 431 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 432 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 433 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 434 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 435 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 436 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 437 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 438 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 439 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 440 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 441 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 442 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */
<> 153:fa9ff456f731 443 #define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */
<> 153:fa9ff456f731 444 #define LDMA_CH_CTRL_DONEIFSEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set Enable */
<> 153:fa9ff456f731 445 #define _LDMA_CH_CTRL_DONEIFSEN_SHIFT 20 /**< Shift value for LDMA_DONEIFSEN */
<> 153:fa9ff456f731 446 #define _LDMA_CH_CTRL_DONEIFSEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIFSEN */
<> 153:fa9ff456f731 447 #define _LDMA_CH_CTRL_DONEIFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 448 #define LDMA_CH_CTRL_DONEIFSEN_DEFAULT (_LDMA_CH_CTRL_DONEIFSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 449 #define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */
<> 153:fa9ff456f731 450 #define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */
<> 153:fa9ff456f731 451 #define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */
<> 153:fa9ff456f731 452 #define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 453 #define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */
<> 153:fa9ff456f731 454 #define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */
<> 153:fa9ff456f731 455 #define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 456 #define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */
<> 153:fa9ff456f731 457 #define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */
<> 153:fa9ff456f731 458 #define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */
<> 153:fa9ff456f731 459 #define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */
<> 153:fa9ff456f731 460 #define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */
<> 153:fa9ff456f731 461 #define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 462 #define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 463 #define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */
<> 153:fa9ff456f731 464 #define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */
<> 153:fa9ff456f731 465 #define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */
<> 153:fa9ff456f731 466 #define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 467 #define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 468 #define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */
<> 153:fa9ff456f731 469 #define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */
<> 153:fa9ff456f731 470 #define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 471 #define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 472 #define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */
<> 153:fa9ff456f731 473 #define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */
<> 153:fa9ff456f731 474 #define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 475 #define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 476 #define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 477 #define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */
<> 153:fa9ff456f731 478 #define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */
<> 153:fa9ff456f731 479 #define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 480 #define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */
<> 153:fa9ff456f731 481 #define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */
<> 153:fa9ff456f731 482 #define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 483 #define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 484 #define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */
<> 153:fa9ff456f731 485 #define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */
<> 153:fa9ff456f731 486 #define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 487 #define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 488 #define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */
<> 153:fa9ff456f731 489 #define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */
<> 153:fa9ff456f731 490 #define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */
<> 153:fa9ff456f731 491 #define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */
<> 153:fa9ff456f731 492 #define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 493 #define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 494 #define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */
<> 153:fa9ff456f731 495 #define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */
<> 153:fa9ff456f731 496 #define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 497 #define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 498 #define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 499 #define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */
<> 153:fa9ff456f731 500 #define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */
<> 153:fa9ff456f731 501 #define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 502 #define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */
<> 153:fa9ff456f731 503 #define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */
<> 153:fa9ff456f731 504 #define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */
<> 153:fa9ff456f731 505 #define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 506 #define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 507 #define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 508 #define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 509 #define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 510 #define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 511 #define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */
<> 153:fa9ff456f731 512 #define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */
<> 153:fa9ff456f731 513 #define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */
<> 153:fa9ff456f731 514 #define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 515 #define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 516 #define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 517 #define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
<> 153:fa9ff456f731 518 #define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 519 #define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
<> 153:fa9ff456f731 520
<> 153:fa9ff456f731 521 /* Bit fields for LDMA CH_SRC */
<> 153:fa9ff456f731 522 #define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */
<> 153:fa9ff456f731 523 #define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */
<> 153:fa9ff456f731 524 #define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */
<> 153:fa9ff456f731 525 #define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */
<> 153:fa9ff456f731 526 #define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */
<> 153:fa9ff456f731 527 #define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */
<> 153:fa9ff456f731 528
<> 153:fa9ff456f731 529 /* Bit fields for LDMA CH_DST */
<> 153:fa9ff456f731 530 #define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */
<> 153:fa9ff456f731 531 #define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */
<> 153:fa9ff456f731 532 #define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */
<> 153:fa9ff456f731 533 #define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */
<> 153:fa9ff456f731 534 #define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */
<> 153:fa9ff456f731 535 #define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */
<> 153:fa9ff456f731 536
<> 153:fa9ff456f731 537 /* Bit fields for LDMA CH_LINK */
<> 153:fa9ff456f731 538 #define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */
<> 153:fa9ff456f731 539 #define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */
<> 153:fa9ff456f731 540 #define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */
<> 153:fa9ff456f731 541 #define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */
<> 153:fa9ff456f731 542 #define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */
<> 153:fa9ff456f731 543 #define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
<> 153:fa9ff456f731 544 #define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */
<> 153:fa9ff456f731 545 #define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */
<> 153:fa9ff456f731 546 #define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
<> 153:fa9ff456f731 547 #define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */
<> 153:fa9ff456f731 548 #define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */
<> 153:fa9ff456f731 549 #define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */
<> 153:fa9ff456f731 550 #define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */
<> 153:fa9ff456f731 551 #define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */
<> 153:fa9ff456f731 552 #define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
<> 153:fa9ff456f731 553 #define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
<> 153:fa9ff456f731 554 #define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */
<> 153:fa9ff456f731 555 #define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */
<> 153:fa9ff456f731 556 #define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
<> 153:fa9ff456f731 557 #define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
<> 153:fa9ff456f731 558
<> 153:fa9ff456f731 559 /** @} End of group EFR32MG1P_LDMA */
<> 153:fa9ff456f731 560 /** @} End of group Parts */
<> 153:fa9ff456f731 561