Diff: targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c

Revision:

178:79309dc6340a

Parent:

160:d5399cc887bb

--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c	Wed Nov 08 13:50:44 2017 +0000
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c	Thu Nov 23 11:57:25 2017 +0000
@@ -65,7 +65,6 @@
 /* See i2c.h for details */
 void fI2cInit(i2c_t *obj,PinName sda,PinName scl)
 {
-    uint32_t clockDivisor;
     /* determine the I2C to use */
     I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
     I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
@@ -93,9 +92,7 @@
     obj->membase->CR.BITS.I2C_APB_CD_EN = True;
 
     /* set default baud rate at 100k */
-    clockDivisor = ((fClockGetPeriphClockfrequency() / 100000) >> 2) - 2;
-    obj->membase->CR.BITS.CD_VAL = (clockDivisor & I2C_CLOCKDIVEDER_VAL_MASK);
-    obj->membase->PRE_SCALE_REG = (clockDivisor & I2C_APB_CLK_DIVIDER_VAL_MASK) >> 5; /**< Zero pre-scale value not allowed */
+    fI2cFrequency(obj, 100000);
 
     /* Cross bar setting */
     pinmap_pinout(sda, PinMap_I2C_SDA);
@@ -110,8 +107,8 @@
     PadReg_t *padRegScl = (PadReg_t*)(PADREG_BASE + (scl * PAD_REG_ADRS_BYTE_SIZE));
 
     CLOCK_ENABLE(CLOCK_PAD);
-    padRegSda->PADIO0.BITS.POWER = 1; /* sda: Drive strength */
-    padRegScl->PADIO0.BITS.POWER = 1; /* scl: Drive strength */
+    padRegSda->PADIO0.BITS.POWER = 3; /* sda: Drive strength */
+    padRegScl->PADIO0.BITS.POWER = 3; /* scl: Drive strength */
     CLOCK_DISABLE(CLOCK_PAD);
 
     CLOCK_ENABLE(CLOCK_GPIO);
@@ -160,7 +157,10 @@
     int32_t read = 0;
 
     while (read < len) {
-        /* Send read command */
+
+        while(FIFO_OFL_CHECK); /* Wait till command overflow ends */
+
+    	/* Send read command */
         SEND_COMMAND(I2C_CMD_RDAT8);
         while(!RD_DATA_READY) {
             if (I2C_BUS_ERR_CHECK) {
@@ -170,8 +170,8 @@
         }
         buf[read++] = obj->membase->RD_FIFO_REG; /**< Reading 'read FIFO register' will clear status register */
 
-        if(!(read>=len)) {  /* No ACK will be generated for the last read, upper level I2C protocol should generate */
-            SEND_COMMAND(I2C_CMD_WDAT0); /* TODO based on requirement generate ACK or NACK Based on the requirement. */
+        if(!(read>=len)) {
+            SEND_COMMAND(I2C_CMD_WDAT0);
         } else {
             /* No ack */
             SEND_COMMAND(I2C_CMD_WDAT1);
@@ -179,7 +179,7 @@
 
         /* check for FIFO underflow */
         if(I2C_UFL_CHECK) {
-            return I2C_ERROR_NO_SLAVE; /* TODO No error available for this in i2c_api.h */
+            return I2C_EVENT_ERROR;
         }
         if(I2C_BUS_ERR_CHECK) {
             /* Bus error */
@@ -196,8 +196,8 @@
     int32_t write = 0;
 
     while (write < len) {
-        /* Send write command */
-        SEND_COMMAND(I2C_CMD_WDAT8);
+
+        while(FIFO_OFL_CHECK); /* Wait till command overflow ends */
 
         if(buf[write] == I2C_CMD_RDAT8) {
             /* SW work around to counter FSM issue. If the only command in the CMD FIFO is the WDAT8 command (data of 0x13)
@@ -205,35 +205,27 @@
             RDAT8 command by the data FSM; resulting in an I2C bus error (NACK instead of an ACK). */
             /* Send 0x13 bit wise */
             SEND_COMMAND(I2C_CMD_WDAT0);
-
             SEND_COMMAND(I2C_CMD_WDAT0);
-
             SEND_COMMAND(I2C_CMD_WDAT0);
-
             SEND_COMMAND(I2C_CMD_WDAT1);
-
             SEND_COMMAND(I2C_CMD_WDAT0);
-
             SEND_COMMAND(I2C_CMD_WDAT0);
-
+            SEND_COMMAND(I2C_CMD_WDAT1);
             SEND_COMMAND(I2C_CMD_WDAT1);
-
-            SEND_COMMAND(I2C_CMD_WDAT1);
+            write++;
         } else {
             /* Send data */
+            SEND_COMMAND(I2C_CMD_WDAT8);
             SEND_COMMAND(buf[write++]);
         }
-        SEND_COMMAND(I2C_CMD_VRFY_ACK); /* TODO Verify ACK based on requirement, Do we need? */
+        SEND_COMMAND(I2C_CMD_VRFY_ACK);
 
         if (I2C_BUS_ERR_CHECK) {
             /* Bus error */
             return I2C_ERROR_BUS_BUSY;
         }
-
-        while(FIFO_OFL_CHECK); /* Wait till command overflow ends */
     }
-
     return write;
 }
 
-#endif /* DEVICE_I2C */
\ No newline at end of file
+#endif /* DEVICE_I2C */