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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.c@180:d79f997829d6, 2017-12-18 (annotated)

Committer:
Anythingconnected
Date:
Mon Dec 18 10:14:27 2017 +0000
Revision:
180:d79f997829d6
Parent:
165:e614a9f1c9e2 
Getting byte by byte read to work

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_dac_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 165:e614a9f1c9e2 5 * @version V1.1.0
AnnaBridge 165:e614a9f1c9e2 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief DAC HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of DAC extension peripheral:
<> 144:ef7eb2e8f9f7 10 * + Extended features functions
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
<> 144:ef7eb2e8f9f7 19 Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
<> 144:ef7eb2e8f9f7 20 HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
<> 144:ef7eb2e8f9f7 21 (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
<> 144:ef7eb2e8f9f7 22 (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 @endverbatim
<> 144:ef7eb2e8f9f7 25 ******************************************************************************
<> 144:ef7eb2e8f9f7 26 * @attention
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 29 *
<> 144:ef7eb2e8f9f7 30 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 31 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 32 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 33 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 34 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 35 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 36 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 37 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 38 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 39 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 40 *
<> 144:ef7eb2e8f9f7 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 44 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 48 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 51 *
<> 144:ef7eb2e8f9f7 52 ******************************************************************************
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /** @defgroup DACEx DACEx
<> 144:ef7eb2e8f9f7 64 * @brief DACEx driver module
<> 144:ef7eb2e8f9f7 65 * @{
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 #ifdef HAL_DAC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 69 #if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 72 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 73 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 74 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 75 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 76 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /** @defgroup DACEx_Exported_Functions DACEx Exported Functions
<> 144:ef7eb2e8f9f7 79 * @{
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
<> 144:ef7eb2e8f9f7 83 * @brief Extended features functions
<> 144:ef7eb2e8f9f7 84 *
<> 144:ef7eb2e8f9f7 85 @verbatim
<> 144:ef7eb2e8f9f7 86 ==============================================================================
<> 144:ef7eb2e8f9f7 87 ##### Extended features functions #####
<> 144:ef7eb2e8f9f7 88 ==============================================================================
<> 144:ef7eb2e8f9f7 89 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 90 (+) Start conversion.
<> 144:ef7eb2e8f9f7 91 (+) Stop conversion.
<> 144:ef7eb2e8f9f7 92 (+) Start conversion and enable DMA transfer.
<> 144:ef7eb2e8f9f7 93 (+) Stop conversion and disable DMA transfer.
<> 144:ef7eb2e8f9f7 94 (+) Get result of conversion.
<> 144:ef7eb2e8f9f7 95 (+) Get result of dual mode conversion.
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 @endverbatim
<> 144:ef7eb2e8f9f7 98 * @{
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /**
<> 144:ef7eb2e8f9f7 102 * @brief Returns the last data output value of the selected DAC channel.
<> 144:ef7eb2e8f9f7 103 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 104 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 105 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 108 {
AnnaBridge 165:e614a9f1c9e2 109 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 tmp |= hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 112
AnnaBridge 165:e614a9f1c9e2 113 tmp |= hdac->Instance->DOR2 << 16U;
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 116 return tmp;
<> 144:ef7eb2e8f9f7 117 }
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /**
<> 144:ef7eb2e8f9f7 120 * @brief Enables or disables the selected DAC channel wave generation.
<> 144:ef7eb2e8f9f7 121 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 122 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 123 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 124 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 125 * DAC_CHANNEL_1 / DAC_CHANNEL_2
<> 144:ef7eb2e8f9f7 126 * @param Amplitude: Select max triangle amplitude.
<> 144:ef7eb2e8f9f7 127 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 128 * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
<> 144:ef7eb2e8f9f7 129 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
<> 144:ef7eb2e8f9f7 130 * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
<> 144:ef7eb2e8f9f7 131 * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
<> 144:ef7eb2e8f9f7 132 * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
<> 144:ef7eb2e8f9f7 133 * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
<> 144:ef7eb2e8f9f7 134 * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
<> 144:ef7eb2e8f9f7 135 * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
<> 144:ef7eb2e8f9f7 136 * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
<> 144:ef7eb2e8f9f7 137 * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
<> 144:ef7eb2e8f9f7 138 * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
<> 144:ef7eb2e8f9f7 139 * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
<> 144:ef7eb2e8f9f7 140 * @retval HAL status
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
<> 144:ef7eb2e8f9f7 143 {
<> 144:ef7eb2e8f9f7 144 /* Check the parameters */
<> 144:ef7eb2e8f9f7 145 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 146 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /* Process locked */
<> 144:ef7eb2e8f9f7 149 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /* Change DAC state */
<> 144:ef7eb2e8f9f7 152 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /* Enable the selected wave generation for the selected DAC channel */
<> 144:ef7eb2e8f9f7 155 MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /* Change DAC state */
<> 144:ef7eb2e8f9f7 158 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Process unlocked */
<> 144:ef7eb2e8f9f7 161 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /* Return function status */
<> 144:ef7eb2e8f9f7 164 return HAL_OK;
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /**
<> 144:ef7eb2e8f9f7 168 * @brief Enables or disables the selected DAC channel wave generation.
<> 144:ef7eb2e8f9f7 169 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 170 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 171 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 172 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 173 * DAC_CHANNEL_1 / DAC_CHANNEL_2
<> 144:ef7eb2e8f9f7 174 * @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
<> 144:ef7eb2e8f9f7 175 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 176 * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
<> 144:ef7eb2e8f9f7 177 * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
<> 144:ef7eb2e8f9f7 178 * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
<> 144:ef7eb2e8f9f7 179 * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
<> 144:ef7eb2e8f9f7 180 * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
<> 144:ef7eb2e8f9f7 181 * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
<> 144:ef7eb2e8f9f7 182 * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
<> 144:ef7eb2e8f9f7 183 * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
<> 144:ef7eb2e8f9f7 184 * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
<> 144:ef7eb2e8f9f7 185 * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
<> 144:ef7eb2e8f9f7 186 * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
<> 144:ef7eb2e8f9f7 187 * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
<> 144:ef7eb2e8f9f7 188 * @retval HAL status
<> 144:ef7eb2e8f9f7 189 */
<> 144:ef7eb2e8f9f7 190 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 /* Check the parameters */
<> 144:ef7eb2e8f9f7 193 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 194 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /* Process locked */
<> 144:ef7eb2e8f9f7 197 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /* Change DAC state */
<> 144:ef7eb2e8f9f7 200 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /* Enable the selected wave generation for the selected DAC channel */
<> 144:ef7eb2e8f9f7 203 MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /* Change DAC state */
<> 144:ef7eb2e8f9f7 206 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Process unlocked */
<> 144:ef7eb2e8f9f7 209 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /* Return function status */
<> 144:ef7eb2e8f9f7 212 return HAL_OK;
<> 144:ef7eb2e8f9f7 213 }
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /**
<> 144:ef7eb2e8f9f7 216 * @brief Set the specified data holding register value for dual DAC channel.
<> 144:ef7eb2e8f9f7 217 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 218 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 219 * @param Alignment: Specifies the data alignment for dual channel DAC.
<> 144:ef7eb2e8f9f7 220 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 221 * DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 222 * DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 223 * DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 224 * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 225 * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 226 * @note In dual mode, a unique register access is required to write in both
<> 144:ef7eb2e8f9f7 227 * DAC channels at the same time.
<> 144:ef7eb2e8f9f7 228 * @retval HAL status
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
<> 144:ef7eb2e8f9f7 231 {
AnnaBridge 165:e614a9f1c9e2 232 uint32_t data = 0U, tmp = 0U;
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /* Check the parameters */
<> 144:ef7eb2e8f9f7 235 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 236 assert_param(IS_DAC_DATA(Data1));
<> 144:ef7eb2e8f9f7 237 assert_param(IS_DAC_DATA(Data2));
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /* Calculate and set dual DAC data holding register value */
<> 144:ef7eb2e8f9f7 240 if (Alignment == DAC_ALIGN_8B_R)
<> 144:ef7eb2e8f9f7 241 {
AnnaBridge 165:e614a9f1c9e2 242 data = ((uint32_t)Data2 << 8U) | Data1;
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244 else
<> 144:ef7eb2e8f9f7 245 {
AnnaBridge 165:e614a9f1c9e2 246 data = ((uint32_t)Data2 << 16U) | Data1;
<> 144:ef7eb2e8f9f7 247 }
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 tmp = (uint32_t)hdac->Instance;
<> 144:ef7eb2e8f9f7 250 tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /* Set the dual DAC selected data holding register */
<> 144:ef7eb2e8f9f7 253 *(__IO uint32_t *)tmp = data;
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* Return function status */
<> 144:ef7eb2e8f9f7 256 return HAL_OK;
<> 144:ef7eb2e8f9f7 257 }
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /**
<> 144:ef7eb2e8f9f7 260 * @brief Conversion complete callback in non blocking mode for Channel2
<> 144:ef7eb2e8f9f7 261 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 262 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 263 * @retval None
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 268 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 269 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 270 the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @brief Conversion half DMA transfer callback in non blocking mode for Channel2
<> 144:ef7eb2e8f9f7 276 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 277 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 278 * @retval None
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 283 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 284 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 285 the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /**
<> 144:ef7eb2e8f9f7 290 * @brief Error DAC callback for Channel2.
<> 144:ef7eb2e8f9f7 291 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 292 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 293 * @retval None
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 296 {
<> 144:ef7eb2e8f9f7 297 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 298 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 299 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 300 the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302 }
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 #if defined (STM32F100xB) || defined (STM32F100xE)
<> 144:ef7eb2e8f9f7 305 /**
<> 144:ef7eb2e8f9f7 306 * @brief DMA underrun DAC callback for channel1.
<> 144:ef7eb2e8f9f7 307 * Note: For STM32F100x devices with specific feature: DMA underrun.
<> 144:ef7eb2e8f9f7 308 * On these devices, this function uses the interruption of DMA
<> 144:ef7eb2e8f9f7 309 * underrun.
<> 144:ef7eb2e8f9f7 310 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 311 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 312 * @retval None
<> 144:ef7eb2e8f9f7 313 */
<> 144:ef7eb2e8f9f7 314 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 315 {
<> 144:ef7eb2e8f9f7 316 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 317 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 318 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 319 the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321 }
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /**
<> 144:ef7eb2e8f9f7 324 * @brief DMA underrun DAC callback for channel2.
<> 144:ef7eb2e8f9f7 325 * Note: For STM32F100x devices with specific feature: DMA underrun.
<> 144:ef7eb2e8f9f7 326 * On these devices, this function uses the interruption of DMA
<> 144:ef7eb2e8f9f7 327 * underrun.
<> 144:ef7eb2e8f9f7 328 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 329 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 330 * @retval None
<> 144:ef7eb2e8f9f7 331 */
<> 144:ef7eb2e8f9f7 332 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 333 {
<> 144:ef7eb2e8f9f7 334 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 335 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 336 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 337 the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339 }
<> 144:ef7eb2e8f9f7 340 #endif /* STM32F100xB) || defined (STM32F100xE) */
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /**
<> 144:ef7eb2e8f9f7 343 * @}
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 #if defined (STM32F100xB) || defined (STM32F100xE)
<> 144:ef7eb2e8f9f7 347 /**
<> 144:ef7eb2e8f9f7 348 * @brief Enables DAC and starts conversion of channel.
<> 144:ef7eb2e8f9f7 349 * Note: For STM32F100x devices with specific feature: DMA underrun.
<> 144:ef7eb2e8f9f7 350 * On these devices, this function enables the interruption of DMA
<> 144:ef7eb2e8f9f7 351 * underrun.
<> 144:ef7eb2e8f9f7 352 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 353 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 354 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 355 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 356 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 357 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 358 * @param pData: The destination peripheral Buffer address.
<> 144:ef7eb2e8f9f7 359 * @param Length: The length of data to be transferred from memory to DAC peripheral
<> 144:ef7eb2e8f9f7 360 * @param Alignment: Specifies the data alignment for DAC channel.
<> 144:ef7eb2e8f9f7 361 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 362 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 363 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 364 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 365 * @retval HAL status
<> 144:ef7eb2e8f9f7 366 */
<> 144:ef7eb2e8f9f7 367 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
<> 144:ef7eb2e8f9f7 368 {
AnnaBridge 165:e614a9f1c9e2 369 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /* Check the parameters */
<> 144:ef7eb2e8f9f7 372 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 373 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* Process locked */
<> 144:ef7eb2e8f9f7 376 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /* Change DAC state */
<> 144:ef7eb2e8f9f7 379 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 382 {
<> 144:ef7eb2e8f9f7 383 /* Set the DMA transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 384 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /* Set the DMA half transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 387 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /* Set the DMA error callback for channel1 */
<> 144:ef7eb2e8f9f7 390 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /* Enable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 393 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /* Case of use of channel 1 */
<> 144:ef7eb2e8f9f7 396 switch(Alignment)
<> 144:ef7eb2e8f9f7 397 {
<> 144:ef7eb2e8f9f7 398 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 399 /* Get DHR12R1 address */
<> 144:ef7eb2e8f9f7 400 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
<> 144:ef7eb2e8f9f7 401 break;
<> 144:ef7eb2e8f9f7 402 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 403 /* Get DHR12L1 address */
<> 144:ef7eb2e8f9f7 404 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
<> 144:ef7eb2e8f9f7 405 break;
<> 144:ef7eb2e8f9f7 406 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 407 /* Get DHR8R1 address */
<> 144:ef7eb2e8f9f7 408 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
<> 144:ef7eb2e8f9f7 409 break;
<> 144:ef7eb2e8f9f7 410 default:
<> 144:ef7eb2e8f9f7 411 break;
<> 144:ef7eb2e8f9f7 412 }
<> 144:ef7eb2e8f9f7 413 }
<> 144:ef7eb2e8f9f7 414 else
<> 144:ef7eb2e8f9f7 415 {
<> 144:ef7eb2e8f9f7 416 /* Set the DMA transfer complete callback for channel2 */
<> 144:ef7eb2e8f9f7 417 hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Set the DMA half transfer complete callback for channel2 */
<> 144:ef7eb2e8f9f7 420 hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* Set the DMA error callback for channel2 */
<> 144:ef7eb2e8f9f7 423 hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Enable the selected DAC channel2 DMA request */
<> 144:ef7eb2e8f9f7 426 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /* Case of use of channel 2 */
<> 144:ef7eb2e8f9f7 429 switch(Alignment)
<> 144:ef7eb2e8f9f7 430 {
<> 144:ef7eb2e8f9f7 431 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 432 /* Get DHR12R2 address */
<> 144:ef7eb2e8f9f7 433 tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
<> 144:ef7eb2e8f9f7 434 break;
<> 144:ef7eb2e8f9f7 435 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 436 /* Get DHR12L2 address */
<> 144:ef7eb2e8f9f7 437 tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
<> 144:ef7eb2e8f9f7 438 break;
<> 144:ef7eb2e8f9f7 439 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 440 /* Get DHR8R2 address */
<> 144:ef7eb2e8f9f7 441 tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
<> 144:ef7eb2e8f9f7 442 break;
<> 144:ef7eb2e8f9f7 443 default:
<> 144:ef7eb2e8f9f7 444 break;
<> 144:ef7eb2e8f9f7 445 }
<> 144:ef7eb2e8f9f7 446 }
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 449 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 450 {
<> 144:ef7eb2e8f9f7 451 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 452 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 455 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 456 }
<> 144:ef7eb2e8f9f7 457 else
<> 144:ef7eb2e8f9f7 458 {
<> 144:ef7eb2e8f9f7 459 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 460 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 463 HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 464 }
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 467 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 470 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /* Return function status */
<> 144:ef7eb2e8f9f7 473 return HAL_OK;
<> 144:ef7eb2e8f9f7 474 }
<> 144:ef7eb2e8f9f7 475 #endif /* STM32F100xB) || defined (STM32F100xE) */
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 #if defined (STM32F100xB) || defined (STM32F100xE)
<> 144:ef7eb2e8f9f7 478 /**
<> 144:ef7eb2e8f9f7 479 * @brief Disables DAC and stop conversion of channel.
<> 144:ef7eb2e8f9f7 480 * Note: For STM32F100x devices with specific feature: DMA underrun.
<> 144:ef7eb2e8f9f7 481 * On these devices, this function disables the interruption of DMA
<> 144:ef7eb2e8f9f7 482 * underrun.
<> 144:ef7eb2e8f9f7 483 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 484 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 485 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 486 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 487 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 488 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 489 * @retval HAL status
<> 144:ef7eb2e8f9f7 490 */
<> 144:ef7eb2e8f9f7 491 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 492 {
<> 144:ef7eb2e8f9f7 493 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /* Check the parameters */
<> 144:ef7eb2e8f9f7 496 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 /* Disable the selected DAC channel DMA request */
<> 144:ef7eb2e8f9f7 499 hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /* Disable the Peripharal */
<> 144:ef7eb2e8f9f7 502 __HAL_DAC_DISABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /* Disable the DMA Channel */
<> 144:ef7eb2e8f9f7 505 /* Channel1 is used */
<> 144:ef7eb2e8f9f7 506 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 507 {
<> 144:ef7eb2e8f9f7 508 /* Disable the DMA channel */
<> 144:ef7eb2e8f9f7 509 status = HAL_DMA_Abort(hdac->DMA_Handle1);
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /* Disable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 512 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
<> 144:ef7eb2e8f9f7 513 }
<> 144:ef7eb2e8f9f7 514 else /* Channel2 is used for */
<> 144:ef7eb2e8f9f7 515 {
<> 144:ef7eb2e8f9f7 516 /* Disable the DMA channel */
<> 144:ef7eb2e8f9f7 517 status = HAL_DMA_Abort(hdac->DMA_Handle2);
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /* Disable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 520 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
<> 144:ef7eb2e8f9f7 521 }
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /* Check if DMA Channel effectively disabled */
<> 144:ef7eb2e8f9f7 524 if(status != HAL_OK)
<> 144:ef7eb2e8f9f7 525 {
<> 144:ef7eb2e8f9f7 526 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 527 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 528 }
<> 144:ef7eb2e8f9f7 529 else
<> 144:ef7eb2e8f9f7 530 {
<> 144:ef7eb2e8f9f7 531 /* Change DAC state */
<> 144:ef7eb2e8f9f7 532 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 533 }
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /* Return function status */
<> 144:ef7eb2e8f9f7 536 return status;
<> 144:ef7eb2e8f9f7 537 }
<> 144:ef7eb2e8f9f7 538 #endif /* STM32F100xB) || defined (STM32F100xE) */
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 #if defined (STM32F100xB) || defined (STM32F100xE)
<> 144:ef7eb2e8f9f7 541 /**
<> 144:ef7eb2e8f9f7 542 * @brief Handles DAC interrupt request
<> 144:ef7eb2e8f9f7 543 * Note: For STM32F100x devices with specific feature: DMA underrun.
<> 144:ef7eb2e8f9f7 544 * On these devices, this function uses the interruption of DMA
<> 144:ef7eb2e8f9f7 545 * underrun.
<> 144:ef7eb2e8f9f7 546 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 547 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 548 * @retval None
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 551 {
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
<> 144:ef7eb2e8f9f7 554 {
<> 144:ef7eb2e8f9f7 555 /* Check underrun flag of DAC channel 1 */
<> 144:ef7eb2e8f9f7 556 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 /* Change DAC state to error state */
<> 144:ef7eb2e8f9f7 559 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /* Set DAC error code to chanel1 DMA underrun error */
<> 144:ef7eb2e8f9f7 562 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 /* Clear the underrun flag */
<> 144:ef7eb2e8f9f7 565 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /* Disable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 568 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /* Error callback */
<> 144:ef7eb2e8f9f7 571 HAL_DAC_DMAUnderrunCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 572 }
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
<> 144:ef7eb2e8f9f7 576 {
<> 144:ef7eb2e8f9f7 577 /* Check underrun flag of DAC channel 2 */
<> 144:ef7eb2e8f9f7 578 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
<> 144:ef7eb2e8f9f7 579 {
<> 144:ef7eb2e8f9f7 580 /* Change DAC state to error state */
<> 144:ef7eb2e8f9f7 581 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 /* Set DAC error code to channel2 DMA underrun error */
<> 144:ef7eb2e8f9f7 584 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /* Clear the underrun flag */
<> 144:ef7eb2e8f9f7 587 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /* Disable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 590 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /* Error callback */
<> 144:ef7eb2e8f9f7 593 HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 594 }
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596 }
<> 144:ef7eb2e8f9f7 597 #endif /* STM32F100xB || STM32F100xE */
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /**
<> 144:ef7eb2e8f9f7 601 * @}
<> 144:ef7eb2e8f9f7 602 */
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /** @defgroup DACEx_Private_Functions DACEx Private Functions
<> 144:ef7eb2e8f9f7 605 * @{
<> 144:ef7eb2e8f9f7 606 */
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /**
<> 144:ef7eb2e8f9f7 609 * @brief DMA conversion complete callback.
<> 144:ef7eb2e8f9f7 610 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 611 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 612 * @retval None
<> 144:ef7eb2e8f9f7 613 */
<> 144:ef7eb2e8f9f7 614 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 615 {
<> 144:ef7eb2e8f9f7 616 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 HAL_DACEx_ConvCpltCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 621 }
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /**
<> 144:ef7eb2e8f9f7 624 * @brief DMA half transfer complete callback.
<> 144:ef7eb2e8f9f7 625 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 626 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 627 * @retval None
<> 144:ef7eb2e8f9f7 628 */
<> 144:ef7eb2e8f9f7 629 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 630 {
<> 144:ef7eb2e8f9f7 631 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 632 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 633 HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 634 }
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /**
<> 144:ef7eb2e8f9f7 637 * @brief DMA error callback
<> 144:ef7eb2e8f9f7 638 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 639 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 640 * @retval None
<> 144:ef7eb2e8f9f7 641 */
<> 144:ef7eb2e8f9f7 642 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 643 {
<> 144:ef7eb2e8f9f7 644 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /* Set DAC error code to DMA error */
<> 144:ef7eb2e8f9f7 647 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 HAL_DACEx_ErrorCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 652 }
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 /**
<> 144:ef7eb2e8f9f7 655 * @}
<> 144:ef7eb2e8f9f7 656 */
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 #endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 659 #endif /* HAL_DAC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /**
<> 144:ef7eb2e8f9f7 662 * @}
<> 144:ef7eb2e8f9f7 663 */
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 /**
<> 144:ef7eb2e8f9f7 666 * @}
<> 144:ef7eb2e8f9f7 667 */
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/