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mbed library sources. Supersedes mbed-src.

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targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c@180:d79f997829d6, 2017-12-18 (annotated)

Committer:
Anythingconnected
Date:
Mon Dec 18 10:14:27 2017 +0000
Revision:
180:d79f997829d6
Parent:
174:b96e65c34a4d 
Getting byte by byte read to work

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 * Copyright (c) 2015-2016 Nuvoton
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 149:156823d33999 5 * you may not use this file except in compliance with the License.
<> 149:156823d33999 6 * You may obtain a copy of the License at
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 149:156823d33999 9 *
<> 149:156823d33999 10 * Unless required by applicable law or agreed to in writing, software
<> 149:156823d33999 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 149:156823d33999 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 149:156823d33999 13 * See the License for the specific language governing permissions and
<> 149:156823d33999 14 * limitations under the License.
<> 149:156823d33999 15 */
<> 149:156823d33999 16
<> 149:156823d33999 17 #include "lp_ticker_api.h"
<> 149:156823d33999 18
<> 149:156823d33999 19 #if DEVICE_LOWPOWERTIMER
<> 149:156823d33999 20
<> 149:156823d33999 21 #include "sleep_api.h"
<> 149:156823d33999 22 #include "nu_modutil.h"
<> 149:156823d33999 23 #include "nu_miscutil.h"
<> 160:d5399cc887bb 24 #include "mbed_critical.h"
<> 149:156823d33999 25
<> 149:156823d33999 26 // lp_ticker tick = us = timestamp
<> 149:156823d33999 27 #define US_PER_TICK (1)
<> 149:156823d33999 28 #define US_PER_SEC (1000 * 1000)
<> 149:156823d33999 29
<> 149:156823d33999 30 #define US_PER_TMR2_INT (US_PER_SEC * 10)
<> 149:156823d33999 31 #define TMR2_CLK_PER_SEC (__LXT)
<> 149:156823d33999 32 #define TMR2_CLK_PER_TMR2_INT ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC))
<> 149:156823d33999 33 #define TMR3_CLK_PER_SEC (__LXT)
<> 149:156823d33999 34
<> 149:156823d33999 35 static void tmr2_vec(void);
<> 149:156823d33999 36 static void tmr3_vec(void);
<> 149:156823d33999 37 static void lp_ticker_arm_cd(void);
<> 149:156823d33999 38
<> 149:156823d33999 39 static int lp_ticker_inited = 0;
<> 149:156823d33999 40 static volatile uint32_t counter_major = 0;
<> 149:156823d33999 41 static volatile uint32_t cd_major_minor_clks = 0;
<> 149:156823d33999 42 static volatile uint32_t cd_minor_clks = 0;
<> 149:156823d33999 43 static volatile uint32_t wakeup_tick = (uint32_t) -1;
<> 149:156823d33999 44
<> 149:156823d33999 45 // NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
<> 149:156823d33999 46 // NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled wakeup
<> 149:156823d33999 47 static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) tmr2_vec};
<> 149:156823d33999 48 static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) tmr3_vec};
<> 149:156823d33999 49
<> 149:156823d33999 50 #define TMR_CMP_MIN 2
<> 149:156823d33999 51 #define TMR_CMP_MAX 0xFFFFFFu
<> 149:156823d33999 52
<> 149:156823d33999 53 void lp_ticker_init(void)
<> 149:156823d33999 54 {
<> 149:156823d33999 55 if (lp_ticker_inited) {
<> 149:156823d33999 56 return;
<> 149:156823d33999 57 }
<> 149:156823d33999 58 lp_ticker_inited = 1;
<> 149:156823d33999 59
<> 149:156823d33999 60 counter_major = 0;
<> 149:156823d33999 61 cd_major_minor_clks = 0;
<> 149:156823d33999 62 cd_minor_clks = 0;
<> 149:156823d33999 63 wakeup_tick = (uint32_t) -1;
<> 149:156823d33999 64
<> 149:156823d33999 65 // Reset module
<> 149:156823d33999 66 SYS_ResetModule(timer2_modinit.rsetidx);
<> 149:156823d33999 67 SYS_ResetModule(timer3_modinit.rsetidx);
<> 149:156823d33999 68
<> 149:156823d33999 69 // Select IP clock source
<> 149:156823d33999 70 CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);
<> 149:156823d33999 71 CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);
<> 149:156823d33999 72 // Enable IP clock
<> 149:156823d33999 73 CLK_EnableModuleClock(timer2_modinit.clkidx);
<> 149:156823d33999 74 CLK_EnableModuleClock(timer3_modinit.clkidx);
<> 149:156823d33999 75
<> 149:156823d33999 76 // Configure clock
<> 149:156823d33999 77 uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
<> 149:156823d33999 78 uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
<> 149:156823d33999 79 MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
<> 149:156823d33999 80 MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
<> 149:156823d33999 81 uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
<> 149:156823d33999 82 MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
<> 149:156823d33999 83 // Continuous mode
<> 149:156823d33999 84 // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
<> 149:156823d33999 85 ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2/* | TIMER_CTL_CNTDATEN_Msk*/;
<> 149:156823d33999 86 ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2;
<> 149:156823d33999 87
<> 149:156823d33999 88 // Set vector
<> 149:156823d33999 89 NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);
<> 149:156823d33999 90 NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);
<> 149:156823d33999 91
<> 149:156823d33999 92 NVIC_EnableIRQ(timer2_modinit.irq_n);
<> 149:156823d33999 93 NVIC_EnableIRQ(timer3_modinit.irq_n);
<> 149:156823d33999 94
<> 149:156823d33999 95 TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
<> 149:156823d33999 96 TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
<> 149:156823d33999 97
<> 153:fa9ff456f731 98 // NOTE: TIMER_Start() first and then lp_ticker_set_interrupt(); otherwise, we may get stuck in lp_ticker_read() because
<> 153:fa9ff456f731 99 // timer is not running.
<> 149:156823d33999 100
<> 149:156823d33999 101 // Start timer
<> 149:156823d33999 102 TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
<> 153:fa9ff456f731 103
<> 153:fa9ff456f731 104 // Schedule wakeup to match semantics of lp_ticker_get_compare_match()
<> 153:fa9ff456f731 105 lp_ticker_set_interrupt(wakeup_tick);
<> 149:156823d33999 106 }
<> 149:156823d33999 107
<> 149:156823d33999 108 timestamp_t lp_ticker_read()
<> 149:156823d33999 109 {
<> 149:156823d33999 110 if (! lp_ticker_inited) {
<> 149:156823d33999 111 lp_ticker_init();
<> 149:156823d33999 112 }
<> 149:156823d33999 113
<> 149:156823d33999 114 TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
<> 149:156823d33999 115
<> 149:156823d33999 116 do {
<> 149:156823d33999 117 uint64_t major_minor_clks;
<> 149:156823d33999 118 uint32_t minor_clks;
<> 149:156823d33999 119
<> 149:156823d33999 120 // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
<> 149:156823d33999 121 // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
<> 149:156823d33999 122 do {
<> 149:156823d33999 123 core_util_critical_section_enter();
<> 149:156823d33999 124
<> 149:156823d33999 125 // NOTE: Order of reading minor_us/carry here is significant.
<> 149:156823d33999 126 minor_clks = TIMER_GetCounter(timer2_base);
<> 149:156823d33999 127 uint32_t carry = (timer2_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
<> 149:156823d33999 128 // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
<> 149:156823d33999 129 if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
<> 149:156823d33999 130 major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
<> 149:156823d33999 131 }
<> 149:156823d33999 132 else {
<> 149:156823d33999 133 major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
<> 149:156823d33999 134 }
<> 149:156823d33999 135
<> 149:156823d33999 136 core_util_critical_section_exit();
<> 149:156823d33999 137 }
<> 149:156823d33999 138 while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
<> 149:156823d33999 139
<> 149:156823d33999 140 // Add power-down compensation
AnnaBridge 172:7d866c31b3c5 141 return ((uint64_t) major_minor_clks * US_PER_SEC / TMR2_CLK_PER_SEC / US_PER_TICK);
<> 149:156823d33999 142 }
<> 149:156823d33999 143 while (0);
<> 149:156823d33999 144 }
<> 149:156823d33999 145
<> 149:156823d33999 146 void lp_ticker_set_interrupt(timestamp_t timestamp)
<> 149:156823d33999 147 {
AnnaBridge 174:b96e65c34a4d 148 uint32_t delta = timestamp - lp_ticker_read();
<> 149:156823d33999 149 wakeup_tick = timestamp;
<> 149:156823d33999 150
<> 149:156823d33999 151 TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
<> 149:156823d33999 152
AnnaBridge 174:b96e65c34a4d 153 cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
AnnaBridge 174:b96e65c34a4d 154 lp_ticker_arm_cd();
AnnaBridge 174:b96e65c34a4d 155 }
AnnaBridge 174:b96e65c34a4d 156
AnnaBridge 174:b96e65c34a4d 157 void lp_ticker_fire_interrupt(void)
AnnaBridge 174:b96e65c34a4d 158 {
AnnaBridge 174:b96e65c34a4d 159 cd_major_minor_clks = cd_minor_clks = 0;
<> 149:156823d33999 160 /**
AnnaBridge 174:b96e65c34a4d 161 * This event was in the past. Set the interrupt as pending, but don't process it here.
AnnaBridge 174:b96e65c34a4d 162 * This prevents a recurive loop under heavy load which can lead to a stack overflow.
AnnaBridge 174:b96e65c34a4d 163 */
AnnaBridge 174:b96e65c34a4d 164 NVIC_SetPendingIRQ(timer3_modinit.irq_n);
<> 149:156823d33999 165 }
<> 149:156823d33999 166
<> 149:156823d33999 167 void lp_ticker_disable_interrupt(void)
<> 149:156823d33999 168 {
<> 149:156823d33999 169 TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
<> 149:156823d33999 170 }
<> 149:156823d33999 171
<> 149:156823d33999 172 void lp_ticker_clear_interrupt(void)
<> 149:156823d33999 173 {
<> 149:156823d33999 174 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
<> 149:156823d33999 175 }
<> 149:156823d33999 176
<> 149:156823d33999 177 static void tmr2_vec(void)
<> 149:156823d33999 178 {
<> 149:156823d33999 179 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
<> 149:156823d33999 180 TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
<> 149:156823d33999 181 counter_major ++;
<> 149:156823d33999 182 }
<> 149:156823d33999 183
<> 149:156823d33999 184 static void tmr3_vec(void)
<> 149:156823d33999 185 {
<> 149:156823d33999 186 TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
<> 149:156823d33999 187 TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
<> 149:156823d33999 188 cd_major_minor_clks = (cd_major_minor_clks > cd_minor_clks) ? (cd_major_minor_clks - cd_minor_clks) : 0;
<> 149:156823d33999 189 if (cd_major_minor_clks == 0) {
<> 149:156823d33999 190 // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
<> 149:156823d33999 191 lp_ticker_irq_handler();
<> 149:156823d33999 192 }
<> 149:156823d33999 193 else {
<> 149:156823d33999 194 lp_ticker_arm_cd();
<> 149:156823d33999 195 }
<> 149:156823d33999 196 }
<> 149:156823d33999 197
<> 149:156823d33999 198 static void lp_ticker_arm_cd(void)
<> 149:156823d33999 199 {
<> 149:156823d33999 200 TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname);
<> 149:156823d33999 201
<> 149:156823d33999 202 // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
<> 149:156823d33999 203 timer3_base->CTL |= TIMER_CTL_RSTCNT_Msk;
<> 149:156823d33999 204 // One-shot mode, Clock = 1 KHz
<> 149:156823d33999 205 uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
<> 149:156823d33999 206 uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1;
<> 149:156823d33999 207 MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
<> 149:156823d33999 208 MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0);
<> 149:156823d33999 209 // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
<> 149:156823d33999 210 timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
<> 149:156823d33999 211 timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3/* | TIMER_CTL_CNTDATEN_Msk*/;
<> 149:156823d33999 212
<> 149:156823d33999 213 cd_minor_clks = cd_major_minor_clks;
<> 149:156823d33999 214 cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX);
<> 149:156823d33999 215 timer3_base->CMP = cd_minor_clks;
<> 149:156823d33999 216
<> 149:156823d33999 217 TIMER_EnableInt(timer3_base);
<> 149:156823d33999 218 TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
<> 149:156823d33999 219 TIMER_Start(timer3_base);
<> 149:156823d33999 220 }
<> 149:156823d33999 221 #endif