mbed library sources. Supersedes mbed-src.
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targets/TARGET_Freescale/TARGET_KLXX/clk_freqs.h@180:d79f997829d6, 2017-12-18 (annotated)
- Committer:
- Anythingconnected
- Date:
- Mon Dec 18 10:14:27 2017 +0000
- Revision:
- 180:d79f997829d6
- Parent:
- 149:156823d33999
Getting byte by byte read to work
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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<> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2006-2013 ARM Limited |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 144:ef7eb2e8f9f7 | 5 | * you may not use this file except in compliance with the License. |
<> | 144:ef7eb2e8f9f7 | 6 | * You may obtain a copy of the License at |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 144:ef7eb2e8f9f7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 144:ef7eb2e8f9f7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 144:ef7eb2e8f9f7 | 13 | * See the License for the specific language governing permissions and |
<> | 144:ef7eb2e8f9f7 | 14 | * limitations under the License. |
<> | 144:ef7eb2e8f9f7 | 15 | */ |
<> | 144:ef7eb2e8f9f7 | 16 | #ifndef MBED_CLK_FREQS_H |
<> | 144:ef7eb2e8f9f7 | 17 | #define MBED_CLK_FREQS_H |
<> | 144:ef7eb2e8f9f7 | 18 | |
<> | 144:ef7eb2e8f9f7 | 19 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 20 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 21 | #endif |
<> | 144:ef7eb2e8f9f7 | 22 | |
<> | 144:ef7eb2e8f9f7 | 23 | #include "PeripheralPins.h" |
<> | 144:ef7eb2e8f9f7 | 24 | |
<> | 144:ef7eb2e8f9f7 | 25 | //Get the peripheral bus clock frequency |
<> | 144:ef7eb2e8f9f7 | 26 | static inline uint32_t bus_frequency(void) { |
<> | 144:ef7eb2e8f9f7 | 27 | return (SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1)); |
<> | 144:ef7eb2e8f9f7 | 28 | } |
<> | 144:ef7eb2e8f9f7 | 29 | |
<> | 144:ef7eb2e8f9f7 | 30 | #if defined(TARGET_KL43Z) |
<> | 144:ef7eb2e8f9f7 | 31 | |
<> | 144:ef7eb2e8f9f7 | 32 | static inline uint32_t extosc_frequency(void) { |
<> | 144:ef7eb2e8f9f7 | 33 | return CPU_XTAL_CLK_HZ; |
<> | 144:ef7eb2e8f9f7 | 34 | } |
<> | 144:ef7eb2e8f9f7 | 35 | |
<> | 144:ef7eb2e8f9f7 | 36 | static inline uint32_t fastirc_frequency(void) { |
<> | 144:ef7eb2e8f9f7 | 37 | return CPU_INT_FAST_CLK_HZ; |
<> | 144:ef7eb2e8f9f7 | 38 | } |
<> | 144:ef7eb2e8f9f7 | 39 | |
<> | 144:ef7eb2e8f9f7 | 40 | static inline uint32_t mcgirc_frequency(void) { |
<> | 144:ef7eb2e8f9f7 | 41 | uint32_t mcgirc_clock = 0; |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | if (MCG->C1 & MCG_C1_IREFSTEN_MASK) { |
<> | 144:ef7eb2e8f9f7 | 44 | mcgirc_clock = (MCG->C2 & MCG_C2_IRCS_MASK) ? 8000000u : 2000000u; |
<> | 144:ef7eb2e8f9f7 | 45 | mcgirc_clock /= 1u + ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT); |
<> | 144:ef7eb2e8f9f7 | 46 | mcgirc_clock /= 1u + (MCG->MC & MCG_MC_LIRC_DIV2_MASK); |
<> | 144:ef7eb2e8f9f7 | 47 | } |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | return mcgirc_clock; |
<> | 144:ef7eb2e8f9f7 | 50 | } |
<> | 144:ef7eb2e8f9f7 | 51 | |
<> | 144:ef7eb2e8f9f7 | 52 | #else |
<> | 144:ef7eb2e8f9f7 | 53 | |
<> | 144:ef7eb2e8f9f7 | 54 | //Get external oscillator (crystal) frequency |
<> | 144:ef7eb2e8f9f7 | 55 | static uint32_t extosc_frequency(void) { |
<> | 144:ef7eb2e8f9f7 | 56 | uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 57 | |
<> | 144:ef7eb2e8f9f7 | 58 | if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock |
<> | 144:ef7eb2e8f9f7 | 59 | return MCGClock; |
<> | 144:ef7eb2e8f9f7 | 60 | |
<> | 144:ef7eb2e8f9f7 | 61 | uint32_t divider, multiplier; |
<> | 144:ef7eb2e8f9f7 | 62 | #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available |
<> | 144:ef7eb2e8f9f7 | 63 | if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected |
<> | 144:ef7eb2e8f9f7 | 64 | if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected |
<> | 144:ef7eb2e8f9f7 | 65 | #endif |
<> | 144:ef7eb2e8f9f7 | 66 | if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference |
<> | 144:ef7eb2e8f9f7 | 67 | divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 68 | if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) |
<> | 144:ef7eb2e8f9f7 | 69 | divider <<= 5u; |
<> | 144:ef7eb2e8f9f7 | 70 | /* Select correct multiplier to calculate the MCG output clock */ |
<> | 144:ef7eb2e8f9f7 | 71 | switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { |
<> | 144:ef7eb2e8f9f7 | 72 | case 0x0u: |
<> | 144:ef7eb2e8f9f7 | 73 | multiplier = 640u; |
<> | 144:ef7eb2e8f9f7 | 74 | break; |
<> | 144:ef7eb2e8f9f7 | 75 | case 0x20u: |
<> | 144:ef7eb2e8f9f7 | 76 | multiplier = 1280u; |
<> | 144:ef7eb2e8f9f7 | 77 | break; |
<> | 144:ef7eb2e8f9f7 | 78 | case 0x40u: |
<> | 144:ef7eb2e8f9f7 | 79 | multiplier = 1920u; |
<> | 144:ef7eb2e8f9f7 | 80 | break; |
<> | 144:ef7eb2e8f9f7 | 81 | case 0x60u: |
<> | 144:ef7eb2e8f9f7 | 82 | multiplier = 2560u; |
<> | 144:ef7eb2e8f9f7 | 83 | break; |
<> | 144:ef7eb2e8f9f7 | 84 | case 0x80u: |
<> | 144:ef7eb2e8f9f7 | 85 | multiplier = 732u; |
<> | 144:ef7eb2e8f9f7 | 86 | break; |
<> | 144:ef7eb2e8f9f7 | 87 | case 0xA0u: |
<> | 144:ef7eb2e8f9f7 | 88 | multiplier = 1464u; |
<> | 144:ef7eb2e8f9f7 | 89 | break; |
<> | 144:ef7eb2e8f9f7 | 90 | case 0xC0u: |
<> | 144:ef7eb2e8f9f7 | 91 | multiplier = 2197u; |
<> | 144:ef7eb2e8f9f7 | 92 | break; |
<> | 144:ef7eb2e8f9f7 | 93 | case 0xE0u: |
<> | 144:ef7eb2e8f9f7 | 94 | default: |
<> | 144:ef7eb2e8f9f7 | 95 | multiplier = 2929u; |
<> | 144:ef7eb2e8f9f7 | 96 | break; |
<> | 144:ef7eb2e8f9f7 | 97 | } |
<> | 144:ef7eb2e8f9f7 | 98 | |
<> | 144:ef7eb2e8f9f7 | 99 | return MCGClock * divider / multiplier; |
<> | 144:ef7eb2e8f9f7 | 100 | } |
<> | 144:ef7eb2e8f9f7 | 101 | #ifdef MCG_C5_PLLCLKEN0_MASK |
<> | 144:ef7eb2e8f9f7 | 102 | } else { //PLL is selected |
<> | 144:ef7eb2e8f9f7 | 103 | divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK)); |
<> | 144:ef7eb2e8f9f7 | 104 | multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u); |
<> | 144:ef7eb2e8f9f7 | 105 | return MCGClock * divider / multiplier; |
<> | 144:ef7eb2e8f9f7 | 106 | } |
<> | 144:ef7eb2e8f9f7 | 107 | } |
<> | 144:ef7eb2e8f9f7 | 108 | #endif |
<> | 144:ef7eb2e8f9f7 | 109 | |
<> | 144:ef7eb2e8f9f7 | 110 | //In all other cases either there is no crystal or we cannot determine it |
<> | 144:ef7eb2e8f9f7 | 111 | //For example when the FLL is running on the internal reference, and there is also an |
<> | 144:ef7eb2e8f9f7 | 112 | //external crystal. However these are unlikely situations |
<> | 144:ef7eb2e8f9f7 | 113 | return 0; |
<> | 144:ef7eb2e8f9f7 | 114 | } |
<> | 144:ef7eb2e8f9f7 | 115 | |
<> | 144:ef7eb2e8f9f7 | 116 | //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit |
<> | 144:ef7eb2e8f9f7 | 117 | static uint32_t mcgpllfll_frequency(void) { |
<> | 144:ef7eb2e8f9f7 | 118 | if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected |
<> | 144:ef7eb2e8f9f7 | 119 | return 0; |
<> | 144:ef7eb2e8f9f7 | 120 | |
<> | 144:ef7eb2e8f9f7 | 121 | uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)); |
<> | 144:ef7eb2e8f9f7 | 122 | #ifdef MCG_C5_PLLCLKEN0_MASK |
<> | 144:ef7eb2e8f9f7 | 123 | if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected |
<> | 144:ef7eb2e8f9f7 | 124 | SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output |
<> | 144:ef7eb2e8f9f7 | 125 | #endif |
<> | 144:ef7eb2e8f9f7 | 126 | return MCGClock; |
<> | 144:ef7eb2e8f9f7 | 127 | #ifdef MCG_C5_PLLCLKEN0_MASK |
<> | 144:ef7eb2e8f9f7 | 128 | } else { //PLL is selected |
<> | 144:ef7eb2e8f9f7 | 129 | SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output |
<> | 144:ef7eb2e8f9f7 | 130 | return (MCGClock >> 1); |
<> | 144:ef7eb2e8f9f7 | 131 | } |
<> | 144:ef7eb2e8f9f7 | 132 | #endif |
<> | 144:ef7eb2e8f9f7 | 133 | |
<> | 144:ef7eb2e8f9f7 | 134 | //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active |
<> | 144:ef7eb2e8f9f7 | 135 | //for the peripherals, this is however an unlikely setup |
<> | 144:ef7eb2e8f9f7 | 136 | } |
<> | 144:ef7eb2e8f9f7 | 137 | |
<> | 144:ef7eb2e8f9f7 | 138 | #endif |
<> | 144:ef7eb2e8f9f7 | 139 | |
<> | 144:ef7eb2e8f9f7 | 140 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 141 | } |
<> | 144:ef7eb2e8f9f7 | 142 | #endif |
<> | 144:ef7eb2e8f9f7 | 143 | |
<> | 144:ef7eb2e8f9f7 | 144 | #endif |