Yelfie / Sensors

Sensor sampling library

sensor_setup.s@1:f9f0b92a9d7c, 2015-02-23 (annotated)

Committer:
Joseph_Penikis
Date:
Mon Feb 23 23:10:36 2015 +0000
Revision:
1:f9f0b92a9d7c
CURRENTLY BROKEN: NOT FUNCTIONING AS REQUIRED

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Joseph_Penikis 1:f9f0b92a9d7c 1 AREA asm_func, CODE, READONLY
Joseph_Penikis 1:f9f0b92a9d7c 2 ; Export my asm function locaiton so that the C compiler can find it and link
Joseph_Penikis 1:f9f0b92a9d7c 3 EXPORT start_systick
Joseph_Penikis 1:f9f0b92a9d7c 4 EXPORT measure_clock_cycles
Joseph_Penikis 1:f9f0b92a9d7c 5 ;
Joseph_Penikis 1:f9f0b92a9d7c 6 ALIGN
Joseph_Penikis 1:f9f0b92a9d7c 7 ;
Joseph_Penikis 1:f9f0b92a9d7c 8 start_systick
Joseph_Penikis 1:f9f0b92a9d7c 9 ;
Joseph_Penikis 1:f9f0b92a9d7c 10 ; Setup base address for SysTick
Joseph_Penikis 1:f9f0b92a9d7c 11 LDR r2, =0xE000E010
Joseph_Penikis 1:f9f0b92a9d7c 12 ; Setup SysTick and start
Joseph_Penikis 1:f9f0b92a9d7c 13 LDR r0, [r2, #0x00] ; Grab current SysTick control state
Joseph_Penikis 1:f9f0b92a9d7c 14 LDR r1, =0x05 ; Mask to set SysTick clock source as processor clock and start it running
Joseph_Penikis 1:f9f0b92a9d7c 15 ORRS r0, r0, r1
Joseph_Penikis 1:f9f0b92a9d7c 16 STR r0, [r2, #0x00]
Joseph_Penikis 1:f9f0b92a9d7c 17 ; Return to previous code
Joseph_Penikis 1:f9f0b92a9d7c 18 BX LR
Joseph_Penikis 1:f9f0b92a9d7c 19 ;
Joseph_Penikis 1:f9f0b92a9d7c 20 measure_clock_cycles
Joseph_Penikis 1:f9f0b92a9d7c 21 ;
Joseph_Penikis 1:f9f0b92a9d7c 22 PUSH {r4-r7}
Joseph_Penikis 1:f9f0b92a9d7c 23 ; Configure pin to sample from
Joseph_Penikis 1:f9f0b92a9d7c 24 LDR r3, =0xF80FF094 ; Port C data direction register
Joseph_Penikis 1:f9f0b92a9d7c 25 LDR r4, =0x00000020 ; Pin 5
Joseph_Penikis 1:f9f0b92a9d7c 26 LDR r5, [r3] ; Current config
Joseph_Penikis 1:f9f0b92a9d7c 27 BICS r5, r5, r4 ; Turn PinC5 to 0, General Purpose Input
Joseph_Penikis 1:f9f0b92a9d7c 28 STR r5, [r3] ; Save config
Joseph_Penikis 1:f9f0b92a9d7c 29 ; Setup base address for current SysTick value
Joseph_Penikis 1:f9f0b92a9d7c 30 LDR r5, =0xE000E018
Joseph_Penikis 1:f9f0b92a9d7c 31 ; Sample starting SysTick
Joseph_Penikis 1:f9f0b92a9d7c 32 LSLS r0, r0, #2 ; Multiply by 2 as both rising and failing edges detected
Joseph_Penikis 1:f9f0b92a9d7c 33 LDR r0, =0x00 ; Clear counter
Joseph_Penikis 1:f9f0b92a9d7c 34 LDR r2, =0x20 ; Pin mask
Joseph_Penikis 1:f9f0b92a9d7c 35 LDR r6, =0xF80FF090 ; Input register
Joseph_Penikis 1:f9f0b92a9d7c 36 LDR r7, =0x00 ; Current pin state
Joseph_Penikis 1:f9f0b92a9d7c 37 LDR r4, [r5] ; Read current SysTick
Joseph_Penikis 1:f9f0b92a9d7c 38 loop
Joseph_Penikis 1:f9f0b92a9d7c 39 LDR r3, [r6] ; Read Input register
Joseph_Penikis 1:f9f0b92a9d7c 40 ANDS r3, r3, r2 ; Mask out pin
Joseph_Penikis 1:f9f0b92a9d7c 41 SUBS r3, r3, r7 ; Sneaky method of detecting bit change, equals zero when no change has occurred
Joseph_Penikis 1:f9f0b92a9d7c 42 BEQ loop ; Loop Until change
Joseph_Penikis 1:f9f0b92a9d7c 43 MOV r7, r3 ; Store new pin state
Joseph_Penikis 1:f9f0b92a9d7c 44 ADDS r0, #1 ; Increment counter by one
Joseph_Penikis 1:f9f0b92a9d7c 45 SUBS r3, r3, r0 ; Subtract SAMPLES from counter
Joseph_Penikis 1:f9f0b92a9d7c 46 BNE loop ; Loop until counter = samples
Joseph_Penikis 1:f9f0b92a9d7c 47 LDR r1, [r5] ; Read ending SysTick
Joseph_Penikis 1:f9f0b92a9d7c 48 ; Compute time difference
Joseph_Penikis 1:f9f0b92a9d7c 49 MOV r0, r4
Joseph_Penikis 1:f9f0b92a9d7c 50 SBCS r0, r0, r1 ; r0 = r4 - r1
Joseph_Penikis 1:f9f0b92a9d7c 51 BPL finish ; If result of subtraction creates a positive number, return r0, otherwise recalculate
Joseph_Penikis 1:f9f0b92a9d7c 52 LDR r3, =0x00FFFFFF
Joseph_Penikis 1:f9f0b92a9d7c 53 SUBS r0, r3, r1 ; r0 = (2^24 - 1 - r1) + r4
Joseph_Penikis 1:f9f0b92a9d7c 54 ADDS r0, r0, r4
Joseph_Penikis 1:f9f0b92a9d7c 55 finish
Joseph_Penikis 1:f9f0b92a9d7c 56 ; Return to previous code
Joseph_Penikis 1:f9f0b92a9d7c 57 POP {r4-r7}
Joseph_Penikis 1:f9f0b92a9d7c 58 BX LR
Joseph_Penikis 1:f9f0b92a9d7c 59 ALIGN
Joseph_Penikis 1:f9f0b92a9d7c 60 END
Joseph_Penikis 1:f9f0b92a9d7c 61