Yelfie / Sensors

Sensor sampling library

Sensors.s@0:eea8d19a7f6b, 2015-02-23 (annotated)

Committer:
Joseph_Penikis
Date:
Mon Feb 23 18:03:29 2015 +0000
Revision:
0:eea8d19a7f6b
Merged Sensor Library into repo

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Joseph_Penikis 0:eea8d19a7f6b 1 AREA asm_func, CODE, READONLY
Joseph_Penikis 0:eea8d19a7f6b 2 ; Export my asm function locaiton so that the C compiler can find it and link
Joseph_Penikis 0:eea8d19a7f6b 3 EXPORT setup_counter
Joseph_Penikis 0:eea8d19a7f6b 4 EXPORT measure_clock_cycles
Joseph_Penikis 0:eea8d19a7f6b 5 ;
Joseph_Penikis 0:eea8d19a7f6b 6 ALIGN
Joseph_Penikis 0:eea8d19a7f6b 7 ;
Joseph_Penikis 0:eea8d19a7f6b 8 setup_counter
Joseph_Penikis 0:eea8d19a7f6b 9 ;
Joseph_Penikis 0:eea8d19a7f6b 10 ; Setup base address for Timer/Counter
Joseph_Penikis 0:eea8d19a7f6b 11 LDR r2, =0x40040000
Joseph_Penikis 0:eea8d19a7f6b 12 ; Setup data for control register, although don't start it yet
Joseph_Penikis 0:eea8d19a7f6b 13 ; TFC set HIGH prevents reset when CNR >= CMR so TCF can be detected
Joseph_Penikis 0:eea8d19a7f6b 14 ; TCF is cleared when timer is disabled after reading value
Joseph_Penikis 0:eea8d19a7f6b 15 LDR r0, =0x06
Joseph_Penikis 0:eea8d19a7f6b 16 STRB r0, [r2, #0x00] ; Setup control register
Joseph_Penikis 0:eea8d19a7f6b 17 ; Setup compare register
Joseph_Penikis 0:eea8d19a7f6b 18 ;STRH r0, [r2, #0x08]
Joseph_Penikis 0:eea8d19a7f6b 19 ; If prescalar is zero, set the register to all 0, CMPS also sets flags
Joseph_Penikis 0:eea8d19a7f6b 20 CMPS r1, #0
Joseph_Penikis 0:eea8d19a7f6b 21 BEQ set_pre_zero
Joseph_Penikis 0:eea8d19a7f6b 22 ; Generate prescale register and store, recycle r0 as its finished with
Joseph_Penikis 0:eea8d19a7f6b 23 LDR r0, =0x03
Joseph_Penikis 0:eea8d19a7f6b 24 LSLS r1, r1, r0 ; Shifts prescale value to the left 3 places
Joseph_Penikis 0:eea8d19a7f6b 25 LDR r0, =0x04
Joseph_Penikis 0:eea8d19a7f6b 26 ORRS r1, r1, r0 ; Sets prescalar enable flag appropiately
Joseph_Penikis 0:eea8d19a7f6b 27 LDR r0, =0x78
Joseph_Penikis 0:eea8d19a7f6b 28 ANDS r1, r1, r0 ; Ensure only the necessary bits are set, maybe redundant
Joseph_Penikis 0:eea8d19a7f6b 29 B continue ; Skip setting register value to zero if above code is executed
Joseph_Penikis 0:eea8d19a7f6b 30 set_pre_zero
Joseph_Penikis 0:eea8d19a7f6b 31 LDR r1, =0x00000000
Joseph_Penikis 0:eea8d19a7f6b 32 continue
Joseph_Penikis 0:eea8d19a7f6b 33 STRB r1, [r2, #0x04] ; Setup prescale register appropriataly
Joseph_Penikis 0:eea8d19a7f6b 34 ; Setup base address for SysTick
Joseph_Penikis 0:eea8d19a7f6b 35 LDR r2, =0xE000E010
Joseph_Penikis 0:eea8d19a7f6b 36 ; Setup SysTick and start
Joseph_Penikis 0:eea8d19a7f6b 37 LDR r0, [r2, #0x00] ; Grab current SysTick control state
Joseph_Penikis 0:eea8d19a7f6b 38 LDR r1, =0x05 ; Mask to set SysTick clock source as processor clock and start it running
Joseph_Penikis 0:eea8d19a7f6b 39 ORRS r0, r0, r1
Joseph_Penikis 0:eea8d19a7f6b 40 STR r0, [r2, #0x00]
Joseph_Penikis 0:eea8d19a7f6b 41 ; Return to previous code
Joseph_Penikis 0:eea8d19a7f6b 42 BX LR
Joseph_Penikis 0:eea8d19a7f6b 43 ;
Joseph_Penikis 0:eea8d19a7f6b 44 measure_clock_cycles
Joseph_Penikis 0:eea8d19a7f6b 45 ; r0 -> Channel Data, r1 -> SAMPLES
Joseph_Penikis 0:eea8d19a7f6b 46 ; Preserve state of all affected registers (ARM convention only requires this on r4 -> r11)
Joseph_Penikis 0:eea8d19a7f6b 47 PUSH {r4-r6}
Joseph_Penikis 0:eea8d19a7f6b 48 ; Setup base address for Timer/Counter
Joseph_Penikis 0:eea8d19a7f6b 49 LDR r2, =0x40040000
Joseph_Penikis 0:eea8d19a7f6b 50 ; Grab current control status register and prepare with sensor and enable
Joseph_Penikis 0:eea8d19a7f6b 51 LDR r3, =0x03
Joseph_Penikis 0:eea8d19a7f6b 52 ANDS r0, r0, r3 ; Trims sensor value to 2 bits in case value larger than 0x03 passed
Joseph_Penikis 0:eea8d19a7f6b 53 LDR r3, =0x04
Joseph_Penikis 0:eea8d19a7f6b 54 LSLS r0, r0, r3 ; Shift timer pin select to appropriate location
Joseph_Penikis 0:eea8d19a7f6b 55 LDR r3, =0x80
Joseph_Penikis 0:eea8d19a7f6b 56 ORRS r0, r0, r3 ; Set TCF flag
Joseph_Penikis 0:eea8d19a7f6b 57 LDR r3, [r2, #0x00] ; Grab current control register state
Joseph_Penikis 0:eea8d19a7f6b 58 ORRS r0, r0, r3 ; Combine with previous register state
Joseph_Penikis 0:eea8d19a7f6b 59 STR r0, [r2, #0x00] ; Save control register
Joseph_Penikis 0:eea8d19a7f6b 60 LDR r1, [r2, #0x08] ; Set compare register to number of samples
Joseph_Penikis 0:eea8d19a7f6b 61 LDR r5, =0x80 ; Mask for TCF
Joseph_Penikis 0:eea8d19a7f6b 62 BICS r0, r0, r4 ; Disable TCF flag
Joseph_Penikis 0:eea8d19a7f6b 63 STR r0, [r2, #0x00] ; Set control register with TCF disabled
Joseph_Penikis 0:eea8d19a7f6b 64 ; Save current tick count of cpu
Joseph_Penikis 0:eea8d19a7f6b 65 LDR r3, =0xE000E010 ; Base address of SysTick
Joseph_Penikis 0:eea8d19a7f6b 66 LDR r4, [r3, #0x08]
Joseph_Penikis 0:eea8d19a7f6b 67 ; Start timer
Joseph_Penikis 0:eea8d19a7f6b 68 STR r0, [r2, #0x00]
Joseph_Penikis 0:eea8d19a7f6b 69 ; Wait until TCF = 1 in Timer/Counter
Joseph_Penikis 0:eea8d19a7f6b 70 loop
Joseph_Penikis 0:eea8d19a7f6b 71 LDR r0, [r2, #0x00]
Joseph_Penikis 0:eea8d19a7f6b 72 ANDS r0, r0, r5
Joseph_Penikis 0:eea8d19a7f6b 73 BEQ loop ; Loops while TCF flag is zero
Joseph_Penikis 0:eea8d19a7f6b 74 ; Save current tick count of cpu
Joseph_Penikis 0:eea8d19a7f6b 75 LDR r5, [r3, #0x08]
Joseph_Penikis 0:eea8d19a7f6b 76 ; Disable timer by toggling bit
Joseph_Penikis 0:eea8d19a7f6b 77 LDR r3, =0x01
Joseph_Penikis 0:eea8d19a7f6b 78 LDR r6, [r2, #0x00]
Joseph_Penikis 0:eea8d19a7f6b 79 EORS r3, r3, r6
Joseph_Penikis 0:eea8d19a7f6b 80 STR r3, [r2, #0x00]
Joseph_Penikis 0:eea8d19a7f6b 81 ; Compute time difference and place it into r0, r0 is the return value of the function
Joseph_Penikis 0:eea8d19a7f6b 82 MOV r0, r4
Joseph_Penikis 0:eea8d19a7f6b 83 SBCS r0, r0, r5 ; r0 = r4 - r5 (With sign)
Joseph_Penikis 0:eea8d19a7f6b 84 BPL finish ; If result of subtraction creates a negative number, return value, otherwise recalculate
Joseph_Penikis 0:eea8d19a7f6b 85 LDR r3, =0x00FFFFFF
Joseph_Penikis 0:eea8d19a7f6b 86 SUBS r0, r3, r5 ; r0 = (2^24 - 1 - r5) + r4
Joseph_Penikis 0:eea8d19a7f6b 87 ADDS r0, r0, r4
Joseph_Penikis 0:eea8d19a7f6b 88 finish
Joseph_Penikis 0:eea8d19a7f6b 89 ;LDR r0, [r2, #0x00]
Joseph_Penikis 0:eea8d19a7f6b 90 ; Return registers to previous states
Joseph_Penikis 0:eea8d19a7f6b 91 POP {r4-r6}
Joseph_Penikis 0:eea8d19a7f6b 92 ; Return to previous code
Joseph_Penikis 0:eea8d19a7f6b 93 BX LR
Joseph_Penikis 0:eea8d19a7f6b 94 ;
Joseph_Penikis 0:eea8d19a7f6b 95 ALIGN
Joseph_Penikis 0:eea8d19a7f6b 96 END
Joseph_Penikis 0:eea8d19a7f6b 97