WIZnet / W5500

W5500 Driver

Fork of W5500 by Raphael Kwon

w5500.c@0:4f25c0dc00f7, 2014-02-18 (annotated)

Committer:
xeon011
Date:
Tue Feb 18 05:25:12 2014 +0000
Revision:
0:4f25c0dc00f7
First release;   - WIZnet Library for W5500

Who changed what in which revision?

UserRevisionLine numberNew contents of line
xeon011 0:4f25c0dc00f7 1 //*****************************************************************************
xeon011 0:4f25c0dc00f7 2 //
xeon011 0:4f25c0dc00f7 3 //! \file w5500.c
xeon011 0:4f25c0dc00f7 4 //! \brief W5500 HAL Interface.
xeon011 0:4f25c0dc00f7 5 //! \version 1.0.0
xeon011 0:4f25c0dc00f7 6 //! \date 2013/10/01
xeon011 0:4f25c0dc00f7 7 //! \par Revision history
xeon011 0:4f25c0dc00f7 8 //! <2013/10/01> 1st Release
xeon011 0:4f25c0dc00f7 9 //! \author MidnightCow
xeon011 0:4f25c0dc00f7 10 //! \copyright
xeon011 0:4f25c0dc00f7 11 //!
xeon011 0:4f25c0dc00f7 12 //! Copyright (c) 2013, WIZnet Co., LTD.
xeon011 0:4f25c0dc00f7 13 //! All rights reserved.
xeon011 0:4f25c0dc00f7 14 //!
xeon011 0:4f25c0dc00f7 15 //! Redistribution and use in source and binary forms, with or without
xeon011 0:4f25c0dc00f7 16 //! modification, are permitted provided that the following conditions
xeon011 0:4f25c0dc00f7 17 //! are met:
xeon011 0:4f25c0dc00f7 18 //!
xeon011 0:4f25c0dc00f7 19 //! * Redistributions of source code must retain the above copyright
xeon011 0:4f25c0dc00f7 20 //! notice, this list of conditions and the following disclaimer.
xeon011 0:4f25c0dc00f7 21 //! * Redistributions in binary form must reproduce the above copyright
xeon011 0:4f25c0dc00f7 22 //! notice, this list of conditions and the following disclaimer in the
xeon011 0:4f25c0dc00f7 23 //! documentation and/or other materials provided with the distribution.
xeon011 0:4f25c0dc00f7 24 //! * Neither the name of the <ORGANIZATION> nor the names of its
xeon011 0:4f25c0dc00f7 25 //! contributors may be used to endorse or promote products derived
xeon011 0:4f25c0dc00f7 26 //! from this software without specific prior written permission.
xeon011 0:4f25c0dc00f7 27 //!
xeon011 0:4f25c0dc00f7 28 //! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
xeon011 0:4f25c0dc00f7 29 //! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
xeon011 0:4f25c0dc00f7 30 //! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
xeon011 0:4f25c0dc00f7 31 //! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
xeon011 0:4f25c0dc00f7 32 //! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
xeon011 0:4f25c0dc00f7 33 //! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
xeon011 0:4f25c0dc00f7 34 //! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
xeon011 0:4f25c0dc00f7 35 //! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
xeon011 0:4f25c0dc00f7 36 //! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
xeon011 0:4f25c0dc00f7 37 //! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
xeon011 0:4f25c0dc00f7 38 //! THE POSSIBILITY OF SUCH DAMAGE.
xeon011 0:4f25c0dc00f7 39 //
xeon011 0:4f25c0dc00f7 40 //*****************************************************************************
xeon011 0:4f25c0dc00f7 41 #include <stdio.h>
xeon011 0:4f25c0dc00f7 42 #include "w5500.h"
xeon011 0:4f25c0dc00f7 43
xeon011 0:4f25c0dc00f7 44
xeon011 0:4f25c0dc00f7 45 #define _W5500_SPI_VDM_OP_ 0x00
xeon011 0:4f25c0dc00f7 46 #define _W5500_SPI_FDM_OP_LEN1_ 0x01
xeon011 0:4f25c0dc00f7 47 #define _W5500_SPI_FDM_OP_LEN2_ 0x02
xeon011 0:4f25c0dc00f7 48 #define _W5500_SPI_FDM_OP_LEN4_ 0x03
xeon011 0:4f25c0dc00f7 49
xeon011 0:4f25c0dc00f7 50 ////////////////////////////////////////////////////
xeon011 0:4f25c0dc00f7 51
xeon011 0:4f25c0dc00f7 52 uint8_t WIZCHIP_READ(uint32_t AddrSel)
xeon011 0:4f25c0dc00f7 53 {
xeon011 0:4f25c0dc00f7 54 uint8_t ret;
xeon011 0:4f25c0dc00f7 55
xeon011 0:4f25c0dc00f7 56 WIZCHIP_CRITICAL_ENTER();
xeon011 0:4f25c0dc00f7 57 WIZCHIP.CS._select();
xeon011 0:4f25c0dc00f7 58
xeon011 0:4f25c0dc00f7 59 #if( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_))
xeon011 0:4f25c0dc00f7 60
xeon011 0:4f25c0dc00f7 61 #if ( _WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_SPI_VDM_ )
xeon011 0:4f25c0dc00f7 62 AddrSel |= (_W5500_SPI_READ_ | _W5500_SPI_VDM_OP_);
xeon011 0:4f25c0dc00f7 63 #elif( _WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_SPI_FDM_ )
xeon011 0:4f25c0dc00f7 64 AddrSel |= (_W5500_SPI_READ_ | _W5500_SPI_FDM_OP_LEN1_);
xeon011 0:4f25c0dc00f7 65 #else
xeon011 0:4f25c0dc00f7 66 #error "Unsupported _WIZCHIP_IO_SPI_ in W5500 !!!"
xeon011 0:4f25c0dc00f7 67 #endif
xeon011 0:4f25c0dc00f7 68
xeon011 0:4f25c0dc00f7 69 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF0000) >> 16);
xeon011 0:4f25c0dc00f7 70 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
xeon011 0:4f25c0dc00f7 71 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
xeon011 0:4f25c0dc00f7 72 ret = WIZCHIP.IF.SPI._read_byte();
xeon011 0:4f25c0dc00f7 73
xeon011 0:4f25c0dc00f7 74 #elif ( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_) )
xeon011 0:4f25c0dc00f7 75
xeon011 0:4f25c0dc00f7 76 #if (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_DIR_)
xeon011 0:4f25c0dc00f7 77
xeon011 0:4f25c0dc00f7 78 #elif(_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_INDIR_)
xeon011 0:4f25c0dc00f7 79
xeon011 0:4f25c0dc00f7 80 #else
xeon011 0:4f25c0dc00f7 81 #error "Unsupported _WIZCHIP_IO_MODE_BUS_ in W5500 !!!"
xeon011 0:4f25c0dc00f7 82 #endif
xeon011 0:4f25c0dc00f7 83 #else
xeon011 0:4f25c0dc00f7 84 #error "Unknown _WIZCHIP_IO_MODE_ in W5000. !!!"
xeon011 0:4f25c0dc00f7 85 #endif
xeon011 0:4f25c0dc00f7 86
xeon011 0:4f25c0dc00f7 87 WIZCHIP.CS._deselect();
xeon011 0:4f25c0dc00f7 88 WIZCHIP_CRITICAL_EXIT();
xeon011 0:4f25c0dc00f7 89 return ret;
xeon011 0:4f25c0dc00f7 90 }
xeon011 0:4f25c0dc00f7 91
xeon011 0:4f25c0dc00f7 92 void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb )
xeon011 0:4f25c0dc00f7 93 {
xeon011 0:4f25c0dc00f7 94 WIZCHIP_CRITICAL_ENTER();
xeon011 0:4f25c0dc00f7 95 WIZCHIP.CS._select();
xeon011 0:4f25c0dc00f7 96
xeon011 0:4f25c0dc00f7 97 #if( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_))
xeon011 0:4f25c0dc00f7 98
xeon011 0:4f25c0dc00f7 99 #if ( _WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_SPI_VDM_ )
xeon011 0:4f25c0dc00f7 100 AddrSel |= (_W5500_SPI_WRITE_ | _W5500_SPI_VDM_OP_);
xeon011 0:4f25c0dc00f7 101 #elif( _WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_SPI_FDM_ )
xeon011 0:4f25c0dc00f7 102 AddrSel |= (_W5500_SPI_WRITE_ | _W5500_SPI_FDM_OP_LEN1_);
xeon011 0:4f25c0dc00f7 103 #else
xeon011 0:4f25c0dc00f7 104 #error "Unsupported _WIZCHIP_IO_SPI_ in W5500 !!!"
xeon011 0:4f25c0dc00f7 105 #endif
xeon011 0:4f25c0dc00f7 106
xeon011 0:4f25c0dc00f7 107 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF0000) >> 16);
xeon011 0:4f25c0dc00f7 108 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
xeon011 0:4f25c0dc00f7 109 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
xeon011 0:4f25c0dc00f7 110 WIZCHIP.IF.SPI._write_byte(wb);
xeon011 0:4f25c0dc00f7 111
xeon011 0:4f25c0dc00f7 112 #elif ( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_) )
xeon011 0:4f25c0dc00f7 113
xeon011 0:4f25c0dc00f7 114 #if (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_DIR_)
xeon011 0:4f25c0dc00f7 115
xeon011 0:4f25c0dc00f7 116 #elif(_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_INDIR_)
xeon011 0:4f25c0dc00f7 117
xeon011 0:4f25c0dc00f7 118 #else
xeon011 0:4f25c0dc00f7 119 #error "Unsupported _WIZCHIP_IO_MODE_BUS_ in W5500 !!!"
xeon011 0:4f25c0dc00f7 120 #endif
xeon011 0:4f25c0dc00f7 121 #else
xeon011 0:4f25c0dc00f7 122 #error "Unknown _WIZCHIP_IO_MODE_ in W5500. !!!"
xeon011 0:4f25c0dc00f7 123 #endif
xeon011 0:4f25c0dc00f7 124
xeon011 0:4f25c0dc00f7 125 WIZCHIP.CS._deselect();
xeon011 0:4f25c0dc00f7 126 WIZCHIP_CRITICAL_EXIT();
xeon011 0:4f25c0dc00f7 127 }
xeon011 0:4f25c0dc00f7 128
xeon011 0:4f25c0dc00f7 129 void WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t* pBuf, uint16_t len)
xeon011 0:4f25c0dc00f7 130 {
xeon011 0:4f25c0dc00f7 131 uint16_t i = 0;
xeon011 0:4f25c0dc00f7 132 uint16_t j = 0;
xeon011 0:4f25c0dc00f7 133 WIZCHIP_CRITICAL_ENTER();
xeon011 0:4f25c0dc00f7 134 WIZCHIP.CS._select();
xeon011 0:4f25c0dc00f7 135
xeon011 0:4f25c0dc00f7 136 #if( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_))
xeon011 0:4f25c0dc00f7 137
xeon011 0:4f25c0dc00f7 138 #if ( _WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_SPI_VDM_ )
xeon011 0:4f25c0dc00f7 139 AddrSel |= (_W5500_SPI_READ_ | _W5500_SPI_VDM_OP_);
xeon011 0:4f25c0dc00f7 140 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF0000) >> 16);
xeon011 0:4f25c0dc00f7 141 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
xeon011 0:4f25c0dc00f7 142 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
xeon011 0:4f25c0dc00f7 143 for(i = 0; i < len; i++)
xeon011 0:4f25c0dc00f7 144 pBuf[i] = WIZCHIP.IF.SPI._read_byte();
xeon011 0:4f25c0dc00f7 145 #elif( _WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_SPI_FDM_ )
xeon011 0:4f25c0dc00f7 146 AddrSel |= (_W5500_SPI_READ_ | _W5500_SPI_FDM_OP_LEN4_);
xeon011 0:4f25c0dc00f7 147 for(i = 0; i < len/4; i++)
xeon011 0:4f25c0dc00f7 148 {
xeon011 0:4f25c0dc00f7 149 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF0000) >> 16);
xeon011 0:4f25c0dc00f7 150 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
xeon011 0:4f25c0dc00f7 151 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
xeon011 0:4f25c0dc00f7 152 pBuf[i*4] = WIZCHIP.IF.SPI._read_byte();
xeon011 0:4f25c0dc00f7 153 pBuf[i*4+1] = WIZCHIP.IF.SPI._read_byte();
xeon011 0:4f25c0dc00f7 154 pBuf[i*4+2] = WIZCHIP.IF.SPI._read_byte();
xeon011 0:4f25c0dc00f7 155 pBuf[i*4+3] = WIZCHIP.IF.SPI._read_byte();
xeon011 0:4f25c0dc00f7 156 //AddrSel += (4 << 8); // offset address + 4
xeon011 0:4f25c0dc00f7 157 AddrSel = WIZCHIP_OFFSET_INC(AddrSel,4);
xeon011 0:4f25c0dc00f7 158 }
xeon011 0:4f25c0dc00f7 159 len %= 4; // for the rest data
xeon011 0:4f25c0dc00f7 160 if(len)
xeon011 0:4f25c0dc00f7 161 {
xeon011 0:4f25c0dc00f7 162 AddrSel -= 1; // change _W5500_SPI_FDM_OP_LEN4_ to _W5500_SPI_FDM_OP_LEN2_
xeon011 0:4f25c0dc00f7 163 i *= 4;
xeon011 0:4f25c0dc00f7 164 for(j = 0; j < len/2 ; j++)
xeon011 0:4f25c0dc00f7 165 {
xeon011 0:4f25c0dc00f7 166 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF0000) >> 16);
xeon011 0:4f25c0dc00f7 167 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
xeon011 0:4f25c0dc00f7 168 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
xeon011 0:4f25c0dc00f7 169 pBuf[i] = WIZCHIP.IF.SPI._read_byte();
xeon011 0:4f25c0dc00f7 170 pBuf[i+1] = WIZCHIP.IF.SPI._read_byte();
xeon011 0:4f25c0dc00f7 171 i += 2;
xeon011 0:4f25c0dc00f7 172 //AddrSel += (2 << 8); // offset address + 2
xeon011 0:4f25c0dc00f7 173 AddrSel = WIZCHIP_OFFSET_INC(AddrSel,2);
xeon011 0:4f25c0dc00f7 174 }
xeon011 0:4f25c0dc00f7 175 len %= 2;
xeon011 0:4f25c0dc00f7 176 if(len)
xeon011 0:4f25c0dc00f7 177 {
xeon011 0:4f25c0dc00f7 178 AddrSel -= 1; // change _W5500_SPI_FDM_OP_LEN2_ to _W5500_SPI_FDM_OP_LEN1_
xeon011 0:4f25c0dc00f7 179 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF0000) >> 16);
xeon011 0:4f25c0dc00f7 180 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
xeon011 0:4f25c0dc00f7 181 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
xeon011 0:4f25c0dc00f7 182 pBuf[i] = WIZCHIP.IF.SPI._read_byte();
xeon011 0:4f25c0dc00f7 183 }
xeon011 0:4f25c0dc00f7 184 }
xeon011 0:4f25c0dc00f7 185 #else
xeon011 0:4f25c0dc00f7 186 #error "Unsupported _WIZCHIP_IO_SPI_ in W5500 !!!"
xeon011 0:4f25c0dc00f7 187 #endif
xeon011 0:4f25c0dc00f7 188
xeon011 0:4f25c0dc00f7 189 #elif ( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_) )
xeon011 0:4f25c0dc00f7 190
xeon011 0:4f25c0dc00f7 191 #if (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_DIR_)
xeon011 0:4f25c0dc00f7 192
xeon011 0:4f25c0dc00f7 193 #elif(_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_INDIR_)
xeon011 0:4f25c0dc00f7 194
xeon011 0:4f25c0dc00f7 195 #else
xeon011 0:4f25c0dc00f7 196 #error "Unsupported _WIZCHIP_IO_MODE_BUS_ in W5500 !!!"
xeon011 0:4f25c0dc00f7 197 #endif
xeon011 0:4f25c0dc00f7 198 #else
xeon011 0:4f25c0dc00f7 199 #error "Unknown _WIZCHIP_IO_MODE_ in W5500. !!!!"
xeon011 0:4f25c0dc00f7 200 #endif
xeon011 0:4f25c0dc00f7 201
xeon011 0:4f25c0dc00f7 202 WIZCHIP.CS._deselect();
xeon011 0:4f25c0dc00f7 203 WIZCHIP_CRITICAL_EXIT();
xeon011 0:4f25c0dc00f7 204 }
xeon011 0:4f25c0dc00f7 205
xeon011 0:4f25c0dc00f7 206 void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len)
xeon011 0:4f25c0dc00f7 207 {
xeon011 0:4f25c0dc00f7 208 uint16_t i = 0;
xeon011 0:4f25c0dc00f7 209 uint16_t j = 0;
xeon011 0:4f25c0dc00f7 210 WIZCHIP_CRITICAL_ENTER();
xeon011 0:4f25c0dc00f7 211 WIZCHIP.CS._select();
xeon011 0:4f25c0dc00f7 212
xeon011 0:4f25c0dc00f7 213 #if( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_))
xeon011 0:4f25c0dc00f7 214
xeon011 0:4f25c0dc00f7 215 #if ( _WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_SPI_VDM_ )
xeon011 0:4f25c0dc00f7 216 AddrSel |= (_W5500_SPI_WRITE_ | _W5500_SPI_VDM_OP_);
xeon011 0:4f25c0dc00f7 217 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF0000) >> 16);
xeon011 0:4f25c0dc00f7 218 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
xeon011 0:4f25c0dc00f7 219 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
xeon011 0:4f25c0dc00f7 220 for(i = 0; i < len; i++)
xeon011 0:4f25c0dc00f7 221 WIZCHIP.IF.SPI._write_byte(pBuf[i]);
xeon011 0:4f25c0dc00f7 222 #elif( _WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_SPI_FDM_ )
xeon011 0:4f25c0dc00f7 223 AddrSel |= (_W5500_SPI_WRITE_ | _W5500_SPI_FDM_OP_LEN4_);
xeon011 0:4f25c0dc00f7 224 for(i = 0; i < len/4; i++)
xeon011 0:4f25c0dc00f7 225 {
xeon011 0:4f25c0dc00f7 226 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF0000) >> 16);
xeon011 0:4f25c0dc00f7 227 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
xeon011 0:4f25c0dc00f7 228 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
xeon011 0:4f25c0dc00f7 229 WIZCHIP.IF.SPI._write_byte(pBuf[i*4] );
xeon011 0:4f25c0dc00f7 230 WIZCHIP.IF.SPI._write_byte(pBuf[i*4+1]);
xeon011 0:4f25c0dc00f7 231 WIZCHIP.IF.SPI._write_byte(pBuf[i*4+2]);
xeon011 0:4f25c0dc00f7 232 WIZCHIP.IF.SPI._write_byte(pBuf[i*4+3]);
xeon011 0:4f25c0dc00f7 233 //AddrSel += (4 << 8); // offset address + 4
xeon011 0:4f25c0dc00f7 234 AddrSel = WIZCHIP_OFFSET_INC(AddrSel,4);
xeon011 0:4f25c0dc00f7 235 }
xeon011 0:4f25c0dc00f7 236 len %= 4; // for the rest data
xeon011 0:4f25c0dc00f7 237 if(len)
xeon011 0:4f25c0dc00f7 238 {
xeon011 0:4f25c0dc00f7 239 AddrSel -= 1; // change _W5500_SPI_FDM_OP_LEN4_ to _W5500_SPI_FDM_OP_LEN2_
xeon011 0:4f25c0dc00f7 240 i *= 4;
xeon011 0:4f25c0dc00f7 241 for(j = 0; j < len/2 ; j++)
xeon011 0:4f25c0dc00f7 242 {
xeon011 0:4f25c0dc00f7 243 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF0000) >> 16);
xeon011 0:4f25c0dc00f7 244 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
xeon011 0:4f25c0dc00f7 245 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
xeon011 0:4f25c0dc00f7 246 WIZCHIP.IF.SPI._write_byte(pBuf[i] );
xeon011 0:4f25c0dc00f7 247 WIZCHIP.IF.SPI._write_byte(pBuf[i+1]);
xeon011 0:4f25c0dc00f7 248 i += 2;
xeon011 0:4f25c0dc00f7 249 //AddrSel += (2 << 8); // offset address + 2
xeon011 0:4f25c0dc00f7 250 AddrSel = WIZCHIP_OFFSET_INC(AddrSel, 2);
xeon011 0:4f25c0dc00f7 251 }
xeon011 0:4f25c0dc00f7 252 len %= 2;
xeon011 0:4f25c0dc00f7 253 if(len)
xeon011 0:4f25c0dc00f7 254 {
xeon011 0:4f25c0dc00f7 255 AddrSel -= 1; // change _W5500_SPI_FDM_OP_LEN2_ to _W5500_SPI_FDM_OP_LEN1_
xeon011 0:4f25c0dc00f7 256 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF0000) >> 16);
xeon011 0:4f25c0dc00f7 257 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
xeon011 0:4f25c0dc00f7 258 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
xeon011 0:4f25c0dc00f7 259 WIZCHIP.IF.SPI._write_byte(pBuf[i]);
xeon011 0:4f25c0dc00f7 260 }
xeon011 0:4f25c0dc00f7 261 }
xeon011 0:4f25c0dc00f7 262 #else
xeon011 0:4f25c0dc00f7 263 #error "Unsupported _WIZCHIP_IO_SPI_ in W5500 !!!"
xeon011 0:4f25c0dc00f7 264 #endif
xeon011 0:4f25c0dc00f7 265
xeon011 0:4f25c0dc00f7 266 #elif ( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_) )
xeon011 0:4f25c0dc00f7 267
xeon011 0:4f25c0dc00f7 268 #if (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_DIR_)
xeon011 0:4f25c0dc00f7 269
xeon011 0:4f25c0dc00f7 270 #elif(_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_INDIR_)
xeon011 0:4f25c0dc00f7 271
xeon011 0:4f25c0dc00f7 272 #else
xeon011 0:4f25c0dc00f7 273 #error "Unsupported _WIZCHIP_IO_MODE_BUS_ in W5500 !!!"
xeon011 0:4f25c0dc00f7 274 #endif
xeon011 0:4f25c0dc00f7 275 #else
xeon011 0:4f25c0dc00f7 276 #error "Unknown _WIZCHIP_IO_MODE_ in W5500. !!!!"
xeon011 0:4f25c0dc00f7 277 #endif
xeon011 0:4f25c0dc00f7 278
xeon011 0:4f25c0dc00f7 279 WIZCHIP.CS._deselect();
xeon011 0:4f25c0dc00f7 280 WIZCHIP_CRITICAL_EXIT();
xeon011 0:4f25c0dc00f7 281 }
xeon011 0:4f25c0dc00f7 282
xeon011 0:4f25c0dc00f7 283
xeon011 0:4f25c0dc00f7 284 uint16_t getSn_TX_FSR(uint8_t sn)
xeon011 0:4f25c0dc00f7 285 {
xeon011 0:4f25c0dc00f7 286 uint16_t val=0,val1=0;
xeon011 0:4f25c0dc00f7 287 do
xeon011 0:4f25c0dc00f7 288 {
xeon011 0:4f25c0dc00f7 289 val1 = WIZCHIP_READ(Sn_TX_FSR(sn));
xeon011 0:4f25c0dc00f7 290 val1 = (val1 << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_FSR(sn),1));
xeon011 0:4f25c0dc00f7 291 if (val1 != 0)
xeon011 0:4f25c0dc00f7 292 {
xeon011 0:4f25c0dc00f7 293 val = WIZCHIP_READ(Sn_TX_FSR(sn));
xeon011 0:4f25c0dc00f7 294 val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_FSR(sn),1));
xeon011 0:4f25c0dc00f7 295 }
xeon011 0:4f25c0dc00f7 296 }while (val != val1);
xeon011 0:4f25c0dc00f7 297 return val;
xeon011 0:4f25c0dc00f7 298 }
xeon011 0:4f25c0dc00f7 299
xeon011 0:4f25c0dc00f7 300
xeon011 0:4f25c0dc00f7 301 uint16_t getSn_RX_RSR(uint8_t sn)
xeon011 0:4f25c0dc00f7 302 {
xeon011 0:4f25c0dc00f7 303 uint16_t val=0,val1=0;
xeon011 0:4f25c0dc00f7 304 do
xeon011 0:4f25c0dc00f7 305 {
xeon011 0:4f25c0dc00f7 306 val1 = WIZCHIP_READ(Sn_RX_RSR(sn));
xeon011 0:4f25c0dc00f7 307 val1 = (val1 << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RSR(sn),1));
xeon011 0:4f25c0dc00f7 308 if (val1 != 0)
xeon011 0:4f25c0dc00f7 309 {
xeon011 0:4f25c0dc00f7 310 val = WIZCHIP_READ(Sn_RX_RSR(sn));
xeon011 0:4f25c0dc00f7 311 val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RSR(sn),1));
xeon011 0:4f25c0dc00f7 312 }
xeon011 0:4f25c0dc00f7 313 }while (val != val1);
xeon011 0:4f25c0dc00f7 314 return val;
xeon011 0:4f25c0dc00f7 315 }
xeon011 0:4f25c0dc00f7 316
xeon011 0:4f25c0dc00f7 317 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len)
xeon011 0:4f25c0dc00f7 318 {
xeon011 0:4f25c0dc00f7 319 uint16_t ptr = 0;
xeon011 0:4f25c0dc00f7 320 uint32_t addrsel = 0;
xeon011 0:4f25c0dc00f7 321 if(len == 0) return;
xeon011 0:4f25c0dc00f7 322 ptr = getSn_TX_WR(sn);
xeon011 0:4f25c0dc00f7 323
xeon011 0:4f25c0dc00f7 324 addrsel = (ptr << 8) + (WIZCHIP_TXBUF_BLOCK(sn) << 3);
xeon011 0:4f25c0dc00f7 325 WIZCHIP_WRITE_BUF(addrsel,wizdata, len);
xeon011 0:4f25c0dc00f7 326
xeon011 0:4f25c0dc00f7 327 ptr += len;
xeon011 0:4f25c0dc00f7 328 setSn_TX_WR(sn,ptr);
xeon011 0:4f25c0dc00f7 329 }
xeon011 0:4f25c0dc00f7 330
xeon011 0:4f25c0dc00f7 331 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len)
xeon011 0:4f25c0dc00f7 332 {
xeon011 0:4f25c0dc00f7 333 uint16_t ptr = 0;
xeon011 0:4f25c0dc00f7 334 uint32_t addrsel = 0;
xeon011 0:4f25c0dc00f7 335
xeon011 0:4f25c0dc00f7 336 if(len == 0) return;
xeon011 0:4f25c0dc00f7 337 ptr = getSn_RX_RD(sn);
xeon011 0:4f25c0dc00f7 338 addrsel = (ptr << 8) + (WIZCHIP_RXBUF_BLOCK(sn) << 3);
xeon011 0:4f25c0dc00f7 339
xeon011 0:4f25c0dc00f7 340 WIZCHIP_READ_BUF(addrsel, wizdata, len);
xeon011 0:4f25c0dc00f7 341 ptr += len;
xeon011 0:4f25c0dc00f7 342
xeon011 0:4f25c0dc00f7 343 setSn_RX_RD(sn,ptr);
xeon011 0:4f25c0dc00f7 344 }
xeon011 0:4f25c0dc00f7 345
xeon011 0:4f25c0dc00f7 346
xeon011 0:4f25c0dc00f7 347 void wiz_recv_ignore(uint8_t sn, uint16_t len)
xeon011 0:4f25c0dc00f7 348 {
xeon011 0:4f25c0dc00f7 349 uint16_t ptr = 0;
xeon011 0:4f25c0dc00f7 350 ptr = getSn_RX_RD(sn);
xeon011 0:4f25c0dc00f7 351 ptr += len;
xeon011 0:4f25c0dc00f7 352 setSn_RX_RD(sn,ptr);
xeon011 0:4f25c0dc00f7 353 }