UVic Assistive Technology Lab
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DSLR_Camera_Gimbal
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Dependencies: mbed ros_lib_kinetic
mbed/TARGET_NUCLEO_F446RE/stm32f4xx_hal_spdifrx.h@0:3a767f41cf04, 2018-01-31 (annotated)
- Committer:
- group-UVic-Assistive-Technolog
- Date:
- Wed Jan 31 05:24:12 2018 +0000
- Revision:
- 0:3a767f41cf04
Initial commit
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 1 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 2 | ****************************************************************************** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 3 | * @file stm32f4xx_hal_spdifrx.h |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 4 | * @author MCD Application Team |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 5 | * @version V1.4.1 |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 6 | * @date 09-October-2015 |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 7 | * @brief Header file of SPDIFRX HAL module. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 8 | ****************************************************************************** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 9 | * @attention |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 10 | * |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 12 | * |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 14 | * are permitted provided that the following conditions are met: |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 16 | * this list of conditions and the following disclaimer. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 18 | * this list of conditions and the following disclaimer in the documentation |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 19 | * and/or other materials provided with the distribution. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 21 | * may be used to endorse or promote products derived from this software |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 22 | * without specific prior written permission. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 23 | * |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 34 | * |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 35 | ****************************************************************************** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 36 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 37 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 39 | #ifndef __STM32F4xx_HAL_SPDIFRX_H |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 40 | #define __STM32F4xx_HAL_SPDIFRX_H |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 41 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 42 | #ifdef __cplusplus |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 43 | extern "C" { |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 44 | #endif |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 45 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 46 | #if defined(STM32F446xx) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 47 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 48 | /* Includes ------------------------------------------------------------------*/ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 49 | #include "stm32f4xx_hal_def.h" |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 50 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 51 | /** @addtogroup STM32F4xx_HAL_Driver |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 52 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 53 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 54 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 55 | /** @addtogroup SPDIFRX |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 56 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 57 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 58 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 59 | /* Exported types ------------------------------------------------------------*/ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 60 | /** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 61 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 62 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 63 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 64 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 65 | * @brief SPDIFRX Init structure definition |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 66 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 67 | typedef struct |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 68 | { |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 69 | uint32_t InputSelection; /*!< Specifies the SPDIF input selection. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 70 | This parameter can be a value of @ref SPDIFRX_Input_Selection */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 71 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 72 | uint32_t Retries; /*!< Specifies the Maximum allowed re-tries during synchronization phase. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 73 | This parameter can be a value of @ref SPDIFRX_Max_Retries */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 74 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 75 | uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 76 | This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 77 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 78 | uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 79 | This parameter can be a value of @ref SPDIFRX_Channel_Selection */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 80 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 81 | uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...). |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 82 | This parameter can be a value of @ref SPDIFRX_Data_Format */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 83 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 84 | uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 85 | This parameter can be a value of @ref SPDIFRX_Stereo_Mode */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 86 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 87 | uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 88 | This parameter can be a value of @ref SPDIFRX_PT_Mask */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 89 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 90 | uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 91 | This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 92 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 93 | uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 94 | This parameter can be a value of @ref SPDIFRX_V_Mask */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 95 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 96 | uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 97 | This parameter can be a value of @ref SPDIFRX_PE_Mask */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 98 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 99 | }SPDIFRX_InitTypeDef; |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 100 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 101 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 102 | * @brief SPDIFRX SetDataFormat structure definition |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 103 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 104 | typedef struct |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 105 | { |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 106 | uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...). |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 107 | This parameter can be a value of @ref SPDIFRX_Data_Format */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 108 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 109 | uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 110 | This parameter can be a value of @ref SPDIFRX_Stereo_Mode */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 111 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 112 | uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 113 | This parameter can be a value of @ref SPDIFRX_PT_Mask */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 114 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 115 | uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 116 | This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 117 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 118 | uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 119 | This parameter can be a value of @ref SPDIFRX_V_Mask */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 120 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 121 | uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 122 | This parameter can be a value of @ref SPDIFRX_PE_Mask */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 123 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 124 | }SPDIFRX_SetDataFormatTypeDef; |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 125 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 126 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 127 | * @brief HAL State structures definition |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 128 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 129 | typedef enum |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 130 | { |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 131 | HAL_SPDIFRX_STATE_RESET = 0x00, /*!< SPDIFRX not yet initialized or disabled */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 132 | HAL_SPDIFRX_STATE_READY = 0x01, /*!< SPDIFRX initialized and ready for use */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 133 | HAL_SPDIFRX_STATE_BUSY = 0x02, /*!< SPDIFRX internal process is ongoing */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 134 | HAL_SPDIFRX_STATE_BUSY_RX = 0x03, /*!< SPDIFRX internal Data Flow RX process is ongoing */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 135 | HAL_SPDIFRX_STATE_BUSY_CX = 0x04, /*!< SPDIFRX internal Control Flow RX process is ongoing */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 136 | HAL_SPDIFRX_STATE_ERROR = 0x07 /*!< SPDIFRX error state */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 137 | }HAL_SPDIFRX_StateTypeDef; |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 138 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 139 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 140 | * @brief SPDIFRX handle Structure definition |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 141 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 142 | typedef struct |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 143 | { |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 144 | SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 145 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 146 | SPDIFRX_InitTypeDef Init; /* SPDIFRX communication parameters */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 147 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 148 | uint32_t *pRxBuffPtr; /* Pointer to SPDIFRX Rx transfer buffer */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 149 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 150 | uint32_t *pCsBuffPtr; /* Pointer to SPDIFRX Cx transfer buffer */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 151 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 152 | __IO uint16_t RxXferSize; /* SPDIFRX Rx transfer size */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 153 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 154 | __IO uint16_t RxXferCount; /* SPDIFRX Rx transfer counter |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 155 | (This field is initialized at the |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 156 | same value as transfer size at the |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 157 | beginning of the transfer and |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 158 | decremented when a sample is received. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 159 | NbSamplesReceived = RxBufferSize-RxBufferCount) */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 160 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 161 | __IO uint16_t CsXferSize; /* SPDIFRX Rx transfer size */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 162 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 163 | __IO uint16_t CsXferCount; /* SPDIFRX Rx transfer counter |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 164 | (This field is initialized at the |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 165 | same value as transfer size at the |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 166 | beginning of the transfer and |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 167 | decremented when a sample is received. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 168 | NbSamplesReceived = RxBufferSize-RxBufferCount) */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 169 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 170 | DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 171 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 172 | DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 173 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 174 | __IO HAL_LockTypeDef Lock; /* SPDIFRX locking object */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 175 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 176 | __IO HAL_SPDIFRX_StateTypeDef State; /* SPDIFRX communication state */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 177 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 178 | __IO uint32_t ErrorCode; /* SPDIFRX Error code */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 179 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 180 | }SPDIFRX_HandleTypeDef; |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 181 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 182 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 183 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 184 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 185 | /* Exported constants --------------------------------------------------------*/ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 186 | /** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 187 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 188 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 189 | /** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 190 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 191 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 192 | #define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 193 | #define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 194 | #define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002) /*!< OVR error */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 195 | #define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004) /*!< Parity error */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 196 | #define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008) /*!< DMA transfer error */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 197 | #define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010) /*!< Unknown Error error */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 198 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 199 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 200 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 201 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 202 | /** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 203 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 204 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 205 | #define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 206 | #define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 207 | #define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 208 | #define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 209 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 210 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 211 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 212 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 213 | /** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 214 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 215 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 216 | #define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 217 | #define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 218 | #define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 219 | #define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 220 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 221 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 222 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 223 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 224 | /** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 225 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 226 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 227 | #define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 228 | #define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 229 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 230 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 231 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 232 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 233 | /** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 234 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 235 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 236 | #define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 237 | #define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 238 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 239 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 240 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 241 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 242 | /** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 243 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 244 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 245 | #define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000) /* The channel status and user bits are copied into the SPDIF_DR */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 246 | #define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 247 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 248 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 249 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 250 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 251 | /** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 252 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 253 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 254 | #define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 255 | #define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 256 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 257 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 258 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 259 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 260 | /** @defgroup SPDIFRX_PE_Mask SPDIFRX Parity Error Mask |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 261 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 262 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 263 | #define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 264 | #define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 265 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 266 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 267 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 268 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 269 | /** @defgroup SPDIFRX_Channel_Selection SPDIFRX Channel Selection |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 270 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 271 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 272 | #define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 273 | #define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 274 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 275 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 276 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 277 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 278 | /** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 279 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 280 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 281 | #define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 282 | #define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 283 | #define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 284 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 285 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 286 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 287 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 288 | /** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 289 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 290 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 291 | #define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 292 | #define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 293 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 294 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 295 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 296 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 297 | /** @defgroup SPDIFRX_State SPDIFRX State |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 298 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 299 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 300 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 301 | #define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFC) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 302 | #define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 303 | #define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 304 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 305 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 306 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 307 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 308 | /** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 309 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 310 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 311 | #define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 312 | #define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 313 | #define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 314 | #define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 315 | #define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 316 | #define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 317 | #define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE ) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 318 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 319 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 320 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 321 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 322 | /** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 323 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 324 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 325 | #define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 326 | #define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 327 | #define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 328 | #define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 329 | #define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 330 | #define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 331 | #define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 332 | #define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 333 | #define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 334 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 335 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 336 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 337 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 338 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 339 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 340 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 341 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 342 | /* Exported macros -----------------------------------------------------------*/ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 343 | /** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 344 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 345 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 346 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 347 | /** @brief Reset SPDIFRX handle state |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 348 | * @param __HANDLE__: SPDIFRX handle. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 349 | * @retval None |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 350 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 351 | #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 352 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 353 | /** @brief Disable the specified SPDIFRX peripheral (IDLE State). |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 354 | * @param __HANDLE__: specifies the SPDIFRX Handle. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 355 | * @retval None |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 356 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 357 | #define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 358 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 359 | /** @brief Enable the specified SPDIFRX peripheral (SYNC State). |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 360 | * @param __HANDLE__: specifies the SPDIFRX Handle. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 361 | * @retval None |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 362 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 363 | #define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 364 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 365 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 366 | /** @brief Enable the specified SPDIFRX peripheral (RCV State). |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 367 | * @param __HANDLE__: specifies the SPDIFRX Handle. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 368 | * @retval None |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 369 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 370 | #define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 371 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 372 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 373 | /** @brief Enable or disable the specified SPDIFRX interrupts. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 374 | * @param __HANDLE__: specifies the SPDIFRX Handle. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 375 | * @param __INTERRUPT__: specifies the interrupt source to enable or disable. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 376 | * This parameter can be one of the following values: |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 377 | * @arg SPDIFRX_IT_RXNE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 378 | * @arg SPDIFRX_IT_CSRNE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 379 | * @arg SPDIFRX_IT_PERRIE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 380 | * @arg SPDIFRX_IT_OVRIE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 381 | * @arg SPDIFRX_IT_SBLKIE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 382 | * @arg SPDIFRX_IT_SYNCDIE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 383 | * @arg SPDIFRX_IT_IFEIE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 384 | * @retval None |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 385 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 386 | #define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 387 | #define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__))) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 388 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 389 | /** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 390 | * @param __HANDLE__: specifies the SPDIFRX Handle. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 391 | * @param __INTERRUPT__: specifies the SPDIFRX interrupt source to check. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 392 | * This parameter can be one of the following values: |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 393 | * @arg SPDIFRX_IT_RXNE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 394 | * @arg SPDIFRX_IT_CSRNE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 395 | * @arg SPDIFRX_IT_PERRIE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 396 | * @arg SPDIFRX_IT_OVRIE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 397 | * @arg SPDIFRX_IT_SBLKIE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 398 | * @arg SPDIFRX_IT_SYNCDIE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 399 | * @arg SPDIFRX_IT_IFEIE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 400 | * @retval The new state of __IT__ (TRUE or FALSE). |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 401 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 402 | #define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 403 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 404 | /** @brief Checks whether the specified SPDIFRX flag is set or not. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 405 | * @param __HANDLE__: specifies the SPDIFRX Handle. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 406 | * @param __FLAG__: specifies the flag to check. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 407 | * This parameter can be one of the following values: |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 408 | * @arg SPDIFRX_FLAG_RXNE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 409 | * @arg SPDIFRX_FLAG_CSRNE |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 410 | * @arg SPDIFRX_FLAG_PERR |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 411 | * @arg SPDIFRX_FLAG_OVR |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 412 | * @arg SPDIFRX_FLAG_SBD |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 413 | * @arg SPDIFRX_FLAG_SYNCD |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 414 | * @arg SPDIFRX_FLAG_FERR |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 415 | * @arg SPDIFRX_FLAG_SERR |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 416 | * @arg SPDIFRX_FLAG_TERR |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 417 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 418 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 419 | #define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 420 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 421 | /** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 422 | * @param __HANDLE__: specifies the USART Handle. |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 423 | * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 424 | * to clear the corresponding interrupt |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 425 | * This parameter can be one of the following values: |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 426 | * @arg SPDIFRX_FLAG_PERR |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 427 | * @arg SPDIFRX_FLAG_OVR |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 428 | * @arg SPDIFRX_SR_SBD |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 429 | * @arg SPDIFRX_SR_SYNCD |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 430 | * @retval None |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 431 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 432 | #define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__)) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 433 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 434 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 435 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 436 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 437 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 438 | /* Exported functions --------------------------------------------------------*/ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 439 | /** @addtogroup SPDIFRX_Exported_Functions |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 440 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 441 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 442 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 443 | /** @addtogroup SPDIFRX_Exported_Functions_Group1 |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 444 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 445 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 446 | /* Initialization/de-initialization functions **********************************/ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 447 | HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 448 | HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 449 | void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 450 | void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 451 | HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 452 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 453 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 454 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 455 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 456 | /** @addtogroup SPDIFRX_Exported_Functions_Group2 |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 457 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 458 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 459 | /* I/O operation functions ***************************************************/ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 460 | /* Blocking mode: Polling */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 461 | HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 462 | HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 463 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 464 | /* Non-Blocking mode: Interrupt */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 465 | HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 466 | HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 467 | void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 468 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 469 | /* Non-Blocking mode: DMA */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 470 | HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 471 | HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 472 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 473 | HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 474 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 475 | /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 476 | void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 477 | void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 478 | void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 479 | void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 480 | void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 481 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 482 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 483 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 484 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 485 | /** @addtogroup SPDIFRX_Exported_Functions_Group3 |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 486 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 487 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 488 | /* Peripheral Control and State functions ************************************/ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 489 | HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 490 | uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif); |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 491 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 492 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 493 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 494 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 495 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 496 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 497 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 498 | /* Private types -------------------------------------------------------------*/ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 499 | /* Private variables ---------------------------------------------------------*/ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 500 | /* Private constants ---------------------------------------------------------*/ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 501 | /* Private macros ------------------------------------------------------------*/ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 502 | /** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 503 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 504 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 505 | #define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 506 | ((INPUT) == SPDIFRX_INPUT_IN2) || \ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 507 | ((INPUT) == SPDIFRX_INPUT_IN3) || \ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 508 | ((INPUT) == SPDIFRX_INPUT_IN0)) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 509 | #define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 510 | ((RET) == SPDIFRX_MAXRETRIES_3) || \ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 511 | ((RET) == SPDIFRX_MAXRETRIES_15) || \ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 512 | ((RET) == SPDIFRX_MAXRETRIES_63)) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 513 | #define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 514 | ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF)) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 515 | #define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 516 | ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF)) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 517 | #define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 518 | ((VAL) == SPDIFRX_VALIDITYMASK_ON)) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 519 | #define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 520 | ((VAL) == SPDIFRX_PARITYERRORMASK_ON)) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 521 | #define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 522 | ((CHANNEL) == SPDIFRX_CHANNEL_B)) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 523 | #define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 524 | ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 525 | ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS)) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 526 | #define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 527 | ((MODE) == SPDIFRX_STEREOMODE_ENABLE)) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 528 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 529 | #define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 530 | ((VAL) == SPDIFRX_CHANNELSTATUS_OFF)) |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 531 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 532 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 533 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 534 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 535 | /* Private functions ---------------------------------------------------------*/ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 536 | /** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 537 | * @{ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 538 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 539 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 540 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 541 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 542 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 543 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 544 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 545 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 546 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 547 | /** |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 548 | * @} |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 549 | */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 550 | #endif /* STM32F446xx */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 551 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 552 | #ifdef __cplusplus |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 553 | } |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 554 | #endif |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 555 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 556 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 557 | #endif /* __STM32F4xx_HAL_SPDIFRX_H */ |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 558 | |
| group-UVic-Assistive-Technolog | 0:3a767f41cf04 | 559 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |