File content as of revision 42:3ae73b61f657:

//-------------------------------------------------------------------------------
// 
//  Treehouse Designs Inc.
//  Colorado Springs, Colorado
// 
//  Copyright (c) 2018 by Treehouse Designs Inc. 
//  Copyright (c) 2018 by Agility Power Systems Inc. 
// 
//  This code is the property of Treehouse Designs, Inc. (Treehouse) and
//  Agility Power Systems Inc. (Agility) and may not be redistributed
//  in any form without prior written permission from 
//  both copyright holders, Treehouse and Agility.
//
//  The above copyright notice and this permission notice shall be included in
//  all copies or substantial portions of the Software.
// 
//   
//-------------------------------------------------------------------------------
// 
//  REVISION HISTORY:
//  
//   $Author: $
//   $Rev: $
//   $Date: $
//   $URL: $
// 
//-------------------------------------------------------------------------------

#include "mbed.h"
#include "all_io.h"
#include "PortOut.h"

// Digital IO
//
// Slots 12 to 0 are activated with the wr_out signals
// wr_out[13] = slots[12:0]
// BusOut signals are specified LSB first
//BusOut wr_out(PA_10, PA_11, PA_12, PA_13, PA_14, PA_15, PC_6, PC_7, PC_8, PC_9, PC_10, PC_11, PC_12); //RK: Need to change ADC inputs to PC_0-PC_5

// en_out are binary weighted signals that activate groups of DC-DC converters on the slot cards.
// en_out[6] = {en32, en16, en8, en4, en2, en1}
//BusOut en_out(PA_9, PA_8, PA_7, PA_6, PC_14, PA_4); //RK: debug 11/26/2018
//BusOut signals are specified LSB first
//BusOut en_out(PA_4, PC_13, PA_6, PA_7, PA_8, PA_9);
//DigitalIn pc14(PC_14);
I2C i2c(PB_6, PB_7);


// Expansion port signals
// eport[16] = eport[18:3]
//DigitalIn  eport[16] = {PB_15, PB_14, PB_13, PB_12, PC_15, PB_10, PB_9, PB_8, PB_7, PB_6, PB_5, PB_4, PB_3, PB_2, PB_1, PB_0}; //RK 11/24/2018 PB_11 throws an error. Identifier "PB_11" is undefined. PB_11 is connected to VCAP1.
DigitalInOut SWDIO(PA_13);
DigitalOut fan_on(PA_15);
AnalogOut vdac(PA_4);

// Use extchlat to latch new wr_out signals to the external slots via ribbon cable.
//DigitalOut extchlat(PA_1);
DigitalOut ec2(PC_0);
DigitalOut ec15(PC_1);
DigitalOut ec28(PC_2);
DigitalOut ec6(PC_3);
DigitalOut ec12(PC_4);
DigitalOut ec25(PC_5);
DigitalOut ec36(PC_6);
DigitalOut ec31(PC_7);
DigitalOut ec9(PC_8);
DigitalOut ec5(PC_9);
DigitalOut ec24(PC_10);
DigitalOut ec11(PC_11);
DigitalOut ec1(PC_12);
DigitalOut ec10(PC_13);
DigitalOut ec23(PC_14);
DigitalOut ec7(PC_15);
DigitalOut ec18(PA_8);
DigitalOut ec14(PA_9);
DigitalOut ec27(PA_10);
DigitalOut ec19(PA_11);
DigitalOut ec32(PA_12);
DigitalOut ec35(PB_0);
DigitalOut ec21(PB_1);
DigitalOut ec30(PB_2);
DigitalOut ec33(PB_4);
DigitalOut ec20(PB_5);
DigitalOut ec34(PB_8);
DigitalOut ec29(PB_9);
DigitalOut ec8(PB_10);
DigitalOut ec4(PB_11);
DigitalOut ec17(PB_12);
DigitalOut ec13(PB_13);
DigitalOut ec26(PB_14);
DigitalOut ec22(PB_15);

// all_on indicates that the load demanded a high amount of current and all DC-DC converters are enabled.
//DigitalIn  all_on(PA_0);
DigitalIn ILR_enable(PA_0);
DigitalIn SWDCLK(PA_14);
DigitalIn fan_pwn(PB_3);
DigitalIn MS(PA_1);

// Analog IO
//
AnalogIn VIN48(PA_7);
AnalogIn VIN12(PA_6);
AnalogIn IIN12(PA_5);