Diff: src/all_io.cpp

Revision:

0:b3410a1e9843

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/all_io.cpp	Thu Jan 27 21:58:14 2022 +0000
@@ -0,0 +1,76 @@
+//-------------------------------------------------------------------------------
+// 
+//  Treehouse Designs Inc.
+//  Colorado Springs, Colorado
+// 
+//  Copyright (c) 2018 by Treehouse Designs Inc. 
+//  Copyright (c) 2018 by Agility Power Systems Inc. 
+// 
+//  This code is the property of Treehouse Designs, Inc. (Treehouse) and
+//  Agility Power Systems Inc. (Agility) and may not be redistributed
+//  in any form without prior written permission from 
+//  both copyright holders, Treehouse and Agility.
+//
+//  The above copyright notice and this permission notice shall be included in
+//  all copies or substantial portions of the Software.
+// 
+//   
+//-------------------------------------------------------------------------------
+// 
+//  REVISION HISTORY:
+//  
+//   $Author: $
+//   $Rev: $
+//   $Date: $
+//   $URL: $
+// 
+//-------------------------------------------------------------------------------
+
+#include "mbed.h"
+#include "all_io.h"
+#include "PortOut.h"
+
+// Digital IO
+
+DigitalInOut SWDIO(PA_13);
+PwmOut fan_pwm(PB_3);
+DigitalOut fan_on(PA_15);
+AnalogOut vdac(PA_4);
+
+// Use extchlat to latch new wr_out signals to the external slots via ribbon cable.
+//DigitalOut extchlat(PA_1);
+/*DigitalOut ec[] = {(PC_0), (PC_1), (PC_2), (PC_3), (PC_4), (PC_5), (PC_6), (PC_7), (PC_8), (PC_9), (PC_10), (PC_11), (PC_12), (PC_13), (PC_14), (PC_15),
+(PA_8), (PA_9), (PA_10), (PA_11), (PA_12), (PB_0), (PB_1), (PB_2), (PB_4), (PB_5), (PB_8), (PB_9), (PB_10), (PB_11), (PB_12), (PB_13), (PB_14), (PB_15),
+(PH_0), (PH_1)};*/
+/*DigitalOut en1(PC_7);
+DigitalOut en2(PC_6);
+DigitalOut en4(PB_15);
+DigitalOut en8(PB_14);
+DigitalOut en16(PB_13);
+DigitalOut en32(PB_12);*/
+DigitalOut en[] = {(PC_7), (PC_6), (PB_15), (PB_14), (PB_13), (PB_12)};
+DigitalOut ALLON(PA_10);
+DigitalOut WR(PA_9);
+
+// all_on indicates that the load demanded a high amount of current and all DC-DC converters are enabled.
+//DigitalIn  all_on(PA_0);
+InterruptIn ILR_enable(PA_0);
+DigitalIn SWDCLK(PA_14);
+DigitalIn MS(PA_1);
+//DigitalIn UART_TX(PA_2);
+//DigitalIn UART_RX(PA_3);
+//Serial chip2221(PA_2, PA_3);
+//DigitalIn I2C_SCL(PB_6);
+//DigitalIn I2C_SDA(PB_7);
+
+// Analog IO
+//
+AnalogIn adc_temp(ADC_TEMP);
+AnalogIn adc_vref(ADC_VREF);
+#if defined(TARGET_DISCO_F051R8) || defined(TARGET_NUCLEO_F030R8) || defined(TARGET_NUCLEO_F031K6) || defined(TARGET_NUCLEO_F042K6) || defined(TARGET_NUCLEO_F070RB) || defined(TARGET_NUCLEO_F072RB) || defined(TARGET_NUCLEO_F091RC) || defined(TARGET_NUCLEO_F207ZG) || defined(TARGET_NUCLEO_F302R8) || defined(TARGET_NUCLEO_F303K8) || defined(TARGET_DISCO_F303VC) || defined(TARGET_NUCLEO_F303RE) || defined(TARGET_NUCLEO_F303ZE) || defined(TARGET_DISCO_F334C8) || defined(TARGET_NUCLEO_F334R8) || defined(TARGET_MTS_DRAGONFLY_F411RE) || defined(TARGET_MTS_MDOT_F405RG) || defined(TARGET_MTS_MDOT_F411RE) || defined(TARGET_DISCO_F401VC) || defined(TARGET_NUCLEO_F401RE) || defined(TARGET_ARCH_MAX) || defined(TARGET_DISCO_F407VG) || defined(TARGET_NUCLEO_F410RB) || defined(TARGET_ELMO_F411RE) || defined(TARGET_NUCLEO_F411RE) || defined(TARGET_NUCLEO_F412ZG) || defined(TARGET_DISCO_F413ZH) || defined(TARGET_DISCO_F429ZI) || defined(TARGET_NUCLEO_F429ZI) || defined(TARGET_NUCLEO_F439ZI) || defined(TARGET_B96B_F446VE) || defined(TARGET_NUCLEO_F446RE) || defined(TARGET_NUCLEO_F446ZE) || defined(TARGET_DISCO_F469NI) || defined(TARGET_DISCO_F746NG) || defined(TARGET_NUCLEO_F746ZG) || defined(TARGET_NUCLEO_F756ZG) || defined(TARGET_NUCLEO_F767ZI) || defined(TARGET_DISCO_F769NI) || defined(TARGET_DISCO_L072CZ_LRWAN1) || defined(TARGET_NUCLEO_L432KC) || defined(TARGET_DISCO_L476VG) || defined(TARGET_NUCLEO_L476RG) || defined(TARGET_NUCLEO_L486RG) 
+AnalogIn adc_vbat(ADC_VBAT); // Warning: Not available on all devices
+#endif
+AnalogIn TESTERPIN(PC_2);
+AnalogIn VIN48(PA_7);
+AnalogIn VIN12(PA_6);
+AnalogIn IIN12(PA_5);
\ No newline at end of file