The Best / FT800_beyondtek

configured for beyondtek displays

Dependents:   datalogger_ft810

Fork of FT800_3 by The Best

FT_Gpu_Hal.cpp@10:39d32e09742d, 2016-08-15 (annotated)

Committer:
cpm219
Date:
Mon Aug 15 15:32:32 2016 +0000
Revision:
10:39d32e09742d
Parent:
9:567b41b360f2 
no change

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dreschpe 2:ab74a9a05970 1 /* mbed Library for FTDI FT800 Enbedded Video Engine "EVE"
dreschpe 3:392d2c733c68 2 * based on Original Code Sample from FTDI
dreschpe 2:ab74a9a05970 3 * ported to mbed by Peter Drescher, DC2PD 2014
dreschpe 3:392d2c733c68 4 * Released under the MIT License: http://mbed.org/license/mit
dreschpe 3:392d2c733c68 5 * 19.09.14 changed to shorter function names
dreschpe 3:392d2c733c68 6 * FTDI was using very long names.
dreschpe 3:392d2c733c68 7 * Ft_App_Flush_Co_Buffer -> Flush_Co_Buffer ... */
dreschpe 3:392d2c733c68 8
dreschpe 0:5e013296b353 9 #include "FT_Platform.h"
dreschpe 0:5e013296b353 10 #include "mbed.h"
dreschpe 0:5e013296b353 11 #include "FT_LCD_Type.h"
davidchilds 7:a69ac4d39afd 12 Serial pc(USBTX, USBRX);
dreschpe 0:5e013296b353 13
dreschpe 0:5e013296b353 14 FT800::FT800(PinName mosi,
dreschpe 0:5e013296b353 15 PinName miso,
dreschpe 0:5e013296b353 16 PinName sck,
dreschpe 0:5e013296b353 17 PinName ss,
dreschpe 0:5e013296b353 18 PinName intr,
dreschpe 0:5e013296b353 19 PinName pd)
dreschpe 3:392d2c733c68 20 :
dreschpe 3:392d2c733c68 21 _spi(mosi, miso, sck),
dreschpe 0:5e013296b353 22 _ss(ss),
dreschpe 3:392d2c733c68 23 _pd(pd),
dreschpe 3:392d2c733c68 24 _f800_isr(InterruptIn(intr))
dreschpe 0:5e013296b353 25 {
dreschpe 0:5e013296b353 26 _spi.format(8,0); // 8 bit spi mode 0
davidchilds 7:a69ac4d39afd 27 _spi.frequency(1000000); // start with 10 Mhz SPI clock
dreschpe 0:5e013296b353 28 _ss = 1; // cs high
dreschpe 3:392d2c733c68 29 _pd = 1; // PD high
dreschpe 3:392d2c733c68 30 Bootup();
dreschpe 0:5e013296b353 31 }
dreschpe 0:5e013296b353 32
dreschpe 0:5e013296b353 33
dreschpe 0:5e013296b353 34 ft_bool_t FT800::Bootup(void){
dreschpe 3:392d2c733c68 35 Open();
dreschpe 0:5e013296b353 36 BootupConfig();
dreschpe 3:392d2c733c68 37
dreschpe 0:5e013296b353 38 return(1);
dreschpe 0:5e013296b353 39 }
dreschpe 3:392d2c733c68 40
dreschpe 0:5e013296b353 41
dreschpe 0:5e013296b353 42 ft_void_t FT800::BootupConfig(void){
dreschpe 0:5e013296b353 43 ft_uint8_t chipid;
dreschpe 0:5e013296b353 44 /* Do a power cycle for safer side */
dreschpe 3:392d2c733c68 45 Powercycle( FT_TRUE);
cpm219 9:567b41b360f2 46 /*
cpm219 9:567b41b360f2 47 7/8/16: Curt added the sleep delay below...
cpm219 9:567b41b360f2 48 */
cpm219 9:567b41b360f2 49 // Sleep(30);
cpm219 9:567b41b360f2 50
dreschpe 0:5e013296b353 51 /* Set the clk to external clock */
dreschpe 3:392d2c733c68 52 HostCommand( FT_GPU_EXTERNAL_OSC);
dreschpe 3:392d2c733c68 53 Sleep(10);
davidchilds 7:a69ac4d39afd 54
davidchilds 7:a69ac4d39afd 55 /* Access address 0 to wake up the FT800 */
davidchilds 7:a69ac4d39afd 56 HostCommand( FT_GPU_ACTIVE_M);
davidchilds 7:a69ac4d39afd 57 Sleep(500);
dreschpe 0:5e013296b353 58
dreschpe 0:5e013296b353 59 /* Switch PLL output to 48MHz */
davidchilds 7:a69ac4d39afd 60 // HostCommand( FT_GPU_PLL_48M);
dreschpe 3:392d2c733c68 61 Sleep(10);
dreschpe 0:5e013296b353 62
dreschpe 0:5e013296b353 63 /* Do a core reset for safer side */
dreschpe 3:392d2c733c68 64 HostCommand( FT_GPU_CORE_RESET);
davidchilds 7:a69ac4d39afd 65 Sleep(500);
dreschpe 3:392d2c733c68 66 //Read Register ID to check if FT800 is ready.
dreschpe 3:392d2c733c68 67 chipid = Rd8( REG_ID);
davidchilds 7:a69ac4d39afd 68 // chipid = Rd8(0x0C0000);
davidchilds 7:a69ac4d39afd 69 pc.printf("ID%08X\n", chipid);
dreschpe 0:5e013296b353 70 while(chipid != 0x7C)
dreschpe 3:392d2c733c68 71
dreschpe 0:5e013296b353 72
dreschpe 3:392d2c733c68 73 // Speed up
cpm219 9:567b41b360f2 74 _spi.frequency(20000000); // 20 Mhz SPI clock DC
cpm219 9:567b41b360f2 75 // _spi.frequency(12000000); // 12 Mhz SPI clock
dreschpe 0:5e013296b353 76 /* Configuration of LCD display */
dreschpe 3:392d2c733c68 77 DispHCycle = my_DispHCycle;
dreschpe 3:392d2c733c68 78 Wr16( REG_HCYCLE, DispHCycle);
dreschpe 3:392d2c733c68 79 DispHOffset = my_DispHOffset;
dreschpe 3:392d2c733c68 80 Wr16( REG_HOFFSET, DispHOffset);
dreschpe 3:392d2c733c68 81 DispWidth = my_DispWidth;
dreschpe 3:392d2c733c68 82 Wr16( REG_HSIZE, DispWidth);
dreschpe 3:392d2c733c68 83 DispHSync0 = my_DispHSync0;
dreschpe 3:392d2c733c68 84 Wr16( REG_HSYNC0, DispHSync0);
dreschpe 3:392d2c733c68 85 DispHSync1 = my_DispHSync1;
dreschpe 3:392d2c733c68 86 Wr16( REG_HSYNC1, DispHSync1);
dreschpe 3:392d2c733c68 87 DispVCycle = my_DispVCycle;
dreschpe 3:392d2c733c68 88 Wr16( REG_VCYCLE, DispVCycle);
dreschpe 3:392d2c733c68 89 DispVOffset = my_DispVOffset;
dreschpe 3:392d2c733c68 90 Wr16( REG_VOFFSET, DispVOffset);
dreschpe 3:392d2c733c68 91 DispHeight = my_DispHeight;
dreschpe 3:392d2c733c68 92 Wr16( REG_VSIZE, DispHeight);
dreschpe 3:392d2c733c68 93 DispVSync0 = my_DispVSync0;
dreschpe 3:392d2c733c68 94 Wr16( REG_VSYNC0, DispVSync0);
dreschpe 3:392d2c733c68 95 DispVSync1 = my_DispVSync1;
dreschpe 3:392d2c733c68 96 Wr16( REG_VSYNC1, DispVSync1);
dreschpe 3:392d2c733c68 97 DispSwizzle = my_DispSwizzle;
dreschpe 4:363ec27cdfaa 98 Wr8( REG_SWIZZLE, DispSwizzle);
dreschpe 3:392d2c733c68 99 DispPCLKPol = my_DispPCLKPol;
dreschpe 4:363ec27cdfaa 100 Wr8( REG_PCLK_POL, DispPCLKPol);
cpm219 9:567b41b360f2 101 Wr8( REG_CSPREAD, 0);
dreschpe 3:392d2c733c68 102 DispPCLK = my_DispPCLK;
dreschpe 4:363ec27cdfaa 103 Wr8( REG_PCLK, DispPCLK);//after this display is visible on the LCD
dreschpe 0:5e013296b353 104
cpm219 9:567b41b360f2 105 Wr16( REG_PWM_HZ, 10000);
dreschpe 3:392d2c733c68 106
dreschpe 3:392d2c733c68 107 #ifdef Inv_Backlite // turn on backlite
dreschpe 3:392d2c733c68 108 Wr16( REG_PWM_DUTY, 0);
dreschpe 0:5e013296b353 109 #else
dreschpe 3:392d2c733c68 110 Wr16( REG_PWM_DUTY, 100);
dreschpe 3:392d2c733c68 111 #endif
dreschpe 3:392d2c733c68 112
dreschpe 3:392d2c733c68 113 Wr8( REG_GPIO_DIR,0x82); //| Rd8( REG_GPIO_DIR));
dreschpe 3:392d2c733c68 114 Wr8( REG_GPIO,0x080); //| Rd8( REG_GPIO));
dreschpe 3:392d2c733c68 115
dreschpe 3:392d2c733c68 116 Wr32( RAM_DL, CLEAR(1,1,1));
dreschpe 3:392d2c733c68 117 Wr32( RAM_DL+4, DISPLAY());
dreschpe 3:392d2c733c68 118 Wr32( REG_DLSWAP,1);
dreschpe 3:392d2c733c68 119
dreschpe 3:392d2c733c68 120 Wr16( REG_PCLK, DispPCLK);
dreschpe 3:392d2c733c68 121
dreschpe 0:5e013296b353 122 /* Touch configuration - configure the resistance value to 1200 - this value is specific to customer requirement and derived by experiment */
montgojj 8:4601ccd8a927 123 Wr16( REG_TOUCH_RZTHRESH,2400);
dreschpe 0:5e013296b353 124
dreschpe 0:5e013296b353 125 }
dreschpe 0:5e013296b353 126
dreschpe 0:5e013296b353 127
dreschpe 0:5e013296b353 128
dreschpe 0:5e013296b353 129 /* API to initialize the SPI interface */
dreschpe 3:392d2c733c68 130 ft_bool_t FT800::Init()
dreschpe 0:5e013296b353 131 {
dreschpe 0:5e013296b353 132 // is done in constructor
dreschpe 0:5e013296b353 133 return 1;
dreschpe 0:5e013296b353 134 }
dreschpe 0:5e013296b353 135
dreschpe 0:5e013296b353 136
dreschpe 3:392d2c733c68 137 ft_bool_t FT800::Open()
dreschpe 0:5e013296b353 138 {
dreschpe 3:392d2c733c68 139 cmd_fifo_wp = dl_buff_wp = 0;
dreschpe 3:392d2c733c68 140 status = OPENED;
dreschpe 0:5e013296b353 141 return 1;
dreschpe 0:5e013296b353 142 }
dreschpe 0:5e013296b353 143
dreschpe 3:392d2c733c68 144 ft_void_t FT800::Close( )
dreschpe 0:5e013296b353 145 {
dreschpe 3:392d2c733c68 146 status = CLOSED;
dreschpe 0:5e013296b353 147 }
dreschpe 0:5e013296b353 148
dreschpe 3:392d2c733c68 149 ft_void_t FT800::DeInit()
dreschpe 0:5e013296b353 150 {
dreschpe 0:5e013296b353 151
dreschpe 0:5e013296b353 152 }
dreschpe 0:5e013296b353 153
dreschpe 0:5e013296b353 154 /*The APIs for reading/writing transfer continuously only with small buffer system*/
dreschpe 3:392d2c733c68 155 ft_void_t FT800::StartTransfer( FT_GPU_TRANSFERDIR_T rw,ft_uint32_t addr)
dreschpe 0:5e013296b353 156 {
dreschpe 0:5e013296b353 157 if (FT_GPU_READ == rw){
dreschpe 0:5e013296b353 158 _ss = 0; // cs low
dreschpe 0:5e013296b353 159 _spi.write(addr >> 16);
dreschpe 0:5e013296b353 160 _spi.write(addr >> 8);
dreschpe 0:5e013296b353 161 _spi.write(addr & 0xff);
dreschpe 0:5e013296b353 162 _spi.write(0); //Dummy Read Byte
dreschpe 3:392d2c733c68 163 status = READING;
dreschpe 0:5e013296b353 164 }else{
dreschpe 0:5e013296b353 165 _ss = 0; // cs low
dreschpe 0:5e013296b353 166 _spi.write(0x80 | (addr >> 16));
dreschpe 0:5e013296b353 167 _spi.write(addr >> 8);
dreschpe 0:5e013296b353 168 _spi.write(addr & 0xff);
dreschpe 3:392d2c733c68 169 status = WRITING;
dreschpe 0:5e013296b353 170 }
dreschpe 0:5e013296b353 171 }
dreschpe 0:5e013296b353 172
dreschpe 0:5e013296b353 173
dreschpe 0:5e013296b353 174 /*The APIs for writing transfer continuously only*/
dreschpe 3:392d2c733c68 175 ft_void_t FT800::StartCmdTransfer( FT_GPU_TRANSFERDIR_T rw, ft_uint16_t count)
dreschpe 0:5e013296b353 176 {
dreschpe 3:392d2c733c68 177 StartTransfer( rw, cmd_fifo_wp + RAM_CMD);
dreschpe 0:5e013296b353 178 }
dreschpe 0:5e013296b353 179
dreschpe 3:392d2c733c68 180 ft_uint8_t FT800::TransferString( const ft_char8_t *string)
dreschpe 0:5e013296b353 181 {
dreschpe 0:5e013296b353 182 ft_uint16_t length = strlen(string);
dreschpe 0:5e013296b353 183 while(length --){
dreschpe 3:392d2c733c68 184 Transfer8( *string);
dreschpe 0:5e013296b353 185 string ++;
dreschpe 0:5e013296b353 186 }
dreschpe 0:5e013296b353 187 //Append one null as ending flag
dreschpe 3:392d2c733c68 188 Transfer8( 0);
dreschpe 3:392d2c733c68 189 return(1);
dreschpe 0:5e013296b353 190 }
dreschpe 0:5e013296b353 191
dreschpe 0:5e013296b353 192
dreschpe 3:392d2c733c68 193 ft_uint8_t FT800::Transfer8( ft_uint8_t value)
dreschpe 0:5e013296b353 194 {
dreschpe 3:392d2c733c68 195 return _spi.write(value);
dreschpe 0:5e013296b353 196 }
dreschpe 0:5e013296b353 197
dreschpe 0:5e013296b353 198
dreschpe 3:392d2c733c68 199 ft_uint16_t FT800::Transfer16( ft_uint16_t value)
dreschpe 0:5e013296b353 200 {
dreschpe 0:5e013296b353 201 ft_uint16_t retVal = 0;
dreschpe 0:5e013296b353 202
dreschpe 3:392d2c733c68 203 if (status == WRITING){
dreschpe 3:392d2c733c68 204 Transfer8( value & 0xFF);//LSB first
dreschpe 3:392d2c733c68 205 Transfer8( (value >> 8) & 0xFF);
dreschpe 0:5e013296b353 206 }else{
dreschpe 3:392d2c733c68 207 retVal = Transfer8( 0);
dreschpe 3:392d2c733c68 208 retVal |= (ft_uint16_t)Transfer8( 0) << 8;
dreschpe 0:5e013296b353 209 }
dreschpe 0:5e013296b353 210
dreschpe 0:5e013296b353 211 return retVal;
dreschpe 0:5e013296b353 212 }
dreschpe 0:5e013296b353 213
dreschpe 3:392d2c733c68 214 ft_uint32_t FT800::Transfer32( ft_uint32_t value)
dreschpe 0:5e013296b353 215 {
dreschpe 0:5e013296b353 216 ft_uint32_t retVal = 0;
dreschpe 3:392d2c733c68 217 if (status == WRITING){
dreschpe 3:392d2c733c68 218 Transfer16( value & 0xFFFF);//LSB first
dreschpe 3:392d2c733c68 219 Transfer16( (value >> 16) & 0xFFFF);
dreschpe 0:5e013296b353 220 }else{
dreschpe 3:392d2c733c68 221 retVal = Transfer16( 0);
dreschpe 3:392d2c733c68 222 retVal |= (ft_uint32_t)Transfer16( 0) << 16;
dreschpe 0:5e013296b353 223 }
dreschpe 0:5e013296b353 224 return retVal;
dreschpe 0:5e013296b353 225 }
dreschpe 0:5e013296b353 226
dreschpe 3:392d2c733c68 227 ft_void_t FT800::EndTransfer( )
dreschpe 0:5e013296b353 228 {
dreschpe 3:392d2c733c68 229 _ss = 1;
dreschpe 3:392d2c733c68 230 status = OPENED;
dreschpe 0:5e013296b353 231 }
dreschpe 0:5e013296b353 232
dreschpe 0:5e013296b353 233
dreschpe 3:392d2c733c68 234 ft_uint8_t FT800::Rd8( ft_uint32_t addr)
dreschpe 0:5e013296b353 235 {
dreschpe 0:5e013296b353 236 ft_uint8_t value;
dreschpe 3:392d2c733c68 237 StartTransfer( FT_GPU_READ,addr);
dreschpe 3:392d2c733c68 238 value = Transfer8( 0);
dreschpe 3:392d2c733c68 239 EndTransfer( );
dreschpe 0:5e013296b353 240 return value;
dreschpe 0:5e013296b353 241 }
dreschpe 3:392d2c733c68 242 ft_uint16_t FT800::Rd16( ft_uint32_t addr)
dreschpe 0:5e013296b353 243 {
dreschpe 0:5e013296b353 244 ft_uint16_t value;
dreschpe 3:392d2c733c68 245 StartTransfer( FT_GPU_READ,addr);
dreschpe 3:392d2c733c68 246 value = Transfer16( 0);
dreschpe 3:392d2c733c68 247 EndTransfer( );
dreschpe 0:5e013296b353 248 return value;
dreschpe 0:5e013296b353 249 }
dreschpe 3:392d2c733c68 250 ft_uint32_t FT800::Rd32( ft_uint32_t addr)
dreschpe 0:5e013296b353 251 {
dreschpe 0:5e013296b353 252 ft_uint32_t value;
dreschpe 3:392d2c733c68 253 StartTransfer( FT_GPU_READ,addr);
dreschpe 3:392d2c733c68 254 value = Transfer32( 0);
dreschpe 3:392d2c733c68 255 EndTransfer( );
dreschpe 0:5e013296b353 256 return value;
dreschpe 0:5e013296b353 257 }
dreschpe 0:5e013296b353 258
dreschpe 3:392d2c733c68 259 ft_void_t FT800::Wr8( ft_uint32_t addr, ft_uint8_t v)
dreschpe 3:392d2c733c68 260 {
dreschpe 3:392d2c733c68 261 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 3:392d2c733c68 262 Transfer8( v);
dreschpe 3:392d2c733c68 263 EndTransfer( );
dreschpe 0:5e013296b353 264 }
dreschpe 3:392d2c733c68 265 ft_void_t FT800::Wr16( ft_uint32_t addr, ft_uint16_t v)
dreschpe 0:5e013296b353 266 {
dreschpe 3:392d2c733c68 267 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 3:392d2c733c68 268 Transfer16( v);
dreschpe 3:392d2c733c68 269 EndTransfer( );
dreschpe 0:5e013296b353 270 }
dreschpe 3:392d2c733c68 271 ft_void_t FT800::Wr32( ft_uint32_t addr, ft_uint32_t v)
dreschpe 0:5e013296b353 272 {
dreschpe 3:392d2c733c68 273 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 3:392d2c733c68 274 Transfer32( v);
dreschpe 3:392d2c733c68 275 EndTransfer( );
dreschpe 0:5e013296b353 276 }
dreschpe 0:5e013296b353 277
dreschpe 3:392d2c733c68 278 ft_void_t FT800::HostCommand( ft_uint8_t cmd)
dreschpe 0:5e013296b353 279 {
dreschpe 0:5e013296b353 280 _ss = 0;
dreschpe 0:5e013296b353 281 _spi.write(cmd);
dreschpe 0:5e013296b353 282 _spi.write(0);
dreschpe 0:5e013296b353 283 _spi.write(0);
dreschpe 0:5e013296b353 284 _ss = 1;
dreschpe 0:5e013296b353 285 }
dreschpe 0:5e013296b353 286
dreschpe 3:392d2c733c68 287 ft_void_t FT800::ClockSelect( FT_GPU_PLL_SOURCE_T pllsource)
dreschpe 0:5e013296b353 288 {
dreschpe 3:392d2c733c68 289 HostCommand( pllsource);
dreschpe 0:5e013296b353 290 }
dreschpe 0:5e013296b353 291
dreschpe 3:392d2c733c68 292 ft_void_t FT800::PLL_FreqSelect( FT_GPU_PLL_FREQ_T freq)
dreschpe 0:5e013296b353 293 {
dreschpe 3:392d2c733c68 294 HostCommand( freq);
dreschpe 0:5e013296b353 295 }
dreschpe 0:5e013296b353 296
dreschpe 3:392d2c733c68 297 ft_void_t FT800::PowerModeSwitch( FT_GPU_POWER_MODE_T pwrmode)
dreschpe 0:5e013296b353 298 {
dreschpe 3:392d2c733c68 299 HostCommand( pwrmode);
dreschpe 0:5e013296b353 300 }
dreschpe 0:5e013296b353 301
dreschpe 3:392d2c733c68 302 ft_void_t FT800::CoreReset( )
dreschpe 0:5e013296b353 303 {
dreschpe 3:392d2c733c68 304 HostCommand( 0x68);
dreschpe 0:5e013296b353 305 }
dreschpe 0:5e013296b353 306
dreschpe 0:5e013296b353 307
dreschpe 3:392d2c733c68 308 ft_void_t FT800::Updatecmdfifo( ft_uint16_t count)
dreschpe 0:5e013296b353 309 {
dreschpe 3:392d2c733c68 310 cmd_fifo_wp = ( cmd_fifo_wp + count) & 4095;
dreschpe 0:5e013296b353 311 //4 byte alignment
dreschpe 3:392d2c733c68 312 cmd_fifo_wp = ( cmd_fifo_wp + 3) & 0xffc;
dreschpe 3:392d2c733c68 313 Wr16( REG_CMD_WRITE, cmd_fifo_wp);
dreschpe 0:5e013296b353 314 }
dreschpe 0:5e013296b353 315
dreschpe 0:5e013296b353 316
dreschpe 3:392d2c733c68 317 ft_uint16_t FT800::fifo_Freespace( )
dreschpe 0:5e013296b353 318 {
dreschpe 0:5e013296b353 319 ft_uint16_t fullness,retval;
dreschpe 0:5e013296b353 320
dreschpe 3:392d2c733c68 321 fullness = ( cmd_fifo_wp - Rd16( REG_CMD_READ)) & 4095;
dreschpe 0:5e013296b353 322 retval = (FT_CMD_FIFO_SIZE - 4) - fullness;
dreschpe 0:5e013296b353 323 return (retval);
dreschpe 0:5e013296b353 324 }
dreschpe 0:5e013296b353 325
dreschpe 3:392d2c733c68 326 ft_void_t FT800::WrCmdBuf( ft_uint8_t *buffer,ft_uint16_t count)
dreschpe 0:5e013296b353 327 {
dreschpe 3:392d2c733c68 328 ft_uint32_t length =0, SizeTransfered = 0;
dreschpe 0:5e013296b353 329
dreschpe 3:392d2c733c68 330 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
dreschpe 3:392d2c733c68 331 do {
dreschpe 0:5e013296b353 332 length = count;
dreschpe 0:5e013296b353 333 if (length > MAX_CMD_FIFO_TRANSFER){
dreschpe 0:5e013296b353 334 length = MAX_CMD_FIFO_TRANSFER;
dreschpe 0:5e013296b353 335 }
dreschpe 3:392d2c733c68 336 CheckCmdBuffer( length);
dreschpe 0:5e013296b353 337
dreschpe 3:392d2c733c68 338 StartCmdTransfer( FT_GPU_WRITE,length);
dreschpe 0:5e013296b353 339
dreschpe 0:5e013296b353 340 SizeTransfered = 0;
dreschpe 0:5e013296b353 341 while (length--) {
dreschpe 3:392d2c733c68 342 Transfer8( *buffer);
dreschpe 0:5e013296b353 343 buffer++;
dreschpe 0:5e013296b353 344 SizeTransfered ++;
dreschpe 0:5e013296b353 345 }
dreschpe 0:5e013296b353 346 length = SizeTransfered;
dreschpe 0:5e013296b353 347
dreschpe 3:392d2c733c68 348 EndTransfer( );
dreschpe 3:392d2c733c68 349 Updatecmdfifo( length);
dreschpe 0:5e013296b353 350
dreschpe 3:392d2c733c68 351 WaitCmdfifo_empty( );
dreschpe 0:5e013296b353 352
dreschpe 0:5e013296b353 353 count -= length;
dreschpe 0:5e013296b353 354 }while (count > 0);
dreschpe 0:5e013296b353 355 }
dreschpe 0:5e013296b353 356
dreschpe 0:5e013296b353 357
dreschpe 3:392d2c733c68 358 ft_void_t FT800::WrCmdBufFromFlash( FT_PROGMEM ft_prog_uchar8_t *buffer,ft_uint16_t count)
dreschpe 0:5e013296b353 359 {
dreschpe 3:392d2c733c68 360 ft_uint32_t length =0, SizeTransfered = 0;
dreschpe 0:5e013296b353 361
dreschpe 3:392d2c733c68 362 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
dreschpe 3:392d2c733c68 363 do {
dreschpe 0:5e013296b353 364 length = count;
dreschpe 0:5e013296b353 365 if (length > MAX_CMD_FIFO_TRANSFER){
dreschpe 0:5e013296b353 366 length = MAX_CMD_FIFO_TRANSFER;
dreschpe 0:5e013296b353 367 }
dreschpe 3:392d2c733c68 368 CheckCmdBuffer( length);
dreschpe 0:5e013296b353 369
dreschpe 3:392d2c733c68 370 StartCmdTransfer( FT_GPU_WRITE,length);
dreschpe 0:5e013296b353 371
dreschpe 0:5e013296b353 372
dreschpe 0:5e013296b353 373 SizeTransfered = 0;
dreschpe 0:5e013296b353 374 while (length--) {
dreschpe 3:392d2c733c68 375 Transfer8( ft_pgm_read_byte_near(buffer));
dreschpe 0:5e013296b353 376 buffer++;
dreschpe 0:5e013296b353 377 SizeTransfered ++;
dreschpe 0:5e013296b353 378 }
dreschpe 0:5e013296b353 379 length = SizeTransfered;
dreschpe 0:5e013296b353 380
dreschpe 3:392d2c733c68 381 EndTransfer( );
dreschpe 3:392d2c733c68 382 Updatecmdfifo( length);
dreschpe 0:5e013296b353 383
dreschpe 3:392d2c733c68 384 WaitCmdfifo_empty( );
dreschpe 0:5e013296b353 385
dreschpe 0:5e013296b353 386 count -= length;
dreschpe 0:5e013296b353 387 }while (count > 0);
dreschpe 0:5e013296b353 388 }
dreschpe 0:5e013296b353 389
dreschpe 0:5e013296b353 390
dreschpe 3:392d2c733c68 391 ft_void_t FT800::CheckCmdBuffer( ft_uint16_t count)
dreschpe 0:5e013296b353 392 {
dreschpe 0:5e013296b353 393 ft_uint16_t getfreespace;
dreschpe 0:5e013296b353 394 do{
dreschpe 3:392d2c733c68 395 getfreespace = fifo_Freespace( );
dreschpe 0:5e013296b353 396 }while(getfreespace < count);
dreschpe 0:5e013296b353 397 }
dreschpe 0:5e013296b353 398
dreschpe 3:392d2c733c68 399 ft_void_t FT800::WaitCmdfifo_empty( )
dreschpe 0:5e013296b353 400 {
dreschpe 3:392d2c733c68 401 while(Rd16( REG_CMD_READ) != Rd16( REG_CMD_WRITE));
dreschpe 3:392d2c733c68 402
dreschpe 3:392d2c733c68 403 cmd_fifo_wp = Rd16( REG_CMD_WRITE);
dreschpe 0:5e013296b353 404 }
dreschpe 0:5e013296b353 405
dreschpe 3:392d2c733c68 406 ft_void_t FT800::WaitLogo_Finish( )
dreschpe 0:5e013296b353 407 {
dreschpe 0:5e013296b353 408 ft_int16_t cmdrdptr,cmdwrptr;
dreschpe 0:5e013296b353 409
dreschpe 0:5e013296b353 410 do{
dreschpe 3:392d2c733c68 411 cmdrdptr = Rd16( REG_CMD_READ);
dreschpe 3:392d2c733c68 412 cmdwrptr = Rd16( REG_CMD_WRITE);
dreschpe 0:5e013296b353 413 }while ((cmdwrptr != cmdrdptr) || (cmdrdptr != 0));
dreschpe 3:392d2c733c68 414 cmd_fifo_wp = 0;
dreschpe 0:5e013296b353 415 }
dreschpe 0:5e013296b353 416
dreschpe 0:5e013296b353 417
dreschpe 3:392d2c733c68 418 ft_void_t FT800::ResetCmdFifo( )
dreschpe 0:5e013296b353 419 {
dreschpe 3:392d2c733c68 420 cmd_fifo_wp = 0;
dreschpe 0:5e013296b353 421 }
dreschpe 0:5e013296b353 422
dreschpe 0:5e013296b353 423
dreschpe 3:392d2c733c68 424 ft_void_t FT800::WrCmd32( ft_uint32_t cmd)
dreschpe 0:5e013296b353 425 {
dreschpe 3:392d2c733c68 426 CheckCmdBuffer( sizeof(cmd));
dreschpe 3:392d2c733c68 427
dreschpe 3:392d2c733c68 428 Wr32( RAM_CMD + cmd_fifo_wp,cmd);
dreschpe 3:392d2c733c68 429
dreschpe 3:392d2c733c68 430 Updatecmdfifo( sizeof(cmd));
dreschpe 0:5e013296b353 431 }
dreschpe 0:5e013296b353 432
dreschpe 0:5e013296b353 433
dreschpe 3:392d2c733c68 434 ft_void_t FT800::ResetDLBuffer( )
dreschpe 0:5e013296b353 435 {
dreschpe 3:392d2c733c68 436 dl_buff_wp = 0;
dreschpe 0:5e013296b353 437 }
dreschpe 0:5e013296b353 438
dreschpe 0:5e013296b353 439 /* Toggle PD_N pin of FT800 board for a power cycle*/
dreschpe 3:392d2c733c68 440 ft_void_t FT800::Powercycle( ft_bool_t up)
dreschpe 0:5e013296b353 441 {
dreschpe 0:5e013296b353 442 if (up)
dreschpe 0:5e013296b353 443 {
dreschpe 3:392d2c733c68 444 //Toggle PD_N from low to high for power up switch
dreschpe 3:392d2c733c68 445 _pd = 0;
dreschpe 3:392d2c733c68 446 Sleep(20);
dreschpe 0:5e013296b353 447
dreschpe 0:5e013296b353 448 _pd = 1;
dreschpe 3:392d2c733c68 449 Sleep(20);
dreschpe 0:5e013296b353 450 }else
dreschpe 0:5e013296b353 451 {
dreschpe 0:5e013296b353 452 //Toggle PD_N from high to low for power down switch
dreschpe 0:5e013296b353 453 _pd = 1;
dreschpe 3:392d2c733c68 454 Sleep(20);
dreschpe 3:392d2c733c68 455
dreschpe 0:5e013296b353 456 _pd = 0;
dreschpe 3:392d2c733c68 457 Sleep(20);
dreschpe 0:5e013296b353 458 }
dreschpe 0:5e013296b353 459 }
dreschpe 0:5e013296b353 460
dreschpe 3:392d2c733c68 461 ft_void_t FT800::WrMemFromFlash( ft_uint32_t addr,const ft_prog_uchar8_t *buffer, ft_uint32_t length)
dreschpe 0:5e013296b353 462 {
dreschpe 3:392d2c733c68 463 //ft_uint32_t SizeTransfered = 0;
dreschpe 0:5e013296b353 464
dreschpe 3:392d2c733c68 465 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 0:5e013296b353 466
dreschpe 0:5e013296b353 467 while (length--) {
dreschpe 3:392d2c733c68 468 Transfer8( ft_pgm_read_byte_near(buffer));
dreschpe 0:5e013296b353 469 buffer++;
dreschpe 0:5e013296b353 470 }
dreschpe 0:5e013296b353 471
dreschpe 3:392d2c733c68 472 EndTransfer( );
dreschpe 0:5e013296b353 473 }
dreschpe 0:5e013296b353 474
dreschpe 3:392d2c733c68 475 ft_void_t FT800::WrMem( ft_uint32_t addr,const ft_uint8_t *buffer, ft_uint32_t length)
dreschpe 0:5e013296b353 476 {
dreschpe 3:392d2c733c68 477 //ft_uint32_t SizeTransfered = 0;
dreschpe 0:5e013296b353 478
dreschpe 3:392d2c733c68 479 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 0:5e013296b353 480
dreschpe 0:5e013296b353 481 while (length--) {
dreschpe 3:392d2c733c68 482 Transfer8( *buffer);
dreschpe 0:5e013296b353 483 buffer++;
dreschpe 0:5e013296b353 484 }
dreschpe 0:5e013296b353 485
dreschpe 3:392d2c733c68 486 EndTransfer( );
dreschpe 0:5e013296b353 487 }
dreschpe 0:5e013296b353 488
dreschpe 0:5e013296b353 489
dreschpe 3:392d2c733c68 490 ft_void_t FT800::RdMem( ft_uint32_t addr, ft_uint8_t *buffer, ft_uint32_t length)
dreschpe 0:5e013296b353 491 {
dreschpe 3:392d2c733c68 492 //ft_uint32_t SizeTransfered = 0;
dreschpe 0:5e013296b353 493
dreschpe 3:392d2c733c68 494 StartTransfer( FT_GPU_READ,addr);
dreschpe 0:5e013296b353 495
dreschpe 0:5e013296b353 496 while (length--) {
dreschpe 3:392d2c733c68 497 *buffer = Transfer8( 0);
dreschpe 0:5e013296b353 498 buffer++;
dreschpe 0:5e013296b353 499 }
dreschpe 0:5e013296b353 500
dreschpe 3:392d2c733c68 501 EndTransfer( );
dreschpe 0:5e013296b353 502 }
dreschpe 0:5e013296b353 503
dreschpe 3:392d2c733c68 504 ft_int32_t FT800::Dec2Ascii(ft_char8_t *pSrc,ft_int32_t value)
dreschpe 0:5e013296b353 505 {
dreschpe 0:5e013296b353 506 ft_int16_t Length;
dreschpe 0:5e013296b353 507 ft_char8_t *pdst,charval;
dreschpe 0:5e013296b353 508 ft_int32_t CurrVal = value,tmpval,i;
dreschpe 0:5e013296b353 509 ft_char8_t tmparray[16],idx = 0;
dreschpe 0:5e013296b353 510
dreschpe 0:5e013296b353 511 Length = strlen(pSrc);
dreschpe 0:5e013296b353 512 pdst = pSrc + Length;
dreschpe 0:5e013296b353 513
dreschpe 0:5e013296b353 514 if(0 == value)
dreschpe 0:5e013296b353 515 {
dreschpe 0:5e013296b353 516 *pdst++ = '0';
dreschpe 0:5e013296b353 517 *pdst++ = '\0';
dreschpe 0:5e013296b353 518 return 0;
dreschpe 0:5e013296b353 519 }
dreschpe 0:5e013296b353 520
dreschpe 0:5e013296b353 521 if(CurrVal < 0)
dreschpe 0:5e013296b353 522 {
dreschpe 0:5e013296b353 523 *pdst++ = '-';
dreschpe 0:5e013296b353 524 CurrVal = - CurrVal;
dreschpe 0:5e013296b353 525 }
dreschpe 0:5e013296b353 526 /* insert the value */
dreschpe 0:5e013296b353 527 while(CurrVal > 0){
dreschpe 0:5e013296b353 528 tmpval = CurrVal;
dreschpe 0:5e013296b353 529 CurrVal /= 10;
dreschpe 0:5e013296b353 530 tmpval = tmpval - CurrVal*10;
dreschpe 0:5e013296b353 531 charval = '0' + tmpval;
dreschpe 0:5e013296b353 532 tmparray[idx++] = charval;
dreschpe 0:5e013296b353 533 }
dreschpe 0:5e013296b353 534
dreschpe 0:5e013296b353 535 for(i=0;i<idx;i++)
dreschpe 0:5e013296b353 536 {
dreschpe 0:5e013296b353 537 *pdst++ = tmparray[idx - i - 1];
dreschpe 0:5e013296b353 538 }
dreschpe 0:5e013296b353 539 *pdst++ = '\0';
dreschpe 0:5e013296b353 540
dreschpe 0:5e013296b353 541 return 0;
dreschpe 0:5e013296b353 542 }
dreschpe 0:5e013296b353 543
dreschpe 0:5e013296b353 544
dreschpe 3:392d2c733c68 545 ft_void_t FT800::Sleep(ft_uint16_t ms)
dreschpe 0:5e013296b353 546 {
dreschpe 0:5e013296b353 547 wait_ms(ms);
dreschpe 0:5e013296b353 548 }
dreschpe 0:5e013296b353 549
dreschpe 3:392d2c733c68 550 ft_void_t FT800::Sound_ON(){
dreschpe 3:392d2c733c68 551 Wr8( REG_GPIO, 0x02 | Rd8( REG_GPIO));
dreschpe 1:bd671a31e765 552 }
dreschpe 1:bd671a31e765 553
dreschpe 3:392d2c733c68 554 ft_void_t FT800::Sound_OFF(){
dreschpe 3:392d2c733c68 555 Wr8( REG_GPIO, 0xFD & Rd8( REG_GPIO));
dreschpe 1:bd671a31e765 556 }
dreschpe 0:5e013296b353 557
dreschpe 0:5e013296b353 558
dreschpe 0:5e013296b353 559
dreschpe 1:bd671a31e765 560