TeamSurface / Praktikum_3

Mit TaskWait ;-)

EncoderCounter.cpp@0:92d57d5d9305, 2018-03-23 (annotated)

Committer:
wannesim
Date:
Fri Mar 23 15:44:15 2018 +0000
Revision:
0:92d57d5d9305
Mit TaskWait     ;-)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wannesim 0:92d57d5d9305 1 /*
wannesim 0:92d57d5d9305 2 * EncoderCounter.cpp
wannesim 0:92d57d5d9305 3 * Copyright (c) 2018, ZHAW
wannesim 0:92d57d5d9305 4 * All rights reserved.
wannesim 0:92d57d5d9305 5 */
wannesim 0:92d57d5d9305 6
wannesim 0:92d57d5d9305 7 #include "EncoderCounter.h"
wannesim 0:92d57d5d9305 8
wannesim 0:92d57d5d9305 9 using namespace std;
wannesim 0:92d57d5d9305 10
wannesim 0:92d57d5d9305 11 /**
wannesim 0:92d57d5d9305 12 * Creates and initializes the driver to read the quadrature
wannesim 0:92d57d5d9305 13 * encoder counter of the STM32 microcontroller.
wannesim 0:92d57d5d9305 14 * @param a the input pin for the channel A.
wannesim 0:92d57d5d9305 15 * @param b the input pin for the channel B.
wannesim 0:92d57d5d9305 16 */
wannesim 0:92d57d5d9305 17 EncoderCounter::EncoderCounter(PinName a, PinName b) {
wannesim 0:92d57d5d9305 18
wannesim 0:92d57d5d9305 19 // check pins
wannesim 0:92d57d5d9305 20
wannesim 0:92d57d5d9305 21 if ((a == PA_0) && (b == PA_1)) {
wannesim 0:92d57d5d9305 22
wannesim 0:92d57d5d9305 23 // pinmap OK for TIM2 CH1 and CH2
wannesim 0:92d57d5d9305 24
wannesim 0:92d57d5d9305 25 TIM = TIM2;
wannesim 0:92d57d5d9305 26
wannesim 0:92d57d5d9305 27 // configure general purpose I/O registers
wannesim 0:92d57d5d9305 28
wannesim 0:92d57d5d9305 29 GPIOA->MODER &= ~GPIO_MODER_MODER0; // reset port A0
wannesim 0:92d57d5d9305 30 GPIOA->MODER |= GPIO_MODER_MODER0_1; // set alternate mode of port A0
wannesim 0:92d57d5d9305 31 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR0; // reset pull-up/pull-down on port A0
wannesim 0:92d57d5d9305 32 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR0_1; // set input as pull-down
wannesim 0:92d57d5d9305 33 GPIOA->AFR[0] &= ~(0xF << 4*0); // reset alternate function of port A0
wannesim 0:92d57d5d9305 34 GPIOA->AFR[0] |= 1 << 4*0; // set alternate funtion 1 of port A0
wannesim 0:92d57d5d9305 35
wannesim 0:92d57d5d9305 36 GPIOA->MODER &= ~GPIO_MODER_MODER1; // reset port A1
wannesim 0:92d57d5d9305 37 GPIOA->MODER |= GPIO_MODER_MODER1_1; // set alternate mode of port A1
wannesim 0:92d57d5d9305 38 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR1; // reset pull-up/pull-down on port A1
wannesim 0:92d57d5d9305 39 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR1_1; // set input as pull-down
wannesim 0:92d57d5d9305 40 GPIOA->AFR[0] &= ~(0xF << 4*1); // reset alternate function of port A1
wannesim 0:92d57d5d9305 41 GPIOA->AFR[0] |= 1 << 4*1; // set alternate funtion 1 of port A1
wannesim 0:92d57d5d9305 42
wannesim 0:92d57d5d9305 43 // configure reset and clock control registers
wannesim 0:92d57d5d9305 44
wannesim 0:92d57d5d9305 45 RCC->APB1RSTR |= RCC_APB1RSTR_TIM2RST; //reset TIM2 controller
wannesim 0:92d57d5d9305 46 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM2RST;
wannesim 0:92d57d5d9305 47
wannesim 0:92d57d5d9305 48 RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // TIM2 clock enable
wannesim 0:92d57d5d9305 49
wannesim 0:92d57d5d9305 50 } else if ((a == PA_6) && (b == PC_7)) {
wannesim 0:92d57d5d9305 51
wannesim 0:92d57d5d9305 52 // pinmap OK for TIM3 CH1 and CH2
wannesim 0:92d57d5d9305 53
wannesim 0:92d57d5d9305 54 TIM = TIM3;
wannesim 0:92d57d5d9305 55
wannesim 0:92d57d5d9305 56 // configure reset and clock control registers
wannesim 0:92d57d5d9305 57
wannesim 0:92d57d5d9305 58 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // manually enable port C (port A enabled by mbed library)
wannesim 0:92d57d5d9305 59
wannesim 0:92d57d5d9305 60 // configure general purpose I/O registers
wannesim 0:92d57d5d9305 61
wannesim 0:92d57d5d9305 62 GPIOA->MODER &= ~GPIO_MODER_MODER6; // reset port A6
wannesim 0:92d57d5d9305 63 GPIOA->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port A6
wannesim 0:92d57d5d9305 64 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port A6
wannesim 0:92d57d5d9305 65 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
wannesim 0:92d57d5d9305 66 GPIOA->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port A6
wannesim 0:92d57d5d9305 67 GPIOA->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port A6
wannesim 0:92d57d5d9305 68
wannesim 0:92d57d5d9305 69 GPIOC->MODER &= ~GPIO_MODER_MODER7; // reset port C7
wannesim 0:92d57d5d9305 70 GPIOC->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port C7
wannesim 0:92d57d5d9305 71 GPIOC->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port C7
wannesim 0:92d57d5d9305 72 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
wannesim 0:92d57d5d9305 73 GPIOC->AFR[0] &= ~0xF0000000; // reset alternate function of port C7
wannesim 0:92d57d5d9305 74 GPIOC->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port C7
wannesim 0:92d57d5d9305 75
wannesim 0:92d57d5d9305 76 // configure reset and clock control registers
wannesim 0:92d57d5d9305 77
wannesim 0:92d57d5d9305 78 RCC->APB1RSTR |= RCC_APB1RSTR_TIM3RST; //reset TIM3 controller
wannesim 0:92d57d5d9305 79 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM3RST;
wannesim 0:92d57d5d9305 80
wannesim 0:92d57d5d9305 81 RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // TIM3 clock enable
wannesim 0:92d57d5d9305 82
wannesim 0:92d57d5d9305 83 } else if ((a == PB_6) && (b == PB_7)) {
wannesim 0:92d57d5d9305 84
wannesim 0:92d57d5d9305 85 // pinmap OK for TIM4 CH1 and CH2
wannesim 0:92d57d5d9305 86
wannesim 0:92d57d5d9305 87 TIM = TIM4;
wannesim 0:92d57d5d9305 88
wannesim 0:92d57d5d9305 89 // configure reset and clock control registers
wannesim 0:92d57d5d9305 90
wannesim 0:92d57d5d9305 91 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // manually enable port B (port A enabled by mbed library)
wannesim 0:92d57d5d9305 92
wannesim 0:92d57d5d9305 93 // configure general purpose I/O registers
wannesim 0:92d57d5d9305 94
wannesim 0:92d57d5d9305 95 GPIOB->MODER &= ~GPIO_MODER_MODER6; // reset port B6
wannesim 0:92d57d5d9305 96 GPIOB->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port B6
wannesim 0:92d57d5d9305 97 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port B6
wannesim 0:92d57d5d9305 98 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
wannesim 0:92d57d5d9305 99 GPIOB->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port B6
wannesim 0:92d57d5d9305 100 GPIOB->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port B6
wannesim 0:92d57d5d9305 101
wannesim 0:92d57d5d9305 102 GPIOB->MODER &= ~GPIO_MODER_MODER7; // reset port B7
wannesim 0:92d57d5d9305 103 GPIOB->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port B7
wannesim 0:92d57d5d9305 104 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port B7
wannesim 0:92d57d5d9305 105 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
wannesim 0:92d57d5d9305 106 GPIOB->AFR[0] &= ~0xF0000000; // reset alternate function of port B7
wannesim 0:92d57d5d9305 107 GPIOB->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port B7
wannesim 0:92d57d5d9305 108
wannesim 0:92d57d5d9305 109 // configure reset and clock control registers
wannesim 0:92d57d5d9305 110
wannesim 0:92d57d5d9305 111 RCC->APB1RSTR |= RCC_APB1RSTR_TIM4RST; //reset TIM4 controller
wannesim 0:92d57d5d9305 112 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM4RST;
wannesim 0:92d57d5d9305 113
wannesim 0:92d57d5d9305 114 RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // TIM4 clock enable
wannesim 0:92d57d5d9305 115
wannesim 0:92d57d5d9305 116 } else {
wannesim 0:92d57d5d9305 117
wannesim 0:92d57d5d9305 118 printf("pinmap not found for peripheral\n");
wannesim 0:92d57d5d9305 119 }
wannesim 0:92d57d5d9305 120
wannesim 0:92d57d5d9305 121 // configure general purpose timer 3 or 4
wannesim 0:92d57d5d9305 122
wannesim 0:92d57d5d9305 123 TIM->CR1 = 0x0000; // counter disable
wannesim 0:92d57d5d9305 124 TIM->CR2 = 0x0000; // reset master mode selection
wannesim 0:92d57d5d9305 125 TIM->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; // counting on both TI1 & TI2 edges
wannesim 0:92d57d5d9305 126 TIM->CCMR1 = TIM_CCMR1_CC2S_0 | TIM_CCMR1_CC1S_0;
wannesim 0:92d57d5d9305 127 TIM->CCMR2 = 0x0000; // reset capture mode register 2
wannesim 0:92d57d5d9305 128 TIM->CCER = TIM_CCER_CC2E | TIM_CCER_CC1E;
wannesim 0:92d57d5d9305 129 TIM->CNT = 0x0000; // reset counter value
wannesim 0:92d57d5d9305 130 TIM->ARR = 0xFFFF; // auto reload register
wannesim 0:92d57d5d9305 131 TIM->CR1 = TIM_CR1_CEN; // counter enable
wannesim 0:92d57d5d9305 132 }
wannesim 0:92d57d5d9305 133
wannesim 0:92d57d5d9305 134 EncoderCounter::~EncoderCounter() {}
wannesim 0:92d57d5d9305 135
wannesim 0:92d57d5d9305 136 /**
wannesim 0:92d57d5d9305 137 * Resets the counter value to zero.
wannesim 0:92d57d5d9305 138 */
wannesim 0:92d57d5d9305 139 void EncoderCounter::reset() {
wannesim 0:92d57d5d9305 140
wannesim 0:92d57d5d9305 141 TIM->CNT = 0x0000;
wannesim 0:92d57d5d9305 142 }
wannesim 0:92d57d5d9305 143
wannesim 0:92d57d5d9305 144 /**
wannesim 0:92d57d5d9305 145 * Resets the counter value to a given offset value.
wannesim 0:92d57d5d9305 146 * @param offset the offset value to reset the counter to.
wannesim 0:92d57d5d9305 147 */
wannesim 0:92d57d5d9305 148 void EncoderCounter::reset(short offset) {
wannesim 0:92d57d5d9305 149
wannesim 0:92d57d5d9305 150 TIM->CNT = -offset;
wannesim 0:92d57d5d9305 151 }
wannesim 0:92d57d5d9305 152
wannesim 0:92d57d5d9305 153 /**
wannesim 0:92d57d5d9305 154 * Reads the quadrature encoder counter value.
wannesim 0:92d57d5d9305 155 * @return the quadrature encoder counter as a signed 16-bit integer value.
wannesim 0:92d57d5d9305 156 */
wannesim 0:92d57d5d9305 157 short EncoderCounter::read() {
wannesim 0:92d57d5d9305 158
wannesim 0:92d57d5d9305 159 return (short)(-TIM->CNT);
wannesim 0:92d57d5d9305 160 }
wannesim 0:92d57d5d9305 161
wannesim 0:92d57d5d9305 162 /**
wannesim 0:92d57d5d9305 163 * The empty operator is a shorthand notation of the <code>read()</code> method.
wannesim 0:92d57d5d9305 164 */
wannesim 0:92d57d5d9305 165 EncoderCounter::operator short() {
wannesim 0:92d57d5d9305 166
wannesim 0:92d57d5d9305 167 return read();
wannesim 0:92d57d5d9305 168 }
wannesim 0:92d57d5d9305 169