TeamGyro / mbed-rtos

OS2

Dependents:   GYRO_MPU6050 Bluetooth_Powered_Multimeter_Using_STM32F429_and_RTOS fyp

targets/TARGET_NXP/mbed_rtx4.h@0:a7c449cd2d5a, 2020-02-03 (annotated)

Committer:
guilhemMBED
Date:
Mon Feb 03 13:41:14 2020 +0000
Revision:
0:a7c449cd2d5a
previous version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
guilhemMBED 0:a7c449cd2d5a 1 /* mbed Microcontroller Library
guilhemMBED 0:a7c449cd2d5a 2 * Copyright (c) 2016 ARM Limited
guilhemMBED 0:a7c449cd2d5a 3 *
guilhemMBED 0:a7c449cd2d5a 4 * Licensed under the Apache License, Version 2.0 (the "License");
guilhemMBED 0:a7c449cd2d5a 5 * you may not use this file except in compliance with the License.
guilhemMBED 0:a7c449cd2d5a 6 * You may obtain a copy of the License at
guilhemMBED 0:a7c449cd2d5a 7 *
guilhemMBED 0:a7c449cd2d5a 8 * http://www.apache.org/licenses/LICENSE-2.0
guilhemMBED 0:a7c449cd2d5a 9 *
guilhemMBED 0:a7c449cd2d5a 10 * Unless required by applicable law or agreed to in writing, software
guilhemMBED 0:a7c449cd2d5a 11 * distributed under the License is distributed on an "AS IS" BASIS,
guilhemMBED 0:a7c449cd2d5a 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
guilhemMBED 0:a7c449cd2d5a 13 * See the License for the specific language governing permissions and
guilhemMBED 0:a7c449cd2d5a 14 * limitations under the License.
guilhemMBED 0:a7c449cd2d5a 15 */
guilhemMBED 0:a7c449cd2d5a 16
guilhemMBED 0:a7c449cd2d5a 17 #ifndef MBED_MBED_RTX_H
guilhemMBED 0:a7c449cd2d5a 18 #define MBED_MBED_RTX_H
guilhemMBED 0:a7c449cd2d5a 19
guilhemMBED 0:a7c449cd2d5a 20 #if defined(TARGET_LPC11U68)
guilhemMBED 0:a7c449cd2d5a 21
guilhemMBED 0:a7c449cd2d5a 22 #ifndef INITIAL_SP
guilhemMBED 0:a7c449cd2d5a 23 #define INITIAL_SP (0x10008000UL)
guilhemMBED 0:a7c449cd2d5a 24 #endif
guilhemMBED 0:a7c449cd2d5a 25
guilhemMBED 0:a7c449cd2d5a 26 // RTX 4 only config below, for backward-compability
guilhemMBED 0:a7c449cd2d5a 27
guilhemMBED 0:a7c449cd2d5a 28 #ifndef OS_TASKCNT
guilhemMBED 0:a7c449cd2d5a 29 #define OS_TASKCNT 14
guilhemMBED 0:a7c449cd2d5a 30 #endif
guilhemMBED 0:a7c449cd2d5a 31 #ifndef OS_MAINSTKSIZE
guilhemMBED 0:a7c449cd2d5a 32 #define OS_MAINSTKSIZE 256
guilhemMBED 0:a7c449cd2d5a 33 #endif
guilhemMBED 0:a7c449cd2d5a 34 #ifndef OS_CLOCK
guilhemMBED 0:a7c449cd2d5a 35 #define OS_CLOCK 48000000
guilhemMBED 0:a7c449cd2d5a 36 #endif
guilhemMBED 0:a7c449cd2d5a 37
guilhemMBED 0:a7c449cd2d5a 38 #elif defined(TARGET_LPC11U24) \
guilhemMBED 0:a7c449cd2d5a 39 || defined(TARGET_LPC11U35_401) \
guilhemMBED 0:a7c449cd2d5a 40 || defined(TARGET_LPC11U35_501) \
guilhemMBED 0:a7c449cd2d5a 41 || defined(TARGET_LPCCAPPUCCINO)
guilhemMBED 0:a7c449cd2d5a 42
guilhemMBED 0:a7c449cd2d5a 43 #ifndef INITIAL_SP
guilhemMBED 0:a7c449cd2d5a 44 #define INITIAL_SP (0x10002000UL)
guilhemMBED 0:a7c449cd2d5a 45 #endif
guilhemMBED 0:a7c449cd2d5a 46
guilhemMBED 0:a7c449cd2d5a 47 // RTX 4 only config below, for backward-compability
guilhemMBED 0:a7c449cd2d5a 48
guilhemMBED 0:a7c449cd2d5a 49 #ifndef OS_TASKCNT
guilhemMBED 0:a7c449cd2d5a 50 #define OS_TASKCNT 6
guilhemMBED 0:a7c449cd2d5a 51 #endif
guilhemMBED 0:a7c449cd2d5a 52 #ifndef OS_MAINSTKSIZE
guilhemMBED 0:a7c449cd2d5a 53 #define OS_MAINSTKSIZE 128
guilhemMBED 0:a7c449cd2d5a 54 #endif
guilhemMBED 0:a7c449cd2d5a 55 #ifndef OS_CLOCK
guilhemMBED 0:a7c449cd2d5a 56 #define OS_CLOCK 48000000
guilhemMBED 0:a7c449cd2d5a 57 #endif
guilhemMBED 0:a7c449cd2d5a 58
guilhemMBED 0:a7c449cd2d5a 59 #elif defined(TARGET_LPC1114)
guilhemMBED 0:a7c449cd2d5a 60
guilhemMBED 0:a7c449cd2d5a 61 #ifndef INITIAL_SP
guilhemMBED 0:a7c449cd2d5a 62 #define INITIAL_SP (0x10001000UL)
guilhemMBED 0:a7c449cd2d5a 63 #endif
guilhemMBED 0:a7c449cd2d5a 64
guilhemMBED 0:a7c449cd2d5a 65 // RTX 4 only config below, for backward-compability
guilhemMBED 0:a7c449cd2d5a 66
guilhemMBED 0:a7c449cd2d5a 67 #ifndef OS_TASKCNT
guilhemMBED 0:a7c449cd2d5a 68 #define OS_TASKCNT 6
guilhemMBED 0:a7c449cd2d5a 69 #endif
guilhemMBED 0:a7c449cd2d5a 70 #ifndef OS_MAINSTKSIZE
guilhemMBED 0:a7c449cd2d5a 71 #define OS_MAINSTKSIZE 128
guilhemMBED 0:a7c449cd2d5a 72 #endif
guilhemMBED 0:a7c449cd2d5a 73 #ifndef OS_CLOCK
guilhemMBED 0:a7c449cd2d5a 74 #define OS_CLOCK 48000000
guilhemMBED 0:a7c449cd2d5a 75 #endif
guilhemMBED 0:a7c449cd2d5a 76
guilhemMBED 0:a7c449cd2d5a 77 #elif defined(TARGET_LPC1347)
guilhemMBED 0:a7c449cd2d5a 78
guilhemMBED 0:a7c449cd2d5a 79 #ifndef INITIAL_SP
guilhemMBED 0:a7c449cd2d5a 80 #define INITIAL_SP (0x10002000UL)
guilhemMBED 0:a7c449cd2d5a 81 #endif
guilhemMBED 0:a7c449cd2d5a 82
guilhemMBED 0:a7c449cd2d5a 83 // RTX 4 only config below, for backward-compability
guilhemMBED 0:a7c449cd2d5a 84
guilhemMBED 0:a7c449cd2d5a 85 #ifndef OS_TASKCNT
guilhemMBED 0:a7c449cd2d5a 86 #define OS_TASKCNT 14
guilhemMBED 0:a7c449cd2d5a 87 #endif
guilhemMBED 0:a7c449cd2d5a 88 #ifndef OS_MAINSTKSIZE
guilhemMBED 0:a7c449cd2d5a 89 #define OS_MAINSTKSIZE 256
guilhemMBED 0:a7c449cd2d5a 90 #endif
guilhemMBED 0:a7c449cd2d5a 91 #ifndef OS_CLOCK
guilhemMBED 0:a7c449cd2d5a 92 #define OS_CLOCK 72000000
guilhemMBED 0:a7c449cd2d5a 93 #endif
guilhemMBED 0:a7c449cd2d5a 94
guilhemMBED 0:a7c449cd2d5a 95 #elif defined(TARGET_LPC1549)
guilhemMBED 0:a7c449cd2d5a 96
guilhemMBED 0:a7c449cd2d5a 97 #ifndef INITIAL_SP
guilhemMBED 0:a7c449cd2d5a 98 #define INITIAL_SP (0x02009000UL)
guilhemMBED 0:a7c449cd2d5a 99 #endif
guilhemMBED 0:a7c449cd2d5a 100
guilhemMBED 0:a7c449cd2d5a 101 // RTX 4 only config below, for backward-compability
guilhemMBED 0:a7c449cd2d5a 102
guilhemMBED 0:a7c449cd2d5a 103 #ifndef OS_TASKCNT
guilhemMBED 0:a7c449cd2d5a 104 #define OS_TASKCNT 14
guilhemMBED 0:a7c449cd2d5a 105 #endif
guilhemMBED 0:a7c449cd2d5a 106 #ifndef OS_MAINSTKSIZE
guilhemMBED 0:a7c449cd2d5a 107 #define OS_MAINSTKSIZE 256
guilhemMBED 0:a7c449cd2d5a 108 #endif
guilhemMBED 0:a7c449cd2d5a 109 #ifndef OS_CLOCK
guilhemMBED 0:a7c449cd2d5a 110 #define OS_CLOCK 72000000
guilhemMBED 0:a7c449cd2d5a 111 #endif
guilhemMBED 0:a7c449cd2d5a 112
guilhemMBED 0:a7c449cd2d5a 113 #elif defined(TARGET_LPC1768)
guilhemMBED 0:a7c449cd2d5a 114
guilhemMBED 0:a7c449cd2d5a 115 #ifndef INITIAL_SP
guilhemMBED 0:a7c449cd2d5a 116 #define INITIAL_SP (0x10008000UL)
guilhemMBED 0:a7c449cd2d5a 117 #endif
guilhemMBED 0:a7c449cd2d5a 118
guilhemMBED 0:a7c449cd2d5a 119 // RTX 4 only config below, for backward-compability
guilhemMBED 0:a7c449cd2d5a 120
guilhemMBED 0:a7c449cd2d5a 121 #ifndef OS_TASKCNT
guilhemMBED 0:a7c449cd2d5a 122 #define OS_TASKCNT 14
guilhemMBED 0:a7c449cd2d5a 123 #endif
guilhemMBED 0:a7c449cd2d5a 124 #ifndef OS_MAINSTKSIZE
guilhemMBED 0:a7c449cd2d5a 125 #define OS_MAINSTKSIZE 256
guilhemMBED 0:a7c449cd2d5a 126 #endif
guilhemMBED 0:a7c449cd2d5a 127 #ifndef OS_CLOCK
guilhemMBED 0:a7c449cd2d5a 128 #define OS_CLOCK 96000000
guilhemMBED 0:a7c449cd2d5a 129 #endif
guilhemMBED 0:a7c449cd2d5a 130
guilhemMBED 0:a7c449cd2d5a 131 #elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
guilhemMBED 0:a7c449cd2d5a 132
guilhemMBED 0:a7c449cd2d5a 133 #ifndef INITIAL_SP
guilhemMBED 0:a7c449cd2d5a 134 #define INITIAL_SP (0x10010000UL)
guilhemMBED 0:a7c449cd2d5a 135 #endif
guilhemMBED 0:a7c449cd2d5a 136
guilhemMBED 0:a7c449cd2d5a 137 // RTX 4 only config below, for backward-compability
guilhemMBED 0:a7c449cd2d5a 138
guilhemMBED 0:a7c449cd2d5a 139 #ifndef OS_TASKCNT
guilhemMBED 0:a7c449cd2d5a 140 #define OS_TASKCNT 14
guilhemMBED 0:a7c449cd2d5a 141 #endif
guilhemMBED 0:a7c449cd2d5a 142 #ifndef OS_MAINSTKSIZE
guilhemMBED 0:a7c449cd2d5a 143 #define OS_MAINSTKSIZE 256
guilhemMBED 0:a7c449cd2d5a 144 #endif
guilhemMBED 0:a7c449cd2d5a 145 #ifndef OS_CLOCK
guilhemMBED 0:a7c449cd2d5a 146 #define OS_CLOCK 120000000
guilhemMBED 0:a7c449cd2d5a 147 #endif
guilhemMBED 0:a7c449cd2d5a 148
guilhemMBED 0:a7c449cd2d5a 149 #elif defined(TARGET_LPC4330) || defined(TARGET_LPC4337)
guilhemMBED 0:a7c449cd2d5a 150
guilhemMBED 0:a7c449cd2d5a 151 #ifndef INITIAL_SP
guilhemMBED 0:a7c449cd2d5a 152 #define INITIAL_SP (0x10008000UL)
guilhemMBED 0:a7c449cd2d5a 153 #endif
guilhemMBED 0:a7c449cd2d5a 154
guilhemMBED 0:a7c449cd2d5a 155 // RTX 4 only config below, for backward-compability
guilhemMBED 0:a7c449cd2d5a 156
guilhemMBED 0:a7c449cd2d5a 157 #ifndef OS_TASKCNT
guilhemMBED 0:a7c449cd2d5a 158 #define OS_TASKCNT 14
guilhemMBED 0:a7c449cd2d5a 159 #endif
guilhemMBED 0:a7c449cd2d5a 160 #ifndef OS_MAINSTKSIZE
guilhemMBED 0:a7c449cd2d5a 161 #define OS_MAINSTKSIZE 256
guilhemMBED 0:a7c449cd2d5a 162 #endif
guilhemMBED 0:a7c449cd2d5a 163 #ifndef OS_CLOCK
guilhemMBED 0:a7c449cd2d5a 164 #define OS_CLOCK 204000000
guilhemMBED 0:a7c449cd2d5a 165 #endif
guilhemMBED 0:a7c449cd2d5a 166
guilhemMBED 0:a7c449cd2d5a 167 #elif defined(TARGET_LPC812)
guilhemMBED 0:a7c449cd2d5a 168
guilhemMBED 0:a7c449cd2d5a 169 #ifndef INITIAL_SP
guilhemMBED 0:a7c449cd2d5a 170 #define INITIAL_SP (0x10001000UL)
guilhemMBED 0:a7c449cd2d5a 171 #endif
guilhemMBED 0:a7c449cd2d5a 172
guilhemMBED 0:a7c449cd2d5a 173 // RTX 4 only config below, for backward-compability
guilhemMBED 0:a7c449cd2d5a 174
guilhemMBED 0:a7c449cd2d5a 175 #ifndef OS_TASKCNT
guilhemMBED 0:a7c449cd2d5a 176 #define OS_TASKCNT 6
guilhemMBED 0:a7c449cd2d5a 177 #endif
guilhemMBED 0:a7c449cd2d5a 178 #ifndef OS_MAINSTKSIZE
guilhemMBED 0:a7c449cd2d5a 179 #define OS_MAINSTKSIZE 128
guilhemMBED 0:a7c449cd2d5a 180 #endif
guilhemMBED 0:a7c449cd2d5a 181 #ifndef OS_CLOCK
guilhemMBED 0:a7c449cd2d5a 182 #define OS_CLOCK 36000000
guilhemMBED 0:a7c449cd2d5a 183 #endif
guilhemMBED 0:a7c449cd2d5a 184
guilhemMBED 0:a7c449cd2d5a 185 #elif defined(TARGET_LPC824) || defined(TARGET_SSCI824)
guilhemMBED 0:a7c449cd2d5a 186
guilhemMBED 0:a7c449cd2d5a 187 #ifndef INITIAL_SP
guilhemMBED 0:a7c449cd2d5a 188 #define INITIAL_SP (0x10002000UL)
guilhemMBED 0:a7c449cd2d5a 189 #endif
guilhemMBED 0:a7c449cd2d5a 190
guilhemMBED 0:a7c449cd2d5a 191 // RTX 4 only config below, for backward-compability
guilhemMBED 0:a7c449cd2d5a 192
guilhemMBED 0:a7c449cd2d5a 193 #ifndef OS_TASKCNT
guilhemMBED 0:a7c449cd2d5a 194 #define OS_TASKCNT 6
guilhemMBED 0:a7c449cd2d5a 195 #endif
guilhemMBED 0:a7c449cd2d5a 196 #ifndef OS_MAINSTKSIZE
guilhemMBED 0:a7c449cd2d5a 197 #define OS_MAINSTKSIZE 128
guilhemMBED 0:a7c449cd2d5a 198 #endif
guilhemMBED 0:a7c449cd2d5a 199 #ifndef OS_CLOCK
guilhemMBED 0:a7c449cd2d5a 200 #define OS_CLOCK 30000000
guilhemMBED 0:a7c449cd2d5a 201 #endif
guilhemMBED 0:a7c449cd2d5a 202
guilhemMBED 0:a7c449cd2d5a 203 #endif
guilhemMBED 0:a7c449cd2d5a 204
guilhemMBED 0:a7c449cd2d5a 205 #endif // MBED_MBED_RTX_H