Team DIANA / Mbed OS Scientific_RTOS

Complete library for whole scientific pre-final

Dependencies:   BOX_1

ENVIROMENTAL/TSL2561.h@5:b0fa65791218, 2019-09-05 (annotated)

Committer:
Alessio_Zaino
Date:
Thu Sep 05 20:56:11 2019 +0000
Revision:
5:b0fa65791218
Parent:
4:f693e434d21c 
final

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Alessio_Zaino 4:f693e434d21c 1
Alessio_Zaino 4:f693e434d21c 2 #ifndef _TSL2561_H_
Alessio_Zaino 4:f693e434d21c 3 #define _TSL2561_H_
Alessio_Zaino 4:f693e434d21c 4
Alessio_Zaino 4:f693e434d21c 5 #include "mbed.h"
Alessio_Zaino 4:f693e434d21c 6
Alessio_Zaino 4:f693e434d21c 7 #define TSL2561_I2C_PINNAME_SDA I2C_SDA
Alessio_Zaino 4:f693e434d21c 8 #define TSL2561_I2C_PINNAME_SCL I2C_SCL
Alessio_Zaino 4:f693e434d21c 9
Alessio_Zaino 4:f693e434d21c 10 #define TSL2561_VISIBLE 2 // channel 0 - channel 1
Alessio_Zaino 4:f693e434d21c 11 #define TSL2561_INFRARED 1 // channel 1
Alessio_Zaino 4:f693e434d21c 12 #define TSL2561_FULLSPECTRUM 0 // channel 0
Alessio_Zaino 4:f693e434d21c 13
Alessio_Zaino 4:f693e434d21c 14 // 3 i2c address options!
Alessio_Zaino 4:f693e434d21c 15 #define TSL2561_ADDR_LOW 0x29
Alessio_Zaino 4:f693e434d21c 16 #define TSL2561_ADDR_FLOAT 0x39
Alessio_Zaino 4:f693e434d21c 17 #define TSL2561_ADDR_HIGH 0x49
Alessio_Zaino 4:f693e434d21c 18
Alessio_Zaino 4:f693e434d21c 19 // Lux calculations differ slightly for CS package
Alessio_Zaino 4:f693e434d21c 20 //#define TSL2561_PACKAGE_CS
Alessio_Zaino 4:f693e434d21c 21 #define TSL2561_PACKAGE_T_FN_CL
Alessio_Zaino 4:f693e434d21c 22
Alessio_Zaino 4:f693e434d21c 23 #define TSL2561_READBIT (0x01)
Alessio_Zaino 4:f693e434d21c 24
Alessio_Zaino 4:f693e434d21c 25 #define TSL2561_COMMAND_BIT (0x80) // Must be 1
Alessio_Zaino 4:f693e434d21c 26 #define TSL2561_CLEAR_BIT (0x40) // Clears any pending interrupt (write 1 to clear)
Alessio_Zaino 4:f693e434d21c 27 #define TSL2561_WORD_BIT (0x20) // 1 = read/write word (rather than byte)
Alessio_Zaino 4:f693e434d21c 28 #define TSL2561_BLOCK_BIT (0x10) // 1 = using block read/write
Alessio_Zaino 4:f693e434d21c 29
Alessio_Zaino 4:f693e434d21c 30 #define TSL2561_CONTROL_POWERON (0x03)
Alessio_Zaino 4:f693e434d21c 31 #define TSL2561_CONTROL_POWEROFF (0x00)
Alessio_Zaino 4:f693e434d21c 32
Alessio_Zaino 4:f693e434d21c 33 #define TSL2561_LUX_LUXSCALE (14) // Scale by 2^14
Alessio_Zaino 4:f693e434d21c 34 #define TSL2561_LUX_RATIOSCALE (9) // Scale ratio by 2^9
Alessio_Zaino 4:f693e434d21c 35 #define TSL2561_LUX_CHSCALE (10) // Scale channel values by 2^10
Alessio_Zaino 4:f693e434d21c 36 #define TSL2561_LUX_CHSCALE_TINT0 (0x7517) // 322/11 * 2^TSL2561_LUX_CHSCALE
Alessio_Zaino 4:f693e434d21c 37 #define TSL2561_LUX_CHSCALE_TINT1 (0x0FE7) // 322/81 * 2^TSL2561_LUX_CHSCALE
Alessio_Zaino 4:f693e434d21c 38
Alessio_Zaino 4:f693e434d21c 39 // T, FN and CL package values
Alessio_Zaino 4:f693e434d21c 40 #define TSL2561_LUX_K1T (0x0040) // 0.125 * 2^RATIO_SCALE
Alessio_Zaino 4:f693e434d21c 41 #define TSL2561_LUX_B1T (0x01f2) // 0.0304 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 42 #define TSL2561_LUX_M1T (0x01be) // 0.0272 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 43 #define TSL2561_LUX_K2T (0x0080) // 0.250 * 2^RATIO_SCALE
Alessio_Zaino 4:f693e434d21c 44 #define TSL2561_LUX_B2T (0x0214) // 0.0325 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 45 #define TSL2561_LUX_M2T (0x02d1) // 0.0440 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 46 #define TSL2561_LUX_K3T (0x00c0) // 0.375 * 2^RATIO_SCALE
Alessio_Zaino 4:f693e434d21c 47 #define TSL2561_LUX_B3T (0x023f) // 0.0351 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 48 #define TSL2561_LUX_M3T (0x037b) // 0.0544 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 49 #define TSL2561_LUX_K4T (0x0100) // 0.50 * 2^RATIO_SCALE
Alessio_Zaino 4:f693e434d21c 50 #define TSL2561_LUX_B4T (0x0270) // 0.0381 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 51 #define TSL2561_LUX_M4T (0x03fe) // 0.0624 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 52 #define TSL2561_LUX_K5T (0x0138) // 0.61 * 2^RATIO_SCALE
Alessio_Zaino 4:f693e434d21c 53 #define TSL2561_LUX_B5T (0x016f) // 0.0224 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 54 #define TSL2561_LUX_M5T (0x01fc) // 0.0310 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 55 #define TSL2561_LUX_K6T (0x019a) // 0.80 * 2^RATIO_SCALE
Alessio_Zaino 4:f693e434d21c 56 #define TSL2561_LUX_B6T (0x00d2) // 0.0128 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 57 #define TSL2561_LUX_M6T (0x00fb) // 0.0153 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 58 #define TSL2561_LUX_K7T (0x029a) // 1.3 * 2^RATIO_SCALE
Alessio_Zaino 4:f693e434d21c 59 #define TSL2561_LUX_B7T (0x0018) // 0.00146 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 60 #define TSL2561_LUX_M7T (0x0012) // 0.00112 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 61 #define TSL2561_LUX_K8T (0x029a) // 1.3 * 2^RATIO_SCALE
Alessio_Zaino 4:f693e434d21c 62 #define TSL2561_LUX_B8T (0x0000) // 0.000 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 63 #define TSL2561_LUX_M8T (0x0000) // 0.000 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 64
Alessio_Zaino 4:f693e434d21c 65 // CS package values
Alessio_Zaino 4:f693e434d21c 66 #define TSL2561_LUX_K1C (0x0043) // 0.130 * 2^RATIO_SCALE
Alessio_Zaino 4:f693e434d21c 67 #define TSL2561_LUX_B1C (0x0204) // 0.0315 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 68 #define TSL2561_LUX_M1C (0x01ad) // 0.0262 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 69 #define TSL2561_LUX_K2C (0x0085) // 0.260 * 2^RATIO_SCALE
Alessio_Zaino 4:f693e434d21c 70 #define TSL2561_LUX_B2C (0x0228) // 0.0337 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 71 #define TSL2561_LUX_M2C (0x02c1) // 0.0430 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 72 #define TSL2561_LUX_K3C (0x00c8) // 0.390 * 2^RATIO_SCALE
Alessio_Zaino 4:f693e434d21c 73 #define TSL2561_LUX_B3C (0x0253) // 0.0363 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 74 #define TSL2561_LUX_M3C (0x0363) // 0.0529 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 75 #define TSL2561_LUX_K4C (0x010a) // 0.520 * 2^RATIO_SCALE
Alessio_Zaino 4:f693e434d21c 76 #define TSL2561_LUX_B4C (0x0282) // 0.0392 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 77 #define TSL2561_LUX_M4C (0x03df) // 0.0605 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 78 #define TSL2561_LUX_K5C (0x014d) // 0.65 * 2^RATIO_SCALE
Alessio_Zaino 4:f693e434d21c 79 #define TSL2561_LUX_B5C (0x0177) // 0.0229 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 80 #define TSL2561_LUX_M5C (0x01dd) // 0.0291 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 81 #define TSL2561_LUX_K6C (0x019a) // 0.80 * 2^RATIO_SCALE
Alessio_Zaino 4:f693e434d21c 82 #define TSL2561_LUX_B6C (0x0101) // 0.0157 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 83 #define TSL2561_LUX_M6C (0x0127) // 0.0180 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 84 #define TSL2561_LUX_K7C (0x029a) // 1.3 * 2^RATIO_SCALE
Alessio_Zaino 4:f693e434d21c 85 #define TSL2561_LUX_B7C (0x0037) // 0.00338 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 86 #define TSL2561_LUX_M7C (0x002b) // 0.00260 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 87 #define TSL2561_LUX_K8C (0x029a) // 1.3 * 2^RATIO_SCALE
Alessio_Zaino 4:f693e434d21c 88 #define TSL2561_LUX_B8C (0x0000) // 0.000 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 89 #define TSL2561_LUX_M8C (0x0000) // 0.000 * 2^LUX_SCALE
Alessio_Zaino 4:f693e434d21c 90
Alessio_Zaino 4:f693e434d21c 91 enum
Alessio_Zaino 4:f693e434d21c 92 {
Alessio_Zaino 4:f693e434d21c 93 TSL2561_REGISTER_CONTROL = 0x00,
Alessio_Zaino 4:f693e434d21c 94 TSL2561_REGISTER_TIMING = 0x01,
Alessio_Zaino 4:f693e434d21c 95 TSL2561_REGISTER_THRESHHOLDL_LOW = 0x02,
Alessio_Zaino 4:f693e434d21c 96 TSL2561_REGISTER_THRESHHOLDL_HIGH = 0x03,
Alessio_Zaino 4:f693e434d21c 97 TSL2561_REGISTER_THRESHHOLDH_LOW = 0x04,
Alessio_Zaino 4:f693e434d21c 98 TSL2561_REGISTER_THRESHHOLDH_HIGH = 0x05,
Alessio_Zaino 4:f693e434d21c 99 TSL2561_REGISTER_INTERRUPT = 0x06,
Alessio_Zaino 4:f693e434d21c 100 TSL2561_REGISTER_CRC = 0x08,
Alessio_Zaino 4:f693e434d21c 101 TSL2561_REGISTER_ID = 0x0A,
Alessio_Zaino 4:f693e434d21c 102 TSL2561_REGISTER_CHAN0_LOW = 0x0C,
Alessio_Zaino 4:f693e434d21c 103 TSL2561_REGISTER_CHAN0_HIGH = 0x0D,
Alessio_Zaino 4:f693e434d21c 104 TSL2561_REGISTER_CHAN1_LOW = 0x0E,
Alessio_Zaino 4:f693e434d21c 105 TSL2561_REGISTER_CHAN1_HIGH = 0x0F
Alessio_Zaino 4:f693e434d21c 106 };
Alessio_Zaino 4:f693e434d21c 107
Alessio_Zaino 4:f693e434d21c 108 typedef enum
Alessio_Zaino 4:f693e434d21c 109 {
Alessio_Zaino 4:f693e434d21c 110 TSL2561_INTEGRATIONTIME_13MS = 0x00, // 13.7ms
Alessio_Zaino 4:f693e434d21c 111 TSL2561_INTEGRATIONTIME_101MS = 0x01, // 101ms
Alessio_Zaino 4:f693e434d21c 112 TSL2561_INTEGRATIONTIME_402MS = 0x02 // 402ms
Alessio_Zaino 4:f693e434d21c 113 }
Alessio_Zaino 4:f693e434d21c 114 tsl2561IntegrationTime_t;
Alessio_Zaino 4:f693e434d21c 115
Alessio_Zaino 4:f693e434d21c 116 typedef enum
Alessio_Zaino 4:f693e434d21c 117 {
Alessio_Zaino 4:f693e434d21c 118 TSL2561_GAIN_0X = 0x00, // No gain
Alessio_Zaino 4:f693e434d21c 119 TSL2561_GAIN_16X = 0x10, // 16x gain
Alessio_Zaino 4:f693e434d21c 120 }
Alessio_Zaino 4:f693e434d21c 121 tsl2561Gain_t;
Alessio_Zaino 4:f693e434d21c 122
Alessio_Zaino 4:f693e434d21c 123 class TSL2561 {
Alessio_Zaino 4:f693e434d21c 124
Alessio_Zaino 4:f693e434d21c 125 public:
Alessio_Zaino 4:f693e434d21c 126 //---CLASS CONSTRUCTOR---//
Alessio_Zaino 4:f693e434d21c 127 TSL2561();
Alessio_Zaino 4:f693e434d21c 128 TSL2561(uint8_t addr);
Alessio_Zaino 4:f693e434d21c 129 TSL2561(PinName sda, PinName scl);
Alessio_Zaino 4:f693e434d21c 130 TSL2561(PinName sda, PinName scl, uint8_t addr);
Alessio_Zaino 4:f693e434d21c 131
Alessio_Zaino 4:f693e434d21c 132 bool begin(void);
Alessio_Zaino 4:f693e434d21c 133 void enable(void);
Alessio_Zaino 4:f693e434d21c 134 void disable(void);
Alessio_Zaino 4:f693e434d21c 135 void write8(uint8_t r, uint8_t v);
Alessio_Zaino 4:f693e434d21c 136 uint16_t read16(uint8_t reg);
Alessio_Zaino 4:f693e434d21c 137
Alessio_Zaino 4:f693e434d21c 138 uint32_t calculateLux(uint16_t ch0, uint16_t ch1);
Alessio_Zaino 4:f693e434d21c 139 void setTiming(tsl2561IntegrationTime_t integration);
Alessio_Zaino 4:f693e434d21c 140 void setGain(tsl2561Gain_t gain);
Alessio_Zaino 4:f693e434d21c 141 uint16_t getLuminosity (uint8_t channel);
Alessio_Zaino 4:f693e434d21c 142 uint32_t getFullLuminosity();
Alessio_Zaino 4:f693e434d21c 143
Alessio_Zaino 4:f693e434d21c 144 private:
Alessio_Zaino 4:f693e434d21c 145 I2C i2c;
Alessio_Zaino 4:f693e434d21c 146 int8_t _addr;
Alessio_Zaino 4:f693e434d21c 147 tsl2561IntegrationTime_t _integration;
Alessio_Zaino 4:f693e434d21c 148 tsl2561Gain_t _gain;
Alessio_Zaino 4:f693e434d21c 149
Alessio_Zaino 4:f693e434d21c 150 bool _initialized;
Alessio_Zaino 4:f693e434d21c 151 };
Alessio_Zaino 4:f693e434d21c 152 #endif