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HAL_L476/stm32l4xx_ll_fmc.c@1:d0dfbce63a89, 2017-02-24 (annotated)
- Committer:
- elmot
- Date:
- Fri Feb 24 21:13:56 2017 +0000
- Revision:
- 1:d0dfbce63a89
Ready-to-copy
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| elmot | 1:d0dfbce63a89 | 1 | /** |
| elmot | 1:d0dfbce63a89 | 2 | ****************************************************************************** |
| elmot | 1:d0dfbce63a89 | 3 | * @file stm32l4xx_ll_fmc.c |
| elmot | 1:d0dfbce63a89 | 4 | * @author MCD Application Team |
| elmot | 1:d0dfbce63a89 | 5 | * @version V1.5.1 |
| elmot | 1:d0dfbce63a89 | 6 | * @date 31-May-2016 |
| elmot | 1:d0dfbce63a89 | 7 | * @brief FMC Low Layer HAL module driver. |
| elmot | 1:d0dfbce63a89 | 8 | * This file provides firmware functions to manage the following |
| elmot | 1:d0dfbce63a89 | 9 | * functionalities of the Flexible Memory Controller (FMC) peripheral memories: |
| elmot | 1:d0dfbce63a89 | 10 | * + Initialization/de-initialization functions |
| elmot | 1:d0dfbce63a89 | 11 | * + Peripheral Control functions |
| elmot | 1:d0dfbce63a89 | 12 | * + Peripheral State functions |
| elmot | 1:d0dfbce63a89 | 13 | * |
| elmot | 1:d0dfbce63a89 | 14 | @verbatim |
| elmot | 1:d0dfbce63a89 | 15 | ============================================================================== |
| elmot | 1:d0dfbce63a89 | 16 | ##### FMC peripheral features ##### |
| elmot | 1:d0dfbce63a89 | 17 | ============================================================================== |
| elmot | 1:d0dfbce63a89 | 18 | [..] The Flexible memory controller (FMC) includes following memory controllers: |
| elmot | 1:d0dfbce63a89 | 19 | (+) The NOR/PSRAM memory controller |
| elmot | 1:d0dfbce63a89 | 20 | (+) The NAND memory controller |
| elmot | 1:d0dfbce63a89 | 21 | |
| elmot | 1:d0dfbce63a89 | 22 | [..] The FMC functional block makes the interface with synchronous and asynchronous static |
| elmot | 1:d0dfbce63a89 | 23 | memories and 16-bit PC memory cards. Its main purposes are: |
| elmot | 1:d0dfbce63a89 | 24 | (+) to translate AHB transactions into the appropriate external device protocol. |
| elmot | 1:d0dfbce63a89 | 25 | (+) to meet the access time requirements of the external memory devices. |
| elmot | 1:d0dfbce63a89 | 26 | |
| elmot | 1:d0dfbce63a89 | 27 | [..] All external memories share the addresses, data and control signals with the controller. |
| elmot | 1:d0dfbce63a89 | 28 | Each external device is accessed by means of a unique Chip Select. The FMC performs |
| elmot | 1:d0dfbce63a89 | 29 | only one access at a time to an external device. |
| elmot | 1:d0dfbce63a89 | 30 | The main features of the FMC controller are the following: |
| elmot | 1:d0dfbce63a89 | 31 | (+) Interface with static-memory mapped devices including: |
| elmot | 1:d0dfbce63a89 | 32 | (++) Static random access memory (SRAM). |
| elmot | 1:d0dfbce63a89 | 33 | (++) NOR Flash memory. |
| elmot | 1:d0dfbce63a89 | 34 | (++) PSRAM (4 memory banks). |
| elmot | 1:d0dfbce63a89 | 35 | (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of |
| elmot | 1:d0dfbce63a89 | 36 | data |
| elmot | 1:d0dfbce63a89 | 37 | (+) Independent Chip Select control for each memory bank |
| elmot | 1:d0dfbce63a89 | 38 | (+) Independent configuration for each memory bank |
| elmot | 1:d0dfbce63a89 | 39 | |
| elmot | 1:d0dfbce63a89 | 40 | @endverbatim |
| elmot | 1:d0dfbce63a89 | 41 | ****************************************************************************** |
| elmot | 1:d0dfbce63a89 | 42 | * @attention |
| elmot | 1:d0dfbce63a89 | 43 | * |
| elmot | 1:d0dfbce63a89 | 44 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| elmot | 1:d0dfbce63a89 | 45 | * |
| elmot | 1:d0dfbce63a89 | 46 | * Redistribution and use in source and binary forms, with or without modification, |
| elmot | 1:d0dfbce63a89 | 47 | * are permitted provided that the following conditions are met: |
| elmot | 1:d0dfbce63a89 | 48 | * 1. Redistributions of source code must retain the above copyright notice, |
| elmot | 1:d0dfbce63a89 | 49 | * this list of conditions and the following disclaimer. |
| elmot | 1:d0dfbce63a89 | 50 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| elmot | 1:d0dfbce63a89 | 51 | * this list of conditions and the following disclaimer in the documentation |
| elmot | 1:d0dfbce63a89 | 52 | * and/or other materials provided with the distribution. |
| elmot | 1:d0dfbce63a89 | 53 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| elmot | 1:d0dfbce63a89 | 54 | * may be used to endorse or promote products derived from this software |
| elmot | 1:d0dfbce63a89 | 55 | * without specific prior written permission. |
| elmot | 1:d0dfbce63a89 | 56 | * |
| elmot | 1:d0dfbce63a89 | 57 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| elmot | 1:d0dfbce63a89 | 58 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| elmot | 1:d0dfbce63a89 | 59 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| elmot | 1:d0dfbce63a89 | 60 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| elmot | 1:d0dfbce63a89 | 61 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| elmot | 1:d0dfbce63a89 | 62 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| elmot | 1:d0dfbce63a89 | 63 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| elmot | 1:d0dfbce63a89 | 64 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| elmot | 1:d0dfbce63a89 | 65 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| elmot | 1:d0dfbce63a89 | 66 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| elmot | 1:d0dfbce63a89 | 67 | * |
| elmot | 1:d0dfbce63a89 | 68 | ****************************************************************************** |
| elmot | 1:d0dfbce63a89 | 69 | */ |
| elmot | 1:d0dfbce63a89 | 70 | |
| elmot | 1:d0dfbce63a89 | 71 | /* Includes ------------------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 72 | #include "stm32l4xx_hal.h" |
| elmot | 1:d0dfbce63a89 | 73 | |
| elmot | 1:d0dfbce63a89 | 74 | #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
| elmot | 1:d0dfbce63a89 | 75 | |
| elmot | 1:d0dfbce63a89 | 76 | /** @addtogroup STM32L4xx_HAL_Driver |
| elmot | 1:d0dfbce63a89 | 77 | * @{ |
| elmot | 1:d0dfbce63a89 | 78 | */ |
| elmot | 1:d0dfbce63a89 | 79 | |
| elmot | 1:d0dfbce63a89 | 80 | #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) |
| elmot | 1:d0dfbce63a89 | 81 | |
| elmot | 1:d0dfbce63a89 | 82 | /** @defgroup FMC_LL FMC Low Layer |
| elmot | 1:d0dfbce63a89 | 83 | * @brief FMC driver modules |
| elmot | 1:d0dfbce63a89 | 84 | * @{ |
| elmot | 1:d0dfbce63a89 | 85 | */ |
| elmot | 1:d0dfbce63a89 | 86 | |
| elmot | 1:d0dfbce63a89 | 87 | /* Private typedef -----------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 88 | /* Private define ------------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 89 | /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants |
| elmot | 1:d0dfbce63a89 | 90 | * @{ |
| elmot | 1:d0dfbce63a89 | 91 | */ |
| elmot | 1:d0dfbce63a89 | 92 | |
| elmot | 1:d0dfbce63a89 | 93 | /* ----------------------- FMC registers bit mask --------------------------- */ |
| elmot | 1:d0dfbce63a89 | 94 | /* --- BCRx Register ---*/ |
| elmot | 1:d0dfbce63a89 | 95 | /* BCRx register clear mask */ |
| elmot | 1:d0dfbce63a89 | 96 | #define BCRx_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\ |
| elmot | 1:d0dfbce63a89 | 97 | FMC_BCRx_MTYP | FMC_BCRx_MWID |\ |
| elmot | 1:d0dfbce63a89 | 98 | FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\ |
| elmot | 1:d0dfbce63a89 | 99 | FMC_BCRx_WAITPOL | FMC_BCRx_WAITCFG |\ |
| elmot | 1:d0dfbce63a89 | 100 | FMC_BCRx_WREN | FMC_BCRx_WAITEN |\ |
| elmot | 1:d0dfbce63a89 | 101 | FMC_BCRx_EXTMOD | FMC_BCRx_ASYNCWAIT |\ |
| elmot | 1:d0dfbce63a89 | 102 | FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW |\ |
| elmot | 1:d0dfbce63a89 | 103 | FMC_BCR1_CCLKEN)) |
| elmot | 1:d0dfbce63a89 | 104 | |
| elmot | 1:d0dfbce63a89 | 105 | /* --- BTRx Register ---*/ |
| elmot | 1:d0dfbce63a89 | 106 | /* BTRx register clear mask */ |
| elmot | 1:d0dfbce63a89 | 107 | #define BTRx_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\ |
| elmot | 1:d0dfbce63a89 | 108 | FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\ |
| elmot | 1:d0dfbce63a89 | 109 | FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\ |
| elmot | 1:d0dfbce63a89 | 110 | FMC_BTRx_ACCMOD)) |
| elmot | 1:d0dfbce63a89 | 111 | |
| elmot | 1:d0dfbce63a89 | 112 | /* --- BWTRx Register ---*/ |
| elmot | 1:d0dfbce63a89 | 113 | /* BWTRx register clear mask */ |
| elmot | 1:d0dfbce63a89 | 114 | #define BWTRx_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ |
| elmot | 1:d0dfbce63a89 | 115 | FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\ |
| elmot | 1:d0dfbce63a89 | 116 | FMC_BWTRx_ACCMOD)) |
| elmot | 1:d0dfbce63a89 | 117 | |
| elmot | 1:d0dfbce63a89 | 118 | /* --- PCR Register ---*/ |
| elmot | 1:d0dfbce63a89 | 119 | /* PCR register clear mask */ |
| elmot | 1:d0dfbce63a89 | 120 | #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN |\ |
| elmot | 1:d0dfbce63a89 | 121 | FMC_PCR_PTYP | FMC_PCR_PWID |\ |
| elmot | 1:d0dfbce63a89 | 122 | FMC_PCR_ECCEN | FMC_PCR_TCLR |\ |
| elmot | 1:d0dfbce63a89 | 123 | FMC_PCR_TAR | FMC_PCR_ECCPS)) |
| elmot | 1:d0dfbce63a89 | 124 | |
| elmot | 1:d0dfbce63a89 | 125 | /* --- SR Register ---*/ |
| elmot | 1:d0dfbce63a89 | 126 | /* SR register clear mask */ |
| elmot | 1:d0dfbce63a89 | 127 | #define SR_CLEAR_MASK ((uint32_t)(FMC_SR_FEMPT)) |
| elmot | 1:d0dfbce63a89 | 128 | |
| elmot | 1:d0dfbce63a89 | 129 | /* --- PMEM Register ---*/ |
| elmot | 1:d0dfbce63a89 | 130 | /* PMEM register clear mask */ |
| elmot | 1:d0dfbce63a89 | 131 | #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\ |
| elmot | 1:d0dfbce63a89 | 132 | FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ)) |
| elmot | 1:d0dfbce63a89 | 133 | |
| elmot | 1:d0dfbce63a89 | 134 | /* --- PATT Register ---*/ |
| elmot | 1:d0dfbce63a89 | 135 | /* PATT register clear mask */ |
| elmot | 1:d0dfbce63a89 | 136 | #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\ |
| elmot | 1:d0dfbce63a89 | 137 | FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ)) |
| elmot | 1:d0dfbce63a89 | 138 | /** |
| elmot | 1:d0dfbce63a89 | 139 | * @} |
| elmot | 1:d0dfbce63a89 | 140 | */ |
| elmot | 1:d0dfbce63a89 | 141 | |
| elmot | 1:d0dfbce63a89 | 142 | /* Private macro -------------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 143 | /** @defgroup FMC_LL_Private_Macros FMC Low Layer Private Macros |
| elmot | 1:d0dfbce63a89 | 144 | * @{ |
| elmot | 1:d0dfbce63a89 | 145 | */ |
| elmot | 1:d0dfbce63a89 | 146 | |
| elmot | 1:d0dfbce63a89 | 147 | /** |
| elmot | 1:d0dfbce63a89 | 148 | * @} |
| elmot | 1:d0dfbce63a89 | 149 | */ |
| elmot | 1:d0dfbce63a89 | 150 | |
| elmot | 1:d0dfbce63a89 | 151 | /* Private variables ---------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 152 | /* Private function prototypes -----------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 153 | /* Exported functions --------------------------------------------------------*/ |
| elmot | 1:d0dfbce63a89 | 154 | |
| elmot | 1:d0dfbce63a89 | 155 | /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions |
| elmot | 1:d0dfbce63a89 | 156 | * @{ |
| elmot | 1:d0dfbce63a89 | 157 | */ |
| elmot | 1:d0dfbce63a89 | 158 | |
| elmot | 1:d0dfbce63a89 | 159 | /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions |
| elmot | 1:d0dfbce63a89 | 160 | * @brief NORSRAM Controller functions |
| elmot | 1:d0dfbce63a89 | 161 | * |
| elmot | 1:d0dfbce63a89 | 162 | @verbatim |
| elmot | 1:d0dfbce63a89 | 163 | ============================================================================== |
| elmot | 1:d0dfbce63a89 | 164 | ##### How to use NORSRAM device driver ##### |
| elmot | 1:d0dfbce63a89 | 165 | ============================================================================== |
| elmot | 1:d0dfbce63a89 | 166 | |
| elmot | 1:d0dfbce63a89 | 167 | [..] |
| elmot | 1:d0dfbce63a89 | 168 | This driver contains a set of APIs to interface with the FMC NORSRAM banks in order |
| elmot | 1:d0dfbce63a89 | 169 | to run the NORSRAM external devices. |
| elmot | 1:d0dfbce63a89 | 170 | |
| elmot | 1:d0dfbce63a89 | 171 | (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() |
| elmot | 1:d0dfbce63a89 | 172 | (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() |
| elmot | 1:d0dfbce63a89 | 173 | (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() |
| elmot | 1:d0dfbce63a89 | 174 | (+) FMC NORSRAM bank extended timing configuration using the function |
| elmot | 1:d0dfbce63a89 | 175 | FMC_NORSRAM_Extended_Timing_Init() |
| elmot | 1:d0dfbce63a89 | 176 | (+) FMC NORSRAM bank enable/disable write operation using the functions |
| elmot | 1:d0dfbce63a89 | 177 | FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() |
| elmot | 1:d0dfbce63a89 | 178 | |
| elmot | 1:d0dfbce63a89 | 179 | |
| elmot | 1:d0dfbce63a89 | 180 | @endverbatim |
| elmot | 1:d0dfbce63a89 | 181 | * @{ |
| elmot | 1:d0dfbce63a89 | 182 | */ |
| elmot | 1:d0dfbce63a89 | 183 | |
| elmot | 1:d0dfbce63a89 | 184 | /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions |
| elmot | 1:d0dfbce63a89 | 185 | * @brief Initialization and Configuration functions |
| elmot | 1:d0dfbce63a89 | 186 | * |
| elmot | 1:d0dfbce63a89 | 187 | @verbatim |
| elmot | 1:d0dfbce63a89 | 188 | ============================================================================== |
| elmot | 1:d0dfbce63a89 | 189 | ##### Initialization and de-initialization functions ##### |
| elmot | 1:d0dfbce63a89 | 190 | ============================================================================== |
| elmot | 1:d0dfbce63a89 | 191 | [..] |
| elmot | 1:d0dfbce63a89 | 192 | This section provides functions allowing to: |
| elmot | 1:d0dfbce63a89 | 193 | (+) Initialize and configure the FMC NORSRAM interface |
| elmot | 1:d0dfbce63a89 | 194 | (+) De-initialize the FMC NORSRAM interface |
| elmot | 1:d0dfbce63a89 | 195 | (+) Configure the FMC clock and associated GPIOs |
| elmot | 1:d0dfbce63a89 | 196 | |
| elmot | 1:d0dfbce63a89 | 197 | @endverbatim |
| elmot | 1:d0dfbce63a89 | 198 | * @{ |
| elmot | 1:d0dfbce63a89 | 199 | */ |
| elmot | 1:d0dfbce63a89 | 200 | |
| elmot | 1:d0dfbce63a89 | 201 | /** |
| elmot | 1:d0dfbce63a89 | 202 | * @brief Initialize the FMC_NORSRAM device according to the specified |
| elmot | 1:d0dfbce63a89 | 203 | * control parameters in the FMC_NORSRAM_InitTypeDef |
| elmot | 1:d0dfbce63a89 | 204 | * @param Device: Pointer to NORSRAM device instance |
| elmot | 1:d0dfbce63a89 | 205 | * @param Init: Pointer to NORSRAM Initialization structure |
| elmot | 1:d0dfbce63a89 | 206 | * @retval HAL status |
| elmot | 1:d0dfbce63a89 | 207 | */ |
| elmot | 1:d0dfbce63a89 | 208 | HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init) |
| elmot | 1:d0dfbce63a89 | 209 | { |
| elmot | 1:d0dfbce63a89 | 210 | uint32_t tmp; |
| elmot | 1:d0dfbce63a89 | 211 | |
| elmot | 1:d0dfbce63a89 | 212 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 213 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| elmot | 1:d0dfbce63a89 | 214 | assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); |
| elmot | 1:d0dfbce63a89 | 215 | assert_param(IS_FMC_MUX(Init->DataAddressMux)); |
| elmot | 1:d0dfbce63a89 | 216 | assert_param(IS_FMC_MEMORY(Init->MemoryType)); |
| elmot | 1:d0dfbce63a89 | 217 | assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); |
| elmot | 1:d0dfbce63a89 | 218 | assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); |
| elmot | 1:d0dfbce63a89 | 219 | assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); |
| elmot | 1:d0dfbce63a89 | 220 | assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); |
| elmot | 1:d0dfbce63a89 | 221 | assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); |
| elmot | 1:d0dfbce63a89 | 222 | assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); |
| elmot | 1:d0dfbce63a89 | 223 | assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); |
| elmot | 1:d0dfbce63a89 | 224 | assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); |
| elmot | 1:d0dfbce63a89 | 225 | assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); |
| elmot | 1:d0dfbce63a89 | 226 | assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); |
| elmot | 1:d0dfbce63a89 | 227 | assert_param(IS_FMC_PAGESIZE(Init->PageSize)); |
| elmot | 1:d0dfbce63a89 | 228 | |
| elmot | 1:d0dfbce63a89 | 229 | tmp = (uint32_t)(Init->DataAddressMux |\ |
| elmot | 1:d0dfbce63a89 | 230 | Init->MemoryType |\ |
| elmot | 1:d0dfbce63a89 | 231 | Init->MemoryDataWidth |\ |
| elmot | 1:d0dfbce63a89 | 232 | Init->BurstAccessMode |\ |
| elmot | 1:d0dfbce63a89 | 233 | Init->WaitSignalPolarity |\ |
| elmot | 1:d0dfbce63a89 | 234 | Init->WaitSignalActive |\ |
| elmot | 1:d0dfbce63a89 | 235 | Init->WriteOperation |\ |
| elmot | 1:d0dfbce63a89 | 236 | Init->WaitSignal |\ |
| elmot | 1:d0dfbce63a89 | 237 | Init->ExtendedMode |\ |
| elmot | 1:d0dfbce63a89 | 238 | Init->AsynchronousWait |\ |
| elmot | 1:d0dfbce63a89 | 239 | Init->WriteBurst |\ |
| elmot | 1:d0dfbce63a89 | 240 | Init->ContinuousClock |\ |
| elmot | 1:d0dfbce63a89 | 241 | Init->PageSize); |
| elmot | 1:d0dfbce63a89 | 242 | |
| elmot | 1:d0dfbce63a89 | 243 | /* Set NORSRAM device control parameters */ |
| elmot | 1:d0dfbce63a89 | 244 | if(Init->MemoryType == FMC_MEMORY_TYPE_NOR) |
| elmot | 1:d0dfbce63a89 | 245 | { |
| elmot | 1:d0dfbce63a89 | 246 | MODIFY_REG(Device->BTCR[Init->NSBank], BCRx_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_ENABLE |\ |
| elmot | 1:d0dfbce63a89 | 247 | tmp)); |
| elmot | 1:d0dfbce63a89 | 248 | } |
| elmot | 1:d0dfbce63a89 | 249 | else |
| elmot | 1:d0dfbce63a89 | 250 | { |
| elmot | 1:d0dfbce63a89 | 251 | MODIFY_REG(Device->BTCR[Init->NSBank], BCRx_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_DISABLE |\ |
| elmot | 1:d0dfbce63a89 | 252 | tmp)); |
| elmot | 1:d0dfbce63a89 | 253 | } |
| elmot | 1:d0dfbce63a89 | 254 | |
| elmot | 1:d0dfbce63a89 | 255 | /* Specific bits on bank1 register for bank2..4 */ |
| elmot | 1:d0dfbce63a89 | 256 | if(Init->NSBank != FMC_NORSRAM_BANK1) |
| elmot | 1:d0dfbce63a89 | 257 | { |
| elmot | 1:d0dfbce63a89 | 258 | /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ |
| elmot | 1:d0dfbce63a89 | 259 | if(Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) |
| elmot | 1:d0dfbce63a89 | 260 | { |
| elmot | 1:d0dfbce63a89 | 261 | Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE; |
| elmot | 1:d0dfbce63a89 | 262 | MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCRx_BURSTEN | FMC_BCR1_CCLKEN, (uint32_t)(Init->BurstAccessMode |\ |
| elmot | 1:d0dfbce63a89 | 263 | Init->ContinuousClock)); |
| elmot | 1:d0dfbce63a89 | 264 | } |
| elmot | 1:d0dfbce63a89 | 265 | } |
| elmot | 1:d0dfbce63a89 | 266 | |
| elmot | 1:d0dfbce63a89 | 267 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 268 | } |
| elmot | 1:d0dfbce63a89 | 269 | |
| elmot | 1:d0dfbce63a89 | 270 | |
| elmot | 1:d0dfbce63a89 | 271 | /** |
| elmot | 1:d0dfbce63a89 | 272 | * @brief DeInitialize the FMC_NORSRAM peripheral |
| elmot | 1:d0dfbce63a89 | 273 | * @param Device: Pointer to NORSRAM device instance |
| elmot | 1:d0dfbce63a89 | 274 | * @param ExDevice: Pointer to NORSRAM extended mode device instance |
| elmot | 1:d0dfbce63a89 | 275 | * @param Bank: NORSRAM bank number |
| elmot | 1:d0dfbce63a89 | 276 | * @retval HAL status |
| elmot | 1:d0dfbce63a89 | 277 | */ |
| elmot | 1:d0dfbce63a89 | 278 | HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) |
| elmot | 1:d0dfbce63a89 | 279 | { |
| elmot | 1:d0dfbce63a89 | 280 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 281 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| elmot | 1:d0dfbce63a89 | 282 | assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); |
| elmot | 1:d0dfbce63a89 | 283 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| elmot | 1:d0dfbce63a89 | 284 | |
| elmot | 1:d0dfbce63a89 | 285 | /* Disable the FMC_NORSRAM device */ |
| elmot | 1:d0dfbce63a89 | 286 | __FMC_NORSRAM_DISABLE(Device, Bank); |
| elmot | 1:d0dfbce63a89 | 287 | |
| elmot | 1:d0dfbce63a89 | 288 | /* De-initialize the FMC_NORSRAM device */ |
| elmot | 1:d0dfbce63a89 | 289 | /* FMC_NORSRAM_BANK1 */ |
| elmot | 1:d0dfbce63a89 | 290 | if(Bank == FMC_NORSRAM_BANK1) |
| elmot | 1:d0dfbce63a89 | 291 | { |
| elmot | 1:d0dfbce63a89 | 292 | Device->BTCR[Bank] = 0x000030DB; |
| elmot | 1:d0dfbce63a89 | 293 | } |
| elmot | 1:d0dfbce63a89 | 294 | /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ |
| elmot | 1:d0dfbce63a89 | 295 | else |
| elmot | 1:d0dfbce63a89 | 296 | { |
| elmot | 1:d0dfbce63a89 | 297 | Device->BTCR[Bank] = 0x000030D2; |
| elmot | 1:d0dfbce63a89 | 298 | } |
| elmot | 1:d0dfbce63a89 | 299 | |
| elmot | 1:d0dfbce63a89 | 300 | Device->BTCR[Bank + 1] = 0x0FFFFFFF; |
| elmot | 1:d0dfbce63a89 | 301 | ExDevice->BWTR[Bank] = 0x0FFFFFFF; |
| elmot | 1:d0dfbce63a89 | 302 | |
| elmot | 1:d0dfbce63a89 | 303 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 304 | } |
| elmot | 1:d0dfbce63a89 | 305 | |
| elmot | 1:d0dfbce63a89 | 306 | |
| elmot | 1:d0dfbce63a89 | 307 | /** |
| elmot | 1:d0dfbce63a89 | 308 | * @brief Initialize the FMC_NORSRAM Timing according to the specified |
| elmot | 1:d0dfbce63a89 | 309 | * parameters in the FMC_NORSRAM_TimingTypeDef |
| elmot | 1:d0dfbce63a89 | 310 | * @param Device: Pointer to NORSRAM device instance |
| elmot | 1:d0dfbce63a89 | 311 | * @param Timing: Pointer to NORSRAM Timing structure |
| elmot | 1:d0dfbce63a89 | 312 | * @param Bank: NORSRAM bank number |
| elmot | 1:d0dfbce63a89 | 313 | * @retval HAL status |
| elmot | 1:d0dfbce63a89 | 314 | */ |
| elmot | 1:d0dfbce63a89 | 315 | HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) |
| elmot | 1:d0dfbce63a89 | 316 | { |
| elmot | 1:d0dfbce63a89 | 317 | uint32_t tmpr = 0; |
| elmot | 1:d0dfbce63a89 | 318 | |
| elmot | 1:d0dfbce63a89 | 319 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 320 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| elmot | 1:d0dfbce63a89 | 321 | assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
| elmot | 1:d0dfbce63a89 | 322 | assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
| elmot | 1:d0dfbce63a89 | 323 | assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); |
| elmot | 1:d0dfbce63a89 | 324 | assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
| elmot | 1:d0dfbce63a89 | 325 | assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); |
| elmot | 1:d0dfbce63a89 | 326 | assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); |
| elmot | 1:d0dfbce63a89 | 327 | assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); |
| elmot | 1:d0dfbce63a89 | 328 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| elmot | 1:d0dfbce63a89 | 329 | |
| elmot | 1:d0dfbce63a89 | 330 | /* Set FMC_NORSRAM device timing parameters */ |
| elmot | 1:d0dfbce63a89 | 331 | MODIFY_REG(Device->BTCR[Bank + 1], \ |
| elmot | 1:d0dfbce63a89 | 332 | BTRx_CLEAR_MASK, \ |
| elmot | 1:d0dfbce63a89 | 333 | (uint32_t)(Timing->AddressSetupTime |\ |
| elmot | 1:d0dfbce63a89 | 334 | ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BTRx_ADDHLD)) |\ |
| elmot | 1:d0dfbce63a89 | 335 | ((Timing->DataSetupTime) << POSITION_VAL(FMC_BTRx_DATAST)) |\ |
| elmot | 1:d0dfbce63a89 | 336 | ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BTRx_BUSTURN)) |\ |
| elmot | 1:d0dfbce63a89 | 337 | (((Timing->CLKDivision)-1) << POSITION_VAL(FMC_BTRx_CLKDIV)) |\ |
| elmot | 1:d0dfbce63a89 | 338 | (((Timing->DataLatency)-2) << POSITION_VAL(FMC_BTRx_DATLAT)) |\ |
| elmot | 1:d0dfbce63a89 | 339 | (Timing->AccessMode))); |
| elmot | 1:d0dfbce63a89 | 340 | |
| elmot | 1:d0dfbce63a89 | 341 | /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ |
| elmot | 1:d0dfbce63a89 | 342 | if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) |
| elmot | 1:d0dfbce63a89 | 343 | { |
| elmot | 1:d0dfbce63a89 | 344 | tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << POSITION_VAL(FMC_BTRx_CLKDIV))); |
| elmot | 1:d0dfbce63a89 | 345 | tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << POSITION_VAL(FMC_BTRx_CLKDIV)); |
| elmot | 1:d0dfbce63a89 | 346 | MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1], FMC_BTRx_CLKDIV, tmpr); |
| elmot | 1:d0dfbce63a89 | 347 | } |
| elmot | 1:d0dfbce63a89 | 348 | |
| elmot | 1:d0dfbce63a89 | 349 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 350 | } |
| elmot | 1:d0dfbce63a89 | 351 | |
| elmot | 1:d0dfbce63a89 | 352 | /** |
| elmot | 1:d0dfbce63a89 | 353 | * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified |
| elmot | 1:d0dfbce63a89 | 354 | * parameters in the FMC_NORSRAM_TimingTypeDef |
| elmot | 1:d0dfbce63a89 | 355 | * @param Device: Pointer to NORSRAM device instance |
| elmot | 1:d0dfbce63a89 | 356 | * @param Timing: Pointer to NORSRAM Timing structure |
| elmot | 1:d0dfbce63a89 | 357 | * @param Bank: NORSRAM bank number |
| elmot | 1:d0dfbce63a89 | 358 | * @param ExtendedMode: FMC Extended Mode |
| elmot | 1:d0dfbce63a89 | 359 | * This parameter can be one of the following values: |
| elmot | 1:d0dfbce63a89 | 360 | * @arg FMC_EXTENDED_MODE_DISABLE |
| elmot | 1:d0dfbce63a89 | 361 | * @arg FMC_EXTENDED_MODE_ENABLE |
| elmot | 1:d0dfbce63a89 | 362 | * @retval HAL status |
| elmot | 1:d0dfbce63a89 | 363 | */ |
| elmot | 1:d0dfbce63a89 | 364 | HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) |
| elmot | 1:d0dfbce63a89 | 365 | { |
| elmot | 1:d0dfbce63a89 | 366 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 367 | assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); |
| elmot | 1:d0dfbce63a89 | 368 | |
| elmot | 1:d0dfbce63a89 | 369 | /* Set NORSRAM device timing register for write configuration, if extended mode is used */ |
| elmot | 1:d0dfbce63a89 | 370 | if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE) |
| elmot | 1:d0dfbce63a89 | 371 | { |
| elmot | 1:d0dfbce63a89 | 372 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 373 | assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); |
| elmot | 1:d0dfbce63a89 | 374 | assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
| elmot | 1:d0dfbce63a89 | 375 | assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
| elmot | 1:d0dfbce63a89 | 376 | assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); |
| elmot | 1:d0dfbce63a89 | 377 | assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
| elmot | 1:d0dfbce63a89 | 378 | assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); |
| elmot | 1:d0dfbce63a89 | 379 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| elmot | 1:d0dfbce63a89 | 380 | |
| elmot | 1:d0dfbce63a89 | 381 | /* Set NORSRAM device timing register for write configuration, if extended mode is used */ |
| elmot | 1:d0dfbce63a89 | 382 | MODIFY_REG(Device->BWTR[Bank], \ |
| elmot | 1:d0dfbce63a89 | 383 | BWTRx_CLEAR_MASK, \ |
| elmot | 1:d0dfbce63a89 | 384 | (uint32_t)(Timing->AddressSetupTime |\ |
| elmot | 1:d0dfbce63a89 | 385 | ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BTRx_ADDHLD)) |\ |
| elmot | 1:d0dfbce63a89 | 386 | ((Timing->DataSetupTime) << POSITION_VAL(FMC_BTRx_DATAST)) |\ |
| elmot | 1:d0dfbce63a89 | 387 | ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BWTRx_BUSTURN)) | \ |
| elmot | 1:d0dfbce63a89 | 388 | (Timing->AccessMode))); |
| elmot | 1:d0dfbce63a89 | 389 | } |
| elmot | 1:d0dfbce63a89 | 390 | else |
| elmot | 1:d0dfbce63a89 | 391 | { |
| elmot | 1:d0dfbce63a89 | 392 | Device->BWTR[Bank] = 0x0FFFFFFF; |
| elmot | 1:d0dfbce63a89 | 393 | } |
| elmot | 1:d0dfbce63a89 | 394 | |
| elmot | 1:d0dfbce63a89 | 395 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 396 | } |
| elmot | 1:d0dfbce63a89 | 397 | |
| elmot | 1:d0dfbce63a89 | 398 | |
| elmot | 1:d0dfbce63a89 | 399 | /** |
| elmot | 1:d0dfbce63a89 | 400 | * @} |
| elmot | 1:d0dfbce63a89 | 401 | */ |
| elmot | 1:d0dfbce63a89 | 402 | |
| elmot | 1:d0dfbce63a89 | 403 | |
| elmot | 1:d0dfbce63a89 | 404 | /** @defgroup FMC_NORSRAM_Exported_Functions_Group2 Peripheral Control functions |
| elmot | 1:d0dfbce63a89 | 405 | * @brief management functions |
| elmot | 1:d0dfbce63a89 | 406 | * |
| elmot | 1:d0dfbce63a89 | 407 | @verbatim |
| elmot | 1:d0dfbce63a89 | 408 | ============================================================================== |
| elmot | 1:d0dfbce63a89 | 409 | ##### FMC_NORSRAM Control functions ##### |
| elmot | 1:d0dfbce63a89 | 410 | ============================================================================== |
| elmot | 1:d0dfbce63a89 | 411 | [..] |
| elmot | 1:d0dfbce63a89 | 412 | This subsection provides a set of functions allowing to control dynamically |
| elmot | 1:d0dfbce63a89 | 413 | the FMC NORSRAM interface. |
| elmot | 1:d0dfbce63a89 | 414 | |
| elmot | 1:d0dfbce63a89 | 415 | @endverbatim |
| elmot | 1:d0dfbce63a89 | 416 | * @{ |
| elmot | 1:d0dfbce63a89 | 417 | */ |
| elmot | 1:d0dfbce63a89 | 418 | |
| elmot | 1:d0dfbce63a89 | 419 | /** |
| elmot | 1:d0dfbce63a89 | 420 | * @brief Enables dynamically FMC_NORSRAM write operation. |
| elmot | 1:d0dfbce63a89 | 421 | * @param Device: Pointer to NORSRAM device instance |
| elmot | 1:d0dfbce63a89 | 422 | * @param Bank: NORSRAM bank number |
| elmot | 1:d0dfbce63a89 | 423 | * @retval HAL status |
| elmot | 1:d0dfbce63a89 | 424 | */ |
| elmot | 1:d0dfbce63a89 | 425 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
| elmot | 1:d0dfbce63a89 | 426 | { |
| elmot | 1:d0dfbce63a89 | 427 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 428 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| elmot | 1:d0dfbce63a89 | 429 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| elmot | 1:d0dfbce63a89 | 430 | |
| elmot | 1:d0dfbce63a89 | 431 | /* Enable write operation */ |
| elmot | 1:d0dfbce63a89 | 432 | SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); |
| elmot | 1:d0dfbce63a89 | 433 | |
| elmot | 1:d0dfbce63a89 | 434 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 435 | } |
| elmot | 1:d0dfbce63a89 | 436 | |
| elmot | 1:d0dfbce63a89 | 437 | /** |
| elmot | 1:d0dfbce63a89 | 438 | * @brief Disables dynamically FMC_NORSRAM write operation. |
| elmot | 1:d0dfbce63a89 | 439 | * @param Device: Pointer to NORSRAM device instance |
| elmot | 1:d0dfbce63a89 | 440 | * @param Bank: NORSRAM bank number |
| elmot | 1:d0dfbce63a89 | 441 | * @retval HAL status |
| elmot | 1:d0dfbce63a89 | 442 | */ |
| elmot | 1:d0dfbce63a89 | 443 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
| elmot | 1:d0dfbce63a89 | 444 | { |
| elmot | 1:d0dfbce63a89 | 445 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 446 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| elmot | 1:d0dfbce63a89 | 447 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| elmot | 1:d0dfbce63a89 | 448 | |
| elmot | 1:d0dfbce63a89 | 449 | /* Disable write operation */ |
| elmot | 1:d0dfbce63a89 | 450 | CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); |
| elmot | 1:d0dfbce63a89 | 451 | |
| elmot | 1:d0dfbce63a89 | 452 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 453 | } |
| elmot | 1:d0dfbce63a89 | 454 | |
| elmot | 1:d0dfbce63a89 | 455 | /** |
| elmot | 1:d0dfbce63a89 | 456 | * @} |
| elmot | 1:d0dfbce63a89 | 457 | */ |
| elmot | 1:d0dfbce63a89 | 458 | |
| elmot | 1:d0dfbce63a89 | 459 | /** |
| elmot | 1:d0dfbce63a89 | 460 | * @} |
| elmot | 1:d0dfbce63a89 | 461 | */ |
| elmot | 1:d0dfbce63a89 | 462 | |
| elmot | 1:d0dfbce63a89 | 463 | /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions |
| elmot | 1:d0dfbce63a89 | 464 | * @brief NAND Controller functions |
| elmot | 1:d0dfbce63a89 | 465 | * |
| elmot | 1:d0dfbce63a89 | 466 | @verbatim |
| elmot | 1:d0dfbce63a89 | 467 | ============================================================================== |
| elmot | 1:d0dfbce63a89 | 468 | ##### How to use NAND device driver ##### |
| elmot | 1:d0dfbce63a89 | 469 | ============================================================================== |
| elmot | 1:d0dfbce63a89 | 470 | [..] |
| elmot | 1:d0dfbce63a89 | 471 | This driver contains a set of APIs to interface with the FMC NAND banks in order |
| elmot | 1:d0dfbce63a89 | 472 | to run the NAND external devices. |
| elmot | 1:d0dfbce63a89 | 473 | |
| elmot | 1:d0dfbce63a89 | 474 | (+) FMC NAND bank reset using the function FMC_NAND_DeInit() |
| elmot | 1:d0dfbce63a89 | 475 | (+) FMC NAND bank control configuration using the function FMC_NAND_Init() |
| elmot | 1:d0dfbce63a89 | 476 | (+) FMC NAND bank common space timing configuration using the function |
| elmot | 1:d0dfbce63a89 | 477 | FMC_NAND_CommonSpace_Timing_Init() |
| elmot | 1:d0dfbce63a89 | 478 | (+) FMC NAND bank attribute space timing configuration using the function |
| elmot | 1:d0dfbce63a89 | 479 | FMC_NAND_AttributeSpace_Timing_Init() |
| elmot | 1:d0dfbce63a89 | 480 | (+) FMC NAND bank enable/disable ECC correction feature using the functions |
| elmot | 1:d0dfbce63a89 | 481 | FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() |
| elmot | 1:d0dfbce63a89 | 482 | (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() |
| elmot | 1:d0dfbce63a89 | 483 | |
| elmot | 1:d0dfbce63a89 | 484 | @endverbatim |
| elmot | 1:d0dfbce63a89 | 485 | * @{ |
| elmot | 1:d0dfbce63a89 | 486 | */ |
| elmot | 1:d0dfbce63a89 | 487 | |
| elmot | 1:d0dfbce63a89 | 488 | /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions |
| elmot | 1:d0dfbce63a89 | 489 | * @brief Initialization and Configuration functions |
| elmot | 1:d0dfbce63a89 | 490 | * |
| elmot | 1:d0dfbce63a89 | 491 | @verbatim |
| elmot | 1:d0dfbce63a89 | 492 | ============================================================================== |
| elmot | 1:d0dfbce63a89 | 493 | ##### Initialization and de-initialization functions ##### |
| elmot | 1:d0dfbce63a89 | 494 | ============================================================================== |
| elmot | 1:d0dfbce63a89 | 495 | [..] |
| elmot | 1:d0dfbce63a89 | 496 | This section provides functions allowing to: |
| elmot | 1:d0dfbce63a89 | 497 | (+) Initialize and configure the FMC NAND interface |
| elmot | 1:d0dfbce63a89 | 498 | (+) De-initialize the FMC NAND interface |
| elmot | 1:d0dfbce63a89 | 499 | (+) Configure the FMC clock and associated GPIOs |
| elmot | 1:d0dfbce63a89 | 500 | |
| elmot | 1:d0dfbce63a89 | 501 | @endverbatim |
| elmot | 1:d0dfbce63a89 | 502 | * @{ |
| elmot | 1:d0dfbce63a89 | 503 | */ |
| elmot | 1:d0dfbce63a89 | 504 | |
| elmot | 1:d0dfbce63a89 | 505 | /** |
| elmot | 1:d0dfbce63a89 | 506 | * @brief Initializes the FMC_NAND device according to the specified |
| elmot | 1:d0dfbce63a89 | 507 | * control parameters in the FMC_NAND_HandleTypeDef |
| elmot | 1:d0dfbce63a89 | 508 | * @param Device: Pointer to NAND device instance |
| elmot | 1:d0dfbce63a89 | 509 | * @param Init: Pointer to NAND Initialization structure |
| elmot | 1:d0dfbce63a89 | 510 | * @retval HAL status |
| elmot | 1:d0dfbce63a89 | 511 | */ |
| elmot | 1:d0dfbce63a89 | 512 | HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) |
| elmot | 1:d0dfbce63a89 | 513 | { |
| elmot | 1:d0dfbce63a89 | 514 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 515 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| elmot | 1:d0dfbce63a89 | 516 | assert_param(IS_FMC_NAND_BANK(Init->NandBank)); |
| elmot | 1:d0dfbce63a89 | 517 | assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); |
| elmot | 1:d0dfbce63a89 | 518 | assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); |
| elmot | 1:d0dfbce63a89 | 519 | assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); |
| elmot | 1:d0dfbce63a89 | 520 | assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); |
| elmot | 1:d0dfbce63a89 | 521 | assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); |
| elmot | 1:d0dfbce63a89 | 522 | assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); |
| elmot | 1:d0dfbce63a89 | 523 | |
| elmot | 1:d0dfbce63a89 | 524 | /* Set NAND device control parameters */ |
| elmot | 1:d0dfbce63a89 | 525 | /* NAND bank 3 registers configuration */ |
| elmot | 1:d0dfbce63a89 | 526 | MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature |\ |
| elmot | 1:d0dfbce63a89 | 527 | FMC_PCR_MEMORY_TYPE_NAND |\ |
| elmot | 1:d0dfbce63a89 | 528 | Init->MemoryDataWidth |\ |
| elmot | 1:d0dfbce63a89 | 529 | Init->EccComputation |\ |
| elmot | 1:d0dfbce63a89 | 530 | Init->ECCPageSize |\ |
| elmot | 1:d0dfbce63a89 | 531 | ((Init->TCLRSetupTime) << POSITION_VAL(FMC_PCR_TCLR)) |\ |
| elmot | 1:d0dfbce63a89 | 532 | ((Init->TARSetupTime) << POSITION_VAL(FMC_PCR_TAR)))); |
| elmot | 1:d0dfbce63a89 | 533 | |
| elmot | 1:d0dfbce63a89 | 534 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 535 | |
| elmot | 1:d0dfbce63a89 | 536 | } |
| elmot | 1:d0dfbce63a89 | 537 | |
| elmot | 1:d0dfbce63a89 | 538 | /** |
| elmot | 1:d0dfbce63a89 | 539 | * @brief Initializes the FMC_NAND Common space Timing according to the specified |
| elmot | 1:d0dfbce63a89 | 540 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
| elmot | 1:d0dfbce63a89 | 541 | * @param Device: Pointer to NAND device instance |
| elmot | 1:d0dfbce63a89 | 542 | * @param Timing: Pointer to NAND timing structure |
| elmot | 1:d0dfbce63a89 | 543 | * @param Bank: NAND bank number |
| elmot | 1:d0dfbce63a89 | 544 | * @retval HAL status |
| elmot | 1:d0dfbce63a89 | 545 | */ |
| elmot | 1:d0dfbce63a89 | 546 | HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
| elmot | 1:d0dfbce63a89 | 547 | { |
| elmot | 1:d0dfbce63a89 | 548 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 549 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| elmot | 1:d0dfbce63a89 | 550 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
| elmot | 1:d0dfbce63a89 | 551 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
| elmot | 1:d0dfbce63a89 | 552 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
| elmot | 1:d0dfbce63a89 | 553 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
| elmot | 1:d0dfbce63a89 | 554 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| elmot | 1:d0dfbce63a89 | 555 | |
| elmot | 1:d0dfbce63a89 | 556 | /* Set FMC_NAND device timing parameters */ |
| elmot | 1:d0dfbce63a89 | 557 | /* NAND bank 3 registers configuration */ |
| elmot | 1:d0dfbce63a89 | 558 | MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |\ |
| elmot | 1:d0dfbce63a89 | 559 | ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEM_MEMWAIT)) |\ |
| elmot | 1:d0dfbce63a89 | 560 | ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEM_MEMHOLD)) |\ |
| elmot | 1:d0dfbce63a89 | 561 | ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEM_MEMHIZ)))); |
| elmot | 1:d0dfbce63a89 | 562 | |
| elmot | 1:d0dfbce63a89 | 563 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 564 | } |
| elmot | 1:d0dfbce63a89 | 565 | |
| elmot | 1:d0dfbce63a89 | 566 | /** |
| elmot | 1:d0dfbce63a89 | 567 | * @brief Initializes the FMC_NAND Attribute space Timing according to the specified |
| elmot | 1:d0dfbce63a89 | 568 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
| elmot | 1:d0dfbce63a89 | 569 | * @param Device: Pointer to NAND device instance |
| elmot | 1:d0dfbce63a89 | 570 | * @param Timing: Pointer to NAND timing structure |
| elmot | 1:d0dfbce63a89 | 571 | * @param Bank: NAND bank number |
| elmot | 1:d0dfbce63a89 | 572 | * @retval HAL status |
| elmot | 1:d0dfbce63a89 | 573 | */ |
| elmot | 1:d0dfbce63a89 | 574 | HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
| elmot | 1:d0dfbce63a89 | 575 | { |
| elmot | 1:d0dfbce63a89 | 576 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 577 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| elmot | 1:d0dfbce63a89 | 578 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
| elmot | 1:d0dfbce63a89 | 579 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
| elmot | 1:d0dfbce63a89 | 580 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
| elmot | 1:d0dfbce63a89 | 581 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
| elmot | 1:d0dfbce63a89 | 582 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| elmot | 1:d0dfbce63a89 | 583 | |
| elmot | 1:d0dfbce63a89 | 584 | /* Set FMC_NAND device timing parameters */ |
| elmot | 1:d0dfbce63a89 | 585 | /* NAND bank 3 registers configuration */ |
| elmot | 1:d0dfbce63a89 | 586 | MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |\ |
| elmot | 1:d0dfbce63a89 | 587 | ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEM_MEMWAIT)) |\ |
| elmot | 1:d0dfbce63a89 | 588 | ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEM_MEMHOLD)) |\ |
| elmot | 1:d0dfbce63a89 | 589 | ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEM_MEMHIZ)))); |
| elmot | 1:d0dfbce63a89 | 590 | |
| elmot | 1:d0dfbce63a89 | 591 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 592 | } |
| elmot | 1:d0dfbce63a89 | 593 | |
| elmot | 1:d0dfbce63a89 | 594 | |
| elmot | 1:d0dfbce63a89 | 595 | /** |
| elmot | 1:d0dfbce63a89 | 596 | * @brief DeInitialize the FMC_NAND device |
| elmot | 1:d0dfbce63a89 | 597 | * @param Device: Pointer to NAND device instance |
| elmot | 1:d0dfbce63a89 | 598 | * @param Bank: NAND bank number |
| elmot | 1:d0dfbce63a89 | 599 | * @retval HAL status |
| elmot | 1:d0dfbce63a89 | 600 | */ |
| elmot | 1:d0dfbce63a89 | 601 | HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) |
| elmot | 1:d0dfbce63a89 | 602 | { |
| elmot | 1:d0dfbce63a89 | 603 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 604 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| elmot | 1:d0dfbce63a89 | 605 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| elmot | 1:d0dfbce63a89 | 606 | |
| elmot | 1:d0dfbce63a89 | 607 | /* Disable the NAND Bank */ |
| elmot | 1:d0dfbce63a89 | 608 | __FMC_NAND_DISABLE(Device, Bank); |
| elmot | 1:d0dfbce63a89 | 609 | |
| elmot | 1:d0dfbce63a89 | 610 | /* Set the FMC_NAND_BANK registers to their reset values */ |
| elmot | 1:d0dfbce63a89 | 611 | WRITE_REG(Device->PCR, 0x00000018); |
| elmot | 1:d0dfbce63a89 | 612 | WRITE_REG(Device->SR, 0x00000040); |
| elmot | 1:d0dfbce63a89 | 613 | WRITE_REG(Device->PMEM, 0xFCFCFCFC); |
| elmot | 1:d0dfbce63a89 | 614 | WRITE_REG(Device->PATT, 0xFCFCFCFC); |
| elmot | 1:d0dfbce63a89 | 615 | |
| elmot | 1:d0dfbce63a89 | 616 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 617 | } |
| elmot | 1:d0dfbce63a89 | 618 | |
| elmot | 1:d0dfbce63a89 | 619 | /** |
| elmot | 1:d0dfbce63a89 | 620 | * @} |
| elmot | 1:d0dfbce63a89 | 621 | */ |
| elmot | 1:d0dfbce63a89 | 622 | |
| elmot | 1:d0dfbce63a89 | 623 | |
| elmot | 1:d0dfbce63a89 | 624 | /** @defgroup FMC_LL_NAND_Exported_Functions_Group2 FMC Low Layer Peripheral Control functions |
| elmot | 1:d0dfbce63a89 | 625 | * @brief management functions |
| elmot | 1:d0dfbce63a89 | 626 | * |
| elmot | 1:d0dfbce63a89 | 627 | @verbatim |
| elmot | 1:d0dfbce63a89 | 628 | ============================================================================== |
| elmot | 1:d0dfbce63a89 | 629 | ##### FMC_NAND Control functions ##### |
| elmot | 1:d0dfbce63a89 | 630 | ============================================================================== |
| elmot | 1:d0dfbce63a89 | 631 | [..] |
| elmot | 1:d0dfbce63a89 | 632 | This subsection provides a set of functions allowing to control dynamically |
| elmot | 1:d0dfbce63a89 | 633 | the FMC NAND interface. |
| elmot | 1:d0dfbce63a89 | 634 | |
| elmot | 1:d0dfbce63a89 | 635 | @endverbatim |
| elmot | 1:d0dfbce63a89 | 636 | * @{ |
| elmot | 1:d0dfbce63a89 | 637 | */ |
| elmot | 1:d0dfbce63a89 | 638 | |
| elmot | 1:d0dfbce63a89 | 639 | |
| elmot | 1:d0dfbce63a89 | 640 | /** |
| elmot | 1:d0dfbce63a89 | 641 | * @brief Enables dynamically FMC_NAND ECC feature. |
| elmot | 1:d0dfbce63a89 | 642 | * @param Device: Pointer to NAND device instance |
| elmot | 1:d0dfbce63a89 | 643 | * @param Bank: NAND bank number |
| elmot | 1:d0dfbce63a89 | 644 | * @retval HAL status |
| elmot | 1:d0dfbce63a89 | 645 | */ |
| elmot | 1:d0dfbce63a89 | 646 | HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
| elmot | 1:d0dfbce63a89 | 647 | { |
| elmot | 1:d0dfbce63a89 | 648 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 649 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| elmot | 1:d0dfbce63a89 | 650 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| elmot | 1:d0dfbce63a89 | 651 | |
| elmot | 1:d0dfbce63a89 | 652 | /* Enable ECC feature */ |
| elmot | 1:d0dfbce63a89 | 653 | SET_BIT(Device->PCR, FMC_PCR_ECCEN); |
| elmot | 1:d0dfbce63a89 | 654 | |
| elmot | 1:d0dfbce63a89 | 655 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 656 | } |
| elmot | 1:d0dfbce63a89 | 657 | |
| elmot | 1:d0dfbce63a89 | 658 | |
| elmot | 1:d0dfbce63a89 | 659 | /** |
| elmot | 1:d0dfbce63a89 | 660 | * @brief Disables dynamically FMC_NAND ECC feature. |
| elmot | 1:d0dfbce63a89 | 661 | * @param Device: Pointer to NAND device instance |
| elmot | 1:d0dfbce63a89 | 662 | * @param Bank: NAND bank number |
| elmot | 1:d0dfbce63a89 | 663 | * @retval HAL status |
| elmot | 1:d0dfbce63a89 | 664 | */ |
| elmot | 1:d0dfbce63a89 | 665 | HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
| elmot | 1:d0dfbce63a89 | 666 | { |
| elmot | 1:d0dfbce63a89 | 667 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 668 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| elmot | 1:d0dfbce63a89 | 669 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| elmot | 1:d0dfbce63a89 | 670 | |
| elmot | 1:d0dfbce63a89 | 671 | /* Disable ECC feature */ |
| elmot | 1:d0dfbce63a89 | 672 | CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); |
| elmot | 1:d0dfbce63a89 | 673 | |
| elmot | 1:d0dfbce63a89 | 674 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 675 | } |
| elmot | 1:d0dfbce63a89 | 676 | |
| elmot | 1:d0dfbce63a89 | 677 | /** |
| elmot | 1:d0dfbce63a89 | 678 | * @brief Disables dynamically FMC_NAND ECC feature. |
| elmot | 1:d0dfbce63a89 | 679 | * @param Device: Pointer to NAND device instance |
| elmot | 1:d0dfbce63a89 | 680 | * @param ECCval: Pointer to ECC value |
| elmot | 1:d0dfbce63a89 | 681 | * @param Bank: NAND bank number |
| elmot | 1:d0dfbce63a89 | 682 | * @param Timeout: Timeout wait value |
| elmot | 1:d0dfbce63a89 | 683 | * @retval HAL status |
| elmot | 1:d0dfbce63a89 | 684 | */ |
| elmot | 1:d0dfbce63a89 | 685 | HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) |
| elmot | 1:d0dfbce63a89 | 686 | { |
| elmot | 1:d0dfbce63a89 | 687 | uint32_t tickstart = 0; |
| elmot | 1:d0dfbce63a89 | 688 | |
| elmot | 1:d0dfbce63a89 | 689 | /* Check the parameters */ |
| elmot | 1:d0dfbce63a89 | 690 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| elmot | 1:d0dfbce63a89 | 691 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| elmot | 1:d0dfbce63a89 | 692 | |
| elmot | 1:d0dfbce63a89 | 693 | /* Get tick */ |
| elmot | 1:d0dfbce63a89 | 694 | tickstart = HAL_GetTick(); |
| elmot | 1:d0dfbce63a89 | 695 | |
| elmot | 1:d0dfbce63a89 | 696 | /* Wait until FIFO is empty */ |
| elmot | 1:d0dfbce63a89 | 697 | while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) |
| elmot | 1:d0dfbce63a89 | 698 | { |
| elmot | 1:d0dfbce63a89 | 699 | /* Check for the Timeout */ |
| elmot | 1:d0dfbce63a89 | 700 | if(Timeout != HAL_MAX_DELAY) |
| elmot | 1:d0dfbce63a89 | 701 | { |
| elmot | 1:d0dfbce63a89 | 702 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
| elmot | 1:d0dfbce63a89 | 703 | { |
| elmot | 1:d0dfbce63a89 | 704 | return HAL_TIMEOUT; |
| elmot | 1:d0dfbce63a89 | 705 | } |
| elmot | 1:d0dfbce63a89 | 706 | } |
| elmot | 1:d0dfbce63a89 | 707 | } |
| elmot | 1:d0dfbce63a89 | 708 | |
| elmot | 1:d0dfbce63a89 | 709 | /* Get the ECCR register value */ |
| elmot | 1:d0dfbce63a89 | 710 | *ECCval = (uint32_t)Device->ECCR; |
| elmot | 1:d0dfbce63a89 | 711 | |
| elmot | 1:d0dfbce63a89 | 712 | return HAL_OK; |
| elmot | 1:d0dfbce63a89 | 713 | } |
| elmot | 1:d0dfbce63a89 | 714 | |
| elmot | 1:d0dfbce63a89 | 715 | /** |
| elmot | 1:d0dfbce63a89 | 716 | * @} |
| elmot | 1:d0dfbce63a89 | 717 | */ |
| elmot | 1:d0dfbce63a89 | 718 | |
| elmot | 1:d0dfbce63a89 | 719 | /** |
| elmot | 1:d0dfbce63a89 | 720 | * @} |
| elmot | 1:d0dfbce63a89 | 721 | */ |
| elmot | 1:d0dfbce63a89 | 722 | |
| elmot | 1:d0dfbce63a89 | 723 | /** |
| elmot | 1:d0dfbce63a89 | 724 | * @} |
| elmot | 1:d0dfbce63a89 | 725 | */ |
| elmot | 1:d0dfbce63a89 | 726 | |
| elmot | 1:d0dfbce63a89 | 727 | /** |
| elmot | 1:d0dfbce63a89 | 728 | * @} |
| elmot | 1:d0dfbce63a89 | 729 | */ |
| elmot | 1:d0dfbce63a89 | 730 | |
| elmot | 1:d0dfbce63a89 | 731 | /** |
| elmot | 1:d0dfbce63a89 | 732 | * @} |
| elmot | 1:d0dfbce63a89 | 733 | */ |
| elmot | 1:d0dfbce63a89 | 734 | |
| elmot | 1:d0dfbce63a89 | 735 | #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED */ |
| elmot | 1:d0dfbce63a89 | 736 | |
| elmot | 1:d0dfbce63a89 | 737 | /** |
| elmot | 1:d0dfbce63a89 | 738 | * @} |
| elmot | 1:d0dfbce63a89 | 739 | */ |
| elmot | 1:d0dfbce63a89 | 740 | |
| elmot | 1:d0dfbce63a89 | 741 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
| elmot | 1:d0dfbce63a89 | 742 | |
| elmot | 1:d0dfbce63a89 | 743 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |